pdnb3.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322
  1. /*
  2. * (C) Copyright 2006-2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Configuation settings for the PDNB3 board.
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. * (easy to change)
  14. */
  15. #define CONFIG_IXP425 1 /* This is an IXP425 CPU */
  16. #define CONFIG_PDNB3 1 /* on an PDNB3 board */
  17. #define CONFIG_MACH_TYPE 1002
  18. #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
  19. #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
  20. /*
  21. * Ethernet
  22. */
  23. #define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
  24. #define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
  25. #define CONFIG_HAS_ETH1
  26. #define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
  27. #define CONFIG_MII 1 /* MII PHY management */
  28. #define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
  29. /*
  30. * Misc configuration options
  31. */
  32. #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
  33. #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
  34. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  35. #define CONFIG_SETUP_MEMORY_TAGS 1
  36. #define CONFIG_INITRD_TAG 1
  37. /*
  38. * Size of malloc() pool
  39. */
  40. #define CONFIG_SYS_MALLOC_LEN (1 << 20)
  41. /* allow to overwrite serial and ethaddr */
  42. #define CONFIG_ENV_OVERWRITE
  43. #define CONFIG_IXP_SERIAL
  44. #define CONFIG_BAUDRATE 115200
  45. #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
  46. /*
  47. * BOOTP options
  48. */
  49. #define CONFIG_BOOTP_BOOTFILESIZE
  50. #define CONFIG_BOOTP_BOOTPATH
  51. #define CONFIG_BOOTP_GATEWAY
  52. #define CONFIG_BOOTP_HOSTNAME
  53. /*
  54. * Command line configuration.
  55. */
  56. #include <config_cmd_default.h>
  57. #define CONFIG_CMD_DHCP
  58. #define CONFIG_CMD_DATE
  59. #define CONFIG_CMD_NET
  60. #define CONFIG_CMD_MII
  61. #define CONFIG_CMD_I2C
  62. #define CONFIG_CMD_ELF
  63. #define CONFIG_CMD_PING
  64. #if !defined(CONFIG_SCPU)
  65. #define CONFIG_CMD_NAND
  66. #endif
  67. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  68. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  69. /*
  70. * Miscellaneous configurable options
  71. */
  72. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  73. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  74. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  75. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  76. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  77. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  78. #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
  79. #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
  80. #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
  81. #define CONFIG_IXP425_TIMER_CLK 66666666
  82. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  83. /***************************************************************
  84. * Platform/Board specific defines start here.
  85. ***************************************************************/
  86. /*-----------------------------------------------------------------------
  87. * Default configuration (environment varibles...)
  88. *----------------------------------------------------------------------*/
  89. #define CONFIG_PREBOOT "echo;" \
  90. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  91. "echo"
  92. #undef CONFIG_BOOTARGS
  93. #define CONFIG_EXTRA_ENV_SETTINGS \
  94. "netdev=eth0\0" \
  95. "hostname=pdnb3\0" \
  96. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  97. "nfsroot=${serverip}:${rootpath}\0" \
  98. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  99. "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
  100. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  101. ":${hostname}:${netdev}:off panic=1\0" \
  102. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
  103. "mtdparts=${mtdparts}\0" \
  104. "flash_nfs=run nfsargs addip addtty;" \
  105. "bootm ${kernel_addr}\0" \
  106. "flash_self=run ramargs addip addtty;" \
  107. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  108. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  109. "bootm\0" \
  110. "rootpath=/opt/buildroot\0" \
  111. "bootfile=/tftpboot/netbox/uImage\0" \
  112. "kernel_addr=50080000\0" \
  113. "ramdisk_addr=50200000\0" \
  114. "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
  115. "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
  116. "cp.b 100000 50000000 ${filesize};" \
  117. "setenv filesize;saveenv\0" \
  118. "upd=run load update\0" \
  119. "ipaddr=10.0.0.233\0" \
  120. "serverip=10.0.0.152\0" \
  121. "netmask=255.255.0.0\0" \
  122. "ethaddr=c6:6f:13:36:f3:81\0" \
  123. "eth1addr=c6:6f:13:36:f3:82\0" \
  124. "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
  125. "4k@508k(renv)\0" \
  126. ""
  127. #define CONFIG_BOOTCOMMAND "run net_nfs"
  128. /*
  129. * Physical Memory Map
  130. */
  131. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  132. #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
  133. #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
  134. #define CONFIG_SYS_TEXT_BASE 0x50000000
  135. #define CONFIG_SYS_FLASH_BASE 0x50000000
  136. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  137. #if defined(CONFIG_SCPU)
  138. #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
  139. #else
  140. #define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
  141. #endif
  142. /*
  143. * Expansion bus settings
  144. */
  145. #if defined(CONFIG_SCPU)
  146. #define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
  147. #else
  148. #define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
  149. #endif
  150. #define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
  151. /*
  152. * SDRAM settings
  153. */
  154. #define CONFIG_SYS_SDR_CONFIG 0x18
  155. #define CONFIG_SYS_SDR_MODE_CONFIG 0x1
  156. #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
  157. /*
  158. * FLASH and environment organization
  159. */
  160. #if defined(CONFIG_SCPU)
  161. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  162. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  163. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
  164. #endif
  165. #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
  166. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  167. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  168. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  169. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  170. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
  171. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  172. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  173. /*
  174. * The following defines are added for buggy IOP480 byte interface.
  175. * All other boards should use the standard values (CPCI405 etc.)
  176. */
  177. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  178. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  179. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  180. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  181. #define CONFIG_ENV_IS_IN_FLASH 1
  182. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
  183. #if defined(CONFIG_SCPU)
  184. /* no redundant environment on SCPU */
  185. #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  186. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  187. #else
  188. #define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
  189. #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
  190. /* Address and size of Redundant Environment Sector */
  191. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  192. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  193. #endif
  194. #if !defined(CONFIG_SCPU)
  195. /*
  196. * NAND-FLASH stuff
  197. */
  198. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  199. #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
  200. #endif
  201. /*
  202. * GPIO settings
  203. */
  204. /* FPGA program pin configuration */
  205. #define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
  206. #define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
  207. #define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
  208. #define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
  209. #define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
  210. /* other GPIO's */
  211. #define CONFIG_SYS_GPIO_RESTORE_INT 0
  212. #define CONFIG_SYS_GPIO_RESTART_INT 1
  213. #define CONFIG_SYS_GPIO_SYS_RUNNING 2
  214. #define CONFIG_SYS_GPIO_PCI_INTA 3
  215. #define CONFIG_SYS_GPIO_PCI_INTB 4
  216. #define CONFIG_SYS_GPIO_I2C_SCL 6
  217. #define CONFIG_SYS_GPIO_I2C_SDA 7
  218. #define CONFIG_SYS_GPIO_FPGA_RESET 9
  219. #define CONFIG_SYS_GPIO_CLK_33M 15
  220. /*
  221. * I2C stuff
  222. */
  223. /* enable I2C and select the hardware/software driver */
  224. #define CONFIG_SYS_I2C
  225. #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  226. #define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
  227. #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
  228. /*
  229. * Software (bit-bang) I2C driver configuration
  230. */
  231. #define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
  232. #define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
  233. #define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
  234. #define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
  235. #define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
  236. #define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
  237. #define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
  238. else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
  239. #define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
  240. else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
  241. #define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
  242. /*
  243. * I2C RTC
  244. */
  245. #if 0 /* test-only */
  246. #define CONFIG_RTC_DS1340 1
  247. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  248. #else
  249. /* M41T11 Serial Access Timekeeper(R) SRAM */
  250. #define CONFIG_RTC_M41T11 1
  251. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  252. #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
  253. #endif
  254. /*
  255. * Spartan3 FPGA configuration support
  256. */
  257. #define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
  258. #define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
  259. #define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
  260. #define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
  261. #define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
  262. #define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
  263. /*
  264. * Cache Configuration
  265. */
  266. #define CONFIG_SYS_CACHELINE_SIZE 32
  267. /* additions for new relocation code, must be added to all boards */
  268. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  269. #define CONFIG_SYS_INIT_SP_ADDR \
  270. (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
  271. #endif /* __CONFIG_H */