p3mx.h 17 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Based on original work by
  6. * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /************************************************************************
  11. * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
  12. *
  13. * The defines:
  14. * CONFIG_P3M750 or
  15. * CONFIG_P3M7448
  16. * are written into include/config.h by the "make xxx_config" command
  17. ***********************************************************************/
  18. #ifndef __CONFIG_H
  19. #define __CONFIG_H
  20. /*-----------------------------------------------------------------------
  21. * High Level Configuration Options
  22. *----------------------------------------------------------------------*/
  23. #define CONFIG_P3Mx /* used for both board versions */
  24. #define CONFIG_SYS_TEXT_BASE 0xfff00000
  25. #if defined (CONFIG_P3M750)
  26. #define CONFIG_750FX /* 750GL/GX/FX */
  27. #define CONFIG_HIGH_BATS /* High BATs supported */
  28. #define CONFIG_SYS_BOARD_NAME "P3M750"
  29. #define CONFIG_SYS_BUS_CLK 100000000
  30. #define CONFIG_SYS_TCLK 100000000
  31. #elif defined (CONFIG_P3M7448)
  32. #define CONFIG_74xx
  33. #define CONFIG_SYS_BOARD_NAME "P3M7448"
  34. #define CONFIG_SYS_BUS_CLK 133333333
  35. #define CONFIG_SYS_TCLK 133333333
  36. #endif
  37. #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
  38. /* which initialization functions to call for this board */
  39. #define CONFIG_SYS_BOARD_ASM_INIT 1
  40. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  41. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
  42. /*-----------------------------------------------------------------------
  43. * Base addresses -- Note these are effective addresses where the
  44. * actual resources get mapped (not physical addresses)
  45. *----------------------------------------------------------------------*/
  46. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  47. #ifdef CONFIG_P3M750
  48. #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
  49. #endif
  50. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  51. #if defined (CONFIG_P3M750)
  52. #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */
  53. #define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */
  54. #elif defined (CONFIG_P3M7448)
  55. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */
  56. #define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */
  57. #endif
  58. #define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */
  59. #define CONFIG_SYS_MONITOR_BASE 0xfff00000
  60. #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
  61. #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
  62. #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
  63. #define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
  64. #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */
  65. #define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
  66. /*-----------------------------------------------------------------------
  67. * Initial RAM & stack pointer (placed in internal SRAM)
  68. *----------------------------------------------------------------------*/
  69. /*
  70. * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  71. * To an unused memory region. The stack will remain in cache until RAM
  72. * is initialized
  73. */
  74. #undef CONFIG_SYS_INIT_RAM_LOCK
  75. #define CONFIG_SYS_INIT_RAM_ADDR 0x42000000
  76. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  77. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  78. /*-----------------------------------------------------------------------
  79. * Serial Port
  80. *----------------------------------------------------------------------*/
  81. #define CONFIG_MPSC /* MV64460 Serial */
  82. #define CONFIG_MPSC_PORT 0
  83. #define CONFIG_BAUDRATE 115200 /* console baudrate */
  84. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  85. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  86. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  87. /*-----------------------------------------------------------------------
  88. * Ethernet
  89. *----------------------------------------------------------------------*/
  90. /* Change the default ethernet port, use this define (options: 0, 1, 2) */
  91. #define CONFIG_SYS_ETH_PORT ETH_0
  92. #define MV_ETH_DEVS 2
  93. #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
  94. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  95. /*-----------------------------------------------------------------------
  96. * FLASH related
  97. *----------------------------------------------------------------------*/
  98. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  99. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  100. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  101. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  102. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  103. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  104. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  105. #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
  106. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  107. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  108. #if defined (CONFIG_P3M750)
  109. #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
  110. #elif defined (CONFIG_P3M7448)
  111. #define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
  112. #endif
  113. #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  114. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  115. /*-----------------------------------------------------------------------
  116. * DDR SDRAM
  117. *----------------------------------------------------------------------*/
  118. #define CONFIG_MV64460_ECC
  119. /*-----------------------------------------------------------------------
  120. * I2C
  121. *----------------------------------------------------------------------*/
  122. #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */
  123. /* I2C RTC */
  124. #define CONFIG_RTC_M41T11 1
  125. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  126. #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
  127. /*-----------------------------------------------------------------------
  128. * PCI stuff
  129. *----------------------------------------------------------------------*/
  130. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  131. #define PCI_HOST_FORCE 1 /* configure as pci host */
  132. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  133. #undef CONFIG_PCI /* include pci support */
  134. #ifdef CONFIG_PCI
  135. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  136. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  137. #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
  138. #endif /* CONFIG_PCI */
  139. /* PCI MEMORY MAP section */
  140. #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
  141. #define CONFIG_SYS_PCI0_MEM_SIZE _128M
  142. #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
  143. #define CONFIG_SYS_PCI1_MEM_SIZE _128M
  144. #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
  145. #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
  146. /* PCI I/O MAP section */
  147. #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
  148. #define CONFIG_SYS_PCI0_IO_SIZE _16M
  149. #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
  150. #define CONFIG_SYS_PCI1_IO_SIZE _16M
  151. #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
  152. #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
  153. #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
  154. #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
  155. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
  156. #define CONFIG_SYS_PCI_IDSEL 0x30
  157. #undef CONFIG_BOOTARGS
  158. #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
  159. "netdev=eth0\0" \
  160. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  161. "nfsroot=${serverip}:${rootpath}\0" \
  162. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  163. "addip=setenv bootargs ${bootargs} " \
  164. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  165. ":${hostname}:${netdev}:off panic=1\0" \
  166. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  167. "flash_nfs=run nfsargs addip addtty;" \
  168. "bootm ${kernel_addr}\0" \
  169. "flash_self=run ramargs addip addtty;" \
  170. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  171. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  172. "bootm\0" \
  173. "rootpath=/opt/eldk/ppc_6xx\0" \
  174. "u-boot=p3mx/u-boot/u-boot.bin\0" \
  175. "load=tftp 100000 ${u-boot}\0" \
  176. "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
  177. "cp.b 100000 fff00000 40000;" \
  178. "setenv filesize;saveenv\0" \
  179. "upd=run load update\0" \
  180. "serverip=11.0.0.152\0"
  181. #if defined (CONFIG_P3M750)
  182. #define CONFIG_EXTRA_ENV_SETTINGS \
  183. CONFIG_EXTRA_ENV_SETTINGS_COMMON \
  184. "hostname=p3m750\0" \
  185. "bootfile=/tftpboot/p3mx/vxWorks.st\0" \
  186. "kernel_addr=fc000000\0" \
  187. "ramdisk_addr=fc180000\0" \
  188. "vxfile=p3m750/vxWorks\0" \
  189. "vxuser=ddg\0" \
  190. "vxpass=ddg\0" \
  191. "vxtarget=target\0" \
  192. "vxflags=0x8\0" \
  193. "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
  194. "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
  195. "f=${vxflags}\0"
  196. #elif defined (CONFIG_P3M7448)
  197. #define CONFIG_EXTRA_ENV_SETTINGS \
  198. CONFIG_EXTRA_ENV_SETTINGS_COMMON \
  199. "hostname=p3m7448\0"
  200. #endif
  201. #if defined (CONFIG_P3M750)
  202. #define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
  203. #elif defined (CONFIG_P3M7448)
  204. #define CONFIG_BOOTCOMMAND " "
  205. #endif
  206. #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
  207. /*
  208. * BOOTP options
  209. */
  210. #define CONFIG_BOOTP_SUBNETMASK
  211. #define CONFIG_BOOTP_GATEWAY
  212. #define CONFIG_BOOTP_HOSTNAME
  213. #define CONFIG_BOOTP_BOOTPATH
  214. #define CONFIG_BOOTP_BOOTFILESIZE
  215. /*
  216. * Command line configuration.
  217. */
  218. #include <config_cmd_default.h>
  219. #define CONFIG_CMD_ASKENV
  220. #define CONFIG_CMD_DATE
  221. #define CONFIG_CMD_DIAG
  222. #define CONFIG_CMD_ELF
  223. #define CONFIG_CMD_I2C
  224. #define CONFIG_CMD_IRQ
  225. #define CONFIG_CMD_MII
  226. #define CONFIG_CMD_NET
  227. #define CONFIG_CMD_NFS
  228. #define CONFIG_CMD_PING
  229. #define CONFIG_CMD_REGINFO
  230. #define CONFIG_CMD_PCI
  231. #define CONFIG_CMD_CACHE
  232. #define CONFIG_CMD_SDRAM
  233. /*-----------------------------------------------------------------------
  234. * Miscellaneous configurable options
  235. *----------------------------------------------------------------------*/
  236. #define CONFIG_SYS_HUSH_PARSER
  237. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  238. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  239. #if defined(CONFIG_CMD_KGDB)
  240. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  241. #else
  242. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  243. #endif
  244. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  245. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  246. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  247. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  248. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  249. #define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */
  250. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  251. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  252. #define CONFIG_LOOPW 1 /* enable loopw command */
  253. #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  254. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  255. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  256. /*-----------------------------------------------------------------------
  257. * Marvell MV64460 config settings
  258. *----------------------------------------------------------------------*/
  259. /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
  260. #if defined (CONFIG_P3M750)
  261. #define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
  262. #elif defined (CONFIG_P3M7448)
  263. #define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
  264. #endif
  265. /*
  266. * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
  267. * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
  268. * MPP[2] NC
  269. * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
  270. * MPP[4] PCI Monarch# GPIO IN Connected to P12
  271. * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
  272. * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
  273. * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
  274. * MPP[8] Reserved Do not use
  275. * MPP[9] Reserved Do not use
  276. * MPP[10] Reserved Do not use
  277. * MPP[11] Reserved Do not use
  278. * MPP[12] Phy 0 Interrupt Int IN
  279. * MPP[13] Phy 1 Interrupt Int IN
  280. * MPP[14] NC
  281. * MPP[15] NC
  282. * MPP[16] PCI Interrupt C Int IN Connected to P11
  283. * MPP[17] PCI Interrupt D Int IN Connected to P11
  284. * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
  285. * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
  286. * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
  287. * MPP[21] NC
  288. * MPP[22] GP LED Green GPIO OUT
  289. * MPP[23] GP LED Red GPIO OUT
  290. * MPP[24] Watchdog NMI# Int OUT
  291. * MPP[25] NC
  292. * MPP[26] NC
  293. * MPP[27] PCI Interrupt A Int IN Connected to P11
  294. * MPP[28] NC
  295. * MPP[29] PCI Interrupt B Int IN Connected to P11
  296. * MPP[30] Module reset GPIO OUT Board reset
  297. * MPP[31] PCI EReady GPIO IN Connected to P12
  298. */
  299. #define CONFIG_SYS_MPP_CONTROL_0 0x00303022
  300. #define CONFIG_SYS_MPP_CONTROL_1 0x00000000
  301. #define CONFIG_SYS_MPP_CONTROL_2 0x00004000
  302. #define CONFIG_SYS_MPP_CONTROL_3 0x00000004
  303. #define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0
  304. /*----------------------------------------------------------------------
  305. * Initial BAT mappings
  306. */
  307. /* NOTES:
  308. * 1) GUARDED and WRITE_THRU not allowed in IBATS
  309. * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
  310. */
  311. /* SDRAM */
  312. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  313. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  314. #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
  315. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  316. /* init ram */
  317. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  318. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
  319. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  320. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  321. /* PCI0, PCI1 in one BAT */
  322. #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
  323. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  324. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  325. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  326. /* GT regs, bootrom, all the devices, PCI I/O */
  327. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
  328. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
  329. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  330. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  331. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  332. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  333. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  334. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  335. /* set rest out of range for Linux !!!!!!!!!!! */
  336. /* IBAT5 and DBAT5 */
  337. #define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  338. #define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  339. #define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  340. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  341. /* IBAT6 and DBAT6 */
  342. #define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  343. #define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  344. #define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  345. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  346. /* IBAT7 and DBAT7 */
  347. #define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  348. #define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  349. #define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  350. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  351. /*
  352. * For booting Linux, the board info and command line data
  353. * have to be in the first 8 MB of memory, since this is
  354. * the maximum mapped by the Linux kernel during initialization.
  355. */
  356. #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
  357. #define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
  358. /*-----------------------------------------------------------------------
  359. * Cache Configuration
  360. */
  361. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
  362. #if defined(CONFIG_CMD_KGDB)
  363. #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  364. #endif
  365. /*-----------------------------------------------------------------------
  366. * L2CR setup -- make sure this is right for your board!
  367. * look in include/mpc74xx.h for the defines used here
  368. */
  369. #define CONFIG_SYS_L2
  370. #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
  371. #define L2_INIT 0
  372. #else
  373. #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  374. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  375. #endif
  376. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  377. #ifndef __ASSEMBLY__
  378. #include <../board/Marvell/include/core.h>
  379. #endif
  380. #endif /* __CONFIG_H */