RBC823.h 14 KB

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  1. /*
  2. * (C) Copyright 2000, 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Modified by Udi Finkelstein udif@udif.com
  6. * For the RBC823 board.
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /*
  11. * board/config.h - configuration options, board specific
  12. */
  13. #ifndef __CONFIG_H
  14. #define __CONFIG_H
  15. /*
  16. * High Level Configuration Options
  17. * (easy to change)
  18. */
  19. #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
  20. #define CONFIG_RBC823 1 /* ...on a RBC823 module */
  21. #define CONFIG_SYS_TEXT_BASE 0xFFF00000
  22. #if 0
  23. #define DEBUG 1
  24. #define CONFIG_LAST_STAGE_INIT
  25. #endif
  26. #define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
  27. #define CONFIG_LCD 1 /* use LCD controller ... */
  28. #define CONFIG_MPC8XX_LCD
  29. #define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
  30. #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
  31. #undef CONFIG_8xx_CONS_SMC1
  32. #undef CONFIG_8xx_CONS_NONE
  33. #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  34. #if 1
  35. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  36. #else
  37. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  38. #endif
  39. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  40. #define CONFIG_8xx_GCLK_FREQ 48000000L
  41. #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  42. #undef CONFIG_BOOTARGS
  43. #define CONFIG_BOOTCOMMAND \
  44. "bootp; " \
  45. "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  46. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  47. "bootm"
  48. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  49. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  50. #undef CONFIG_WATCHDOG /* watchdog disabled */
  51. #define CONFIG_STATUS_LED 1 /* Status LED enabled */
  52. #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
  53. /*
  54. * BOOTP options
  55. */
  56. #define CONFIG_BOOTP_SUBNETMASK
  57. #define CONFIG_BOOTP_GATEWAY
  58. #define CONFIG_BOOTP_HOSTNAME
  59. #define CONFIG_BOOTP_BOOTPATH
  60. #define CONFIG_BOOTP_BOOTFILESIZE
  61. #undef CONFIG_MAC_PARTITION
  62. #define CONFIG_DOS_PARTITION
  63. #undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
  64. #define CONFIG_HARD_I2C
  65. #define CONFIG_SYS_I2C_SPEED 40000
  66. #define CONFIG_SYS_I2C_SLAVE 0xfe
  67. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  68. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  69. #define CONFIG_SYS_EEPROM_WRITE_BITS 4
  70. #define CONFIG_SYS_EEPROM_WRITE_DELAY_MS 10
  71. /*
  72. * Command line configuration.
  73. */
  74. #include <config_cmd_default.h>
  75. #define CONFIG_CMD_ASKENV
  76. #define CONFIG_CMD_BEDBUG
  77. #define CONFIG_CMD_BMP
  78. #define CONFIG_CMD_CACHE
  79. #define CONFIG_CMD_CDP
  80. #define CONFIG_CMD_DHCP
  81. #define CONFIG_CMD_DIAG
  82. #define CONFIG_CMD_EEPROM
  83. #define CONFIG_CMD_ELF
  84. #define CONFIG_CMD_FAT
  85. #define CONFIG_CMD_I2C
  86. #define CONFIG_CMD_IMMAP
  87. #define CONFIG_CMD_KGDB
  88. #define CONFIG_CMD_PING
  89. #define CONFIG_CMD_PORTIO
  90. #define CONFIG_CMD_REGINFO
  91. #define CONFIG_CMD_SAVES
  92. #define CONFIG_CMD_SDRAM
  93. #undef CONFIG_CMD_SETGETDCR
  94. #undef CONFIG_CMD_XIMG
  95. /*
  96. * Miscellaneous configurable options
  97. */
  98. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  99. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  100. #if defined(CONFIG_CMD_KGDB)
  101. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  102. #else
  103. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  104. #endif
  105. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  106. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  107. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  108. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  109. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  110. #define CONFIG_SYS_LOAD_ADDR 0x0100000 /* default load address */
  111. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  112. /*
  113. * Low Level Configuration Settings
  114. * (address mappings, register initial values, etc.)
  115. * You should know what you are doing if you make changes here.
  116. */
  117. /*-----------------------------------------------------------------------
  118. * Internal Memory Mapped Register
  119. */
  120. #define CONFIG_SYS_IMMR 0xFF000000
  121. /*-----------------------------------------------------------------------
  122. * Definitions for initial stack pointer and data area (in DPRAM)
  123. */
  124. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  125. #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
  126. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  127. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  128. /*-----------------------------------------------------------------------
  129. * Start addresses for the final memory configuration
  130. * (Set up by the startup code)
  131. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  132. */
  133. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  134. #define CONFIG_SYS_FLASH_BASE 0xFFF00000
  135. #if defined(DEBUG)
  136. #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
  137. #else
  138. #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
  139. #endif
  140. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  141. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  142. /*
  143. * For booting Linux, the board info and command line data
  144. * have to be in the first 8 MB of memory, since this is
  145. * the maximum mapped by the Linux kernel during initialization.
  146. */
  147. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  148. /*-----------------------------------------------------------------------
  149. * FLASH organization
  150. */
  151. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  152. #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
  153. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  154. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  155. #define CONFIG_ENV_IS_IN_FLASH 1
  156. #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
  157. #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
  158. /*-----------------------------------------------------------------------
  159. * Cache Configuration
  160. */
  161. #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  162. #if defined(CONFIG_CMD_KGDB)
  163. #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  164. #endif
  165. /*-----------------------------------------------------------------------
  166. * SYPCR - System Protection Control 11-9
  167. * SYPCR can only be written once after reset!
  168. *-----------------------------------------------------------------------
  169. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  170. */
  171. #if defined(CONFIG_WATCHDOG)
  172. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  173. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  174. #else
  175. /*
  176. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  177. */
  178. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
  179. #endif
  180. /*-----------------------------------------------------------------------
  181. * SIUMCR - SIU Module Configuration 11-6
  182. *-----------------------------------------------------------------------
  183. * PCMCIA config., multi-function pin tri-state
  184. */
  185. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
  186. /*-----------------------------------------------------------------------
  187. * TBSCR - Time Base Status and Control 11-26
  188. *-----------------------------------------------------------------------
  189. * Clear Reference Interrupt Status, Timebase freezing enabled
  190. */
  191. #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  192. /*-----------------------------------------------------------------------
  193. * RTCSC - Real-Time Clock Status and Control Register 11-27
  194. *-----------------------------------------------------------------------
  195. */
  196. #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  197. /*-----------------------------------------------------------------------
  198. * PISCR - Periodic Interrupt Status and Control 11-31
  199. *-----------------------------------------------------------------------
  200. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  201. */
  202. #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
  203. /*-----------------------------------------------------------------------
  204. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  205. *-----------------------------------------------------------------------
  206. * Reset PLL lock status sticky bit, timer expired status bit and timer
  207. * interrupt status bit
  208. *
  209. */
  210. /*
  211. * for 48 MHz, we use a 4 MHz clock * 12
  212. */
  213. #define CONFIG_SYS_PLPRCR \
  214. ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
  215. /*-----------------------------------------------------------------------
  216. * SCCR - System Clock and reset Control Register 15-27
  217. *-----------------------------------------------------------------------
  218. * Set clock output, timebase and RTC source and divider,
  219. * power management and some other internal clocks
  220. */
  221. #define SCCR_MASK SCCR_EBDF11
  222. #define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
  223. SCCR_PRQEN | SCCR_EBDF00 | \
  224. SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  225. SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
  226. SCCR_DFALCD00)
  227. #ifdef NOT_USED
  228. /*-----------------------------------------------------------------------
  229. * PCMCIA stuff
  230. *-----------------------------------------------------------------------
  231. *
  232. */
  233. #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
  234. #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
  235. #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
  236. #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
  237. #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
  238. #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  239. #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
  240. #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
  241. /*-----------------------------------------------------------------------
  242. * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  243. *-----------------------------------------------------------------------
  244. */
  245. #define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
  246. #undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
  247. #undef CONFIG_IDE_LED /* LED for ide not supported */
  248. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  249. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  250. #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  251. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  252. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
  253. /* Offset for data I/O */
  254. #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  255. /* Offset for normal register accesses */
  256. #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  257. /* Offset for alternate registers */
  258. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
  259. #endif
  260. /*-----------------------------------------------------------------------
  261. *
  262. *-----------------------------------------------------------------------
  263. *
  264. */
  265. /*#define CONFIG_SYS_DER 0x2002000F*/
  266. #define CONFIG_SYS_DER 0
  267. /*
  268. * Init Memory Controller:
  269. *
  270. * BR0/1 and OR0/1 (FLASH)
  271. */
  272. #define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
  273. #define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
  274. /* used to re-map FLASH both when starting from SRAM or FLASH:
  275. * restrict access enough to keep SRAM working (if any)
  276. * but not too much to meddle with FLASH accesses
  277. */
  278. #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
  279. /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
  280. #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
  281. #define CONFIG_SYS_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
  282. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  283. #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
  284. #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
  285. #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
  286. BR_PS_8 | BR_V)
  287. /*
  288. * BR4 and OR4 (SDRAM)
  289. *
  290. */
  291. #define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
  292. #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  293. /*
  294. * SDRAM timing:
  295. */
  296. #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM)
  297. #define CONFIG_SYS_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
  298. #define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  299. /*
  300. * Memory Periodic Timer Prescaler
  301. */
  302. /* periodic timer for refresh */
  303. #define CONFIG_SYS_MAMR_PTA 187 /* start with divider for 48 MHz */
  304. /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
  305. #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  306. #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  307. /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  308. #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  309. #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  310. /*
  311. * MAMR settings for SDRAM
  312. */
  313. /* 8 column SDRAM */
  314. #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  315. MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  316. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  317. /* 9 column SDRAM */
  318. #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  319. MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  320. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  321. /*
  322. * JFFS2 partitions
  323. *
  324. */
  325. /* No command line, one static partition, whole device */
  326. #undef CONFIG_CMD_MTDPARTS
  327. #define CONFIG_JFFS2_DEV "nor0"
  328. #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
  329. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  330. /* mtdparts command line support */
  331. /* Note: fake mtd_id used, no linux mtd map file */
  332. /*
  333. #define CONFIG_CMD_MTDPARTS
  334. #define MTDIDS_DEFAULT ""
  335. #define MTDPARTS_DEFAULT ""
  336. */
  337. #endif /* __CONFIG_H */