mpc8xxx_spi.c 4.1 KB

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  1. /*
  2. * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
  3. * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <malloc.h>
  9. #include <spi.h>
  10. #include <asm/mpc8xxx_spi.h>
  11. #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
  12. #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
  13. #define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
  14. #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
  15. #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
  16. #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
  17. #define SPI_TIMEOUT 1000
  18. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  19. unsigned int max_hz, unsigned int mode)
  20. {
  21. struct spi_slave *slave;
  22. if (!spi_cs_is_valid(bus, cs))
  23. return NULL;
  24. slave = spi_alloc_slave_base(bus, cs);
  25. if (!slave)
  26. return NULL;
  27. /*
  28. * TODO: Some of the code in spi_init() should probably move
  29. * here, or into spi_claim_bus() below.
  30. */
  31. return slave;
  32. }
  33. void spi_free_slave(struct spi_slave *slave)
  34. {
  35. free(slave);
  36. }
  37. void spi_init(void)
  38. {
  39. volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
  40. /*
  41. * SPI pins on the MPC83xx are not muxed, so all we do is initialize
  42. * some registers
  43. */
  44. spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
  45. spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
  46. (16.67MHz typ.) */
  47. spi->event = 0xffffffff; /* Clear all SPI events */
  48. spi->mask = 0x00000000; /* Mask all SPI interrupts */
  49. spi->com = 0; /* LST bit doesn't do anything, so disregard */
  50. }
  51. int spi_claim_bus(struct spi_slave *slave)
  52. {
  53. return 0;
  54. }
  55. void spi_release_bus(struct spi_slave *slave)
  56. {
  57. }
  58. int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  59. void *din, unsigned long flags)
  60. {
  61. volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
  62. unsigned int tmpdout, tmpdin, event;
  63. int numBlks = DIV_ROUND_UP(bitlen, 32);
  64. int tm, isRead = 0;
  65. unsigned char charSize = 32;
  66. debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
  67. slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
  68. if (flags & SPI_XFER_BEGIN)
  69. spi_cs_activate(slave);
  70. spi->event = 0xffffffff; /* Clear all SPI events */
  71. /* handle data in 32-bit chunks */
  72. while (numBlks--) {
  73. tmpdout = 0;
  74. charSize = (bitlen >= 32 ? 32 : bitlen);
  75. /* Shift data so it's msb-justified */
  76. tmpdout = *(u32 *) dout >> (32 - charSize);
  77. /* The LEN field of the SPMODE register is set as follows:
  78. *
  79. * Bit length setting
  80. * len <= 4 3
  81. * 4 < len <= 16 len - 1
  82. * len > 16 0
  83. */
  84. spi->mode &= ~SPI_MODE_EN;
  85. if (bitlen <= 16) {
  86. if (bitlen <= 4)
  87. spi->mode = (spi->mode & 0xff0fffff) |
  88. (3 << 20);
  89. else
  90. spi->mode = (spi->mode & 0xff0fffff) |
  91. ((bitlen - 1) << 20);
  92. } else {
  93. spi->mode = (spi->mode & 0xff0fffff);
  94. /* Set up the next iteration if sending > 32 bits */
  95. bitlen -= 32;
  96. dout += 4;
  97. }
  98. spi->mode |= SPI_MODE_EN;
  99. spi->tx = tmpdout; /* Write the data out */
  100. debug("*** spi_xfer: ... %08x written\n", tmpdout);
  101. /*
  102. * Wait for SPI transmit to get out
  103. * or time out (1 second = 1000 ms)
  104. * The NE event must be read and cleared first
  105. */
  106. for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
  107. event = spi->event;
  108. if (event & SPI_EV_NE) {
  109. tmpdin = spi->rx;
  110. spi->event |= SPI_EV_NE;
  111. isRead = 1;
  112. *(u32 *) din = (tmpdin << (32 - charSize));
  113. if (charSize == 32) {
  114. /* Advance output buffer by 32 bits */
  115. din += 4;
  116. }
  117. }
  118. /*
  119. * Only bail when we've had both NE and NF events.
  120. * This will cause timeouts on RO devices, so maybe
  121. * in the future put an arbitrary delay after writing
  122. * the device. Arbitrary delays suck, though...
  123. */
  124. if (isRead && (event & SPI_EV_NF))
  125. break;
  126. }
  127. if (tm >= SPI_TIMEOUT)
  128. puts("*** spi_xfer: Time out during SPI transfer");
  129. debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
  130. }
  131. if (flags & SPI_XFER_END)
  132. spi_cs_deactivate(slave);
  133. return 0;
  134. }