nand_base.c 90 KB

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  1. /*
  2. * drivers/mtd/nand.c
  3. *
  4. * Overview:
  5. * This is the generic MTD driver for NAND flash devices. It should be
  6. * capable of working with almost all NAND chips currently available.
  7. * Basic support for AG-AND chips is provided.
  8. *
  9. * Additional technical information is available on
  10. * http://www.linux-mtd.infradead.org/doc/nand.html
  11. *
  12. * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13. * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14. *
  15. * Credits:
  16. * David Woodhouse for adding multichip support
  17. *
  18. * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19. * rework for 2K page size chips
  20. *
  21. * TODO:
  22. * Enable cached programming for 2k page size chips
  23. * Check, if mtd->ecctype should be set to MTD_ECC_HW
  24. * if we have HW ECC support.
  25. * The AG-AND chips have nice features for speed improvement,
  26. * which are not supported yet. Read / program 4 pages in one go.
  27. * BBT table is not serialized, has to be fixed
  28. *
  29. * This program is free software; you can redistribute it and/or modify
  30. * it under the terms of the GNU General Public License version 2 as
  31. * published by the Free Software Foundation.
  32. *
  33. */
  34. #include <common.h>
  35. #define ENOTSUPP 524 /* Operation is not supported */
  36. #include <malloc.h>
  37. #include <watchdog.h>
  38. #include <linux/err.h>
  39. #include <linux/compat.h>
  40. #include <linux/mtd/mtd.h>
  41. #include <linux/mtd/nand.h>
  42. #include <linux/mtd/nand_ecc.h>
  43. #include <linux/mtd/nand_bch.h>
  44. #ifdef CONFIG_MTD_PARTITIONS
  45. #include <linux/mtd/partitions.h>
  46. #endif
  47. #include <asm/io.h>
  48. #include <asm/errno.h>
  49. /*
  50. * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  51. * a flash. NAND flash is initialized prior to interrupts so standard timers
  52. * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
  53. * which is greater than (max NAND reset time / NAND status read time).
  54. * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  55. */
  56. #ifndef CONFIG_SYS_NAND_RESET_CNT
  57. #define CONFIG_SYS_NAND_RESET_CNT 200000
  58. #endif
  59. /* Define default oob placement schemes for large and small page devices */
  60. static struct nand_ecclayout nand_oob_8 = {
  61. .eccbytes = 3,
  62. .eccpos = {0, 1, 2},
  63. .oobfree = {
  64. {.offset = 3,
  65. .length = 2},
  66. {.offset = 6,
  67. .length = 2} }
  68. };
  69. static struct nand_ecclayout nand_oob_16 = {
  70. .eccbytes = 6,
  71. .eccpos = {0, 1, 2, 3, 6, 7},
  72. .oobfree = {
  73. {.offset = 8,
  74. . length = 8} }
  75. };
  76. static struct nand_ecclayout nand_oob_64 = {
  77. .eccbytes = 24,
  78. .eccpos = {
  79. 40, 41, 42, 43, 44, 45, 46, 47,
  80. 48, 49, 50, 51, 52, 53, 54, 55,
  81. 56, 57, 58, 59, 60, 61, 62, 63},
  82. .oobfree = {
  83. {.offset = 2,
  84. .length = 38} }
  85. };
  86. static struct nand_ecclayout nand_oob_128 = {
  87. .eccbytes = 48,
  88. .eccpos = {
  89. 80, 81, 82, 83, 84, 85, 86, 87,
  90. 88, 89, 90, 91, 92, 93, 94, 95,
  91. 96, 97, 98, 99, 100, 101, 102, 103,
  92. 104, 105, 106, 107, 108, 109, 110, 111,
  93. 112, 113, 114, 115, 116, 117, 118, 119,
  94. 120, 121, 122, 123, 124, 125, 126, 127},
  95. .oobfree = {
  96. {.offset = 2,
  97. .length = 78} }
  98. };
  99. static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  100. int new_state);
  101. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  102. struct mtd_oob_ops *ops);
  103. static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
  104. static int check_offs_len(struct mtd_info *mtd,
  105. loff_t ofs, uint64_t len)
  106. {
  107. struct nand_chip *chip = mtd->priv;
  108. int ret = 0;
  109. /* Start address must align on block boundary */
  110. if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
  111. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
  112. ret = -EINVAL;
  113. }
  114. /* Length must align on block boundary */
  115. if (len & ((1 << chip->phys_erase_shift) - 1)) {
  116. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
  117. __func__);
  118. ret = -EINVAL;
  119. }
  120. return ret;
  121. }
  122. /**
  123. * nand_release_device - [GENERIC] release chip
  124. * @mtd: MTD device structure
  125. *
  126. * Deselect, release chip lock and wake up anyone waiting on the device.
  127. */
  128. static void nand_release_device(struct mtd_info *mtd)
  129. {
  130. struct nand_chip *chip = mtd->priv;
  131. /* De-select the NAND device */
  132. chip->select_chip(mtd, -1);
  133. }
  134. /**
  135. * nand_read_byte - [DEFAULT] read one byte from the chip
  136. * @mtd: MTD device structure
  137. *
  138. * Default read function for 8bit buswidth.
  139. */
  140. uint8_t nand_read_byte(struct mtd_info *mtd)
  141. {
  142. struct nand_chip *chip = mtd->priv;
  143. return readb(chip->IO_ADDR_R);
  144. }
  145. /**
  146. * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
  147. * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
  148. * @mtd: MTD device structure
  149. *
  150. * Default read function for 16bit buswidth with endianness conversion.
  151. *
  152. */
  153. static uint8_t nand_read_byte16(struct mtd_info *mtd)
  154. {
  155. struct nand_chip *chip = mtd->priv;
  156. return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
  157. }
  158. /**
  159. * nand_read_word - [DEFAULT] read one word from the chip
  160. * @mtd: MTD device structure
  161. *
  162. * Default read function for 16bit buswidth without endianness conversion.
  163. */
  164. static u16 nand_read_word(struct mtd_info *mtd)
  165. {
  166. struct nand_chip *chip = mtd->priv;
  167. return readw(chip->IO_ADDR_R);
  168. }
  169. /**
  170. * nand_select_chip - [DEFAULT] control CE line
  171. * @mtd: MTD device structure
  172. * @chipnr: chipnumber to select, -1 for deselect
  173. *
  174. * Default select function for 1 chip devices.
  175. */
  176. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  177. {
  178. struct nand_chip *chip = mtd->priv;
  179. switch (chipnr) {
  180. case -1:
  181. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  182. break;
  183. case 0:
  184. break;
  185. default:
  186. BUG();
  187. }
  188. }
  189. /**
  190. * nand_write_buf - [DEFAULT] write buffer to chip
  191. * @mtd: MTD device structure
  192. * @buf: data buffer
  193. * @len: number of bytes to write
  194. *
  195. * Default write function for 8bit buswidth.
  196. */
  197. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  198. {
  199. int i;
  200. struct nand_chip *chip = mtd->priv;
  201. for (i = 0; i < len; i++)
  202. writeb(buf[i], chip->IO_ADDR_W);
  203. }
  204. /**
  205. * nand_read_buf - [DEFAULT] read chip data into buffer
  206. * @mtd: MTD device structure
  207. * @buf: buffer to store date
  208. * @len: number of bytes to read
  209. *
  210. * Default read function for 8bit buswidth.
  211. */
  212. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  213. {
  214. int i;
  215. struct nand_chip *chip = mtd->priv;
  216. for (i = 0; i < len; i++)
  217. buf[i] = readb(chip->IO_ADDR_R);
  218. }
  219. /**
  220. * nand_verify_buf - [DEFAULT] Verify chip data against buffer
  221. * @mtd: MTD device structure
  222. * @buf: buffer containing the data to compare
  223. * @len: number of bytes to compare
  224. *
  225. * Default verify function for 8bit buswidth.
  226. */
  227. static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  228. {
  229. int i;
  230. struct nand_chip *chip = mtd->priv;
  231. for (i = 0; i < len; i++)
  232. if (buf[i] != readb(chip->IO_ADDR_R))
  233. return -EFAULT;
  234. return 0;
  235. }
  236. /**
  237. * nand_write_buf16 - [DEFAULT] write buffer to chip
  238. * @mtd: MTD device structure
  239. * @buf: data buffer
  240. * @len: number of bytes to write
  241. *
  242. * Default write function for 16bit buswidth.
  243. */
  244. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  245. {
  246. int i;
  247. struct nand_chip *chip = mtd->priv;
  248. u16 *p = (u16 *) buf;
  249. len >>= 1;
  250. for (i = 0; i < len; i++)
  251. writew(p[i], chip->IO_ADDR_W);
  252. }
  253. /**
  254. * nand_read_buf16 - [DEFAULT] read chip data into buffer
  255. * @mtd: MTD device structure
  256. * @buf: buffer to store date
  257. * @len: number of bytes to read
  258. *
  259. * Default read function for 16bit buswidth.
  260. */
  261. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  262. {
  263. int i;
  264. struct nand_chip *chip = mtd->priv;
  265. u16 *p = (u16 *) buf;
  266. len >>= 1;
  267. for (i = 0; i < len; i++)
  268. p[i] = readw(chip->IO_ADDR_R);
  269. }
  270. /**
  271. * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
  272. * @mtd: MTD device structure
  273. * @buf: buffer containing the data to compare
  274. * @len: number of bytes to compare
  275. *
  276. * Default verify function for 16bit buswidth.
  277. */
  278. static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  279. {
  280. int i;
  281. struct nand_chip *chip = mtd->priv;
  282. u16 *p = (u16 *) buf;
  283. len >>= 1;
  284. for (i = 0; i < len; i++)
  285. if (p[i] != readw(chip->IO_ADDR_R))
  286. return -EFAULT;
  287. return 0;
  288. }
  289. /**
  290. * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  291. * @mtd: MTD device structure
  292. * @ofs: offset from device start
  293. * @getchip: 0, if the chip is already selected
  294. *
  295. * Check, if the block is bad.
  296. */
  297. static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
  298. {
  299. int page, chipnr, res = 0, i = 0;
  300. struct nand_chip *chip = mtd->priv;
  301. u16 bad;
  302. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  303. ofs += mtd->erasesize - mtd->writesize;
  304. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  305. if (getchip) {
  306. chipnr = (int)(ofs >> chip->chip_shift);
  307. nand_get_device(chip, mtd, FL_READING);
  308. /* Select the NAND device */
  309. chip->select_chip(mtd, chipnr);
  310. }
  311. do {
  312. if (chip->options & NAND_BUSWIDTH_16) {
  313. chip->cmdfunc(mtd, NAND_CMD_READOOB,
  314. chip->badblockpos & 0xFE, page);
  315. bad = cpu_to_le16(chip->read_word(mtd));
  316. if (chip->badblockpos & 0x1)
  317. bad >>= 8;
  318. else
  319. bad &= 0xFF;
  320. } else {
  321. chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
  322. page);
  323. bad = chip->read_byte(mtd);
  324. }
  325. if (likely(chip->badblockbits == 8))
  326. res = bad != 0xFF;
  327. else
  328. res = hweight8(bad) < chip->badblockbits;
  329. ofs += mtd->writesize;
  330. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  331. i++;
  332. } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
  333. if (getchip)
  334. nand_release_device(mtd);
  335. return res;
  336. }
  337. /**
  338. * nand_default_block_markbad - [DEFAULT] mark a block bad
  339. * @mtd: MTD device structure
  340. * @ofs: offset from device start
  341. *
  342. * This is the default implementation, which can be overridden by a hardware
  343. * specific driver. We try operations in the following order, according to our
  344. * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
  345. * (1) erase the affected block, to allow OOB marker to be written cleanly
  346. * (2) update in-memory BBT
  347. * (3) write bad block marker to OOB area of affected block
  348. * (4) update flash-based BBT
  349. * Note that we retain the first error encountered in (3) or (4), finish the
  350. * procedures, and dump the error in the end.
  351. */
  352. static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
  353. {
  354. struct nand_chip *chip = mtd->priv;
  355. uint8_t buf[2] = { 0, 0 };
  356. int block, res, ret = 0, i = 0;
  357. int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
  358. if (write_oob) {
  359. struct erase_info einfo;
  360. /* Attempt erase before marking OOB */
  361. memset(&einfo, 0, sizeof(einfo));
  362. einfo.mtd = mtd;
  363. einfo.addr = ofs;
  364. einfo.len = 1 << chip->phys_erase_shift;
  365. nand_erase_nand(mtd, &einfo, 0);
  366. }
  367. /* Get block number */
  368. block = (int)(ofs >> chip->bbt_erase_shift);
  369. /* Mark block bad in memory-based BBT */
  370. if (chip->bbt)
  371. chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
  372. /* Write bad block marker to OOB */
  373. if (write_oob) {
  374. struct mtd_oob_ops ops;
  375. loff_t wr_ofs = ofs;
  376. nand_get_device(chip, mtd, FL_WRITING);
  377. ops.datbuf = NULL;
  378. ops.oobbuf = buf;
  379. ops.ooboffs = chip->badblockpos;
  380. if (chip->options & NAND_BUSWIDTH_16) {
  381. ops.ooboffs &= ~0x01;
  382. ops.len = ops.ooblen = 2;
  383. } else {
  384. ops.len = ops.ooblen = 1;
  385. }
  386. ops.mode = MTD_OPS_PLACE_OOB;
  387. /* Write to first/last page(s) if necessary */
  388. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  389. wr_ofs += mtd->erasesize - mtd->writesize;
  390. do {
  391. res = nand_do_write_oob(mtd, wr_ofs, &ops);
  392. if (!ret)
  393. ret = res;
  394. i++;
  395. wr_ofs += mtd->writesize;
  396. } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
  397. nand_release_device(mtd);
  398. }
  399. /* Update flash-based bad block table */
  400. if (chip->bbt_options & NAND_BBT_USE_FLASH) {
  401. res = nand_update_bbt(mtd, ofs);
  402. if (!ret)
  403. ret = res;
  404. }
  405. if (!ret)
  406. mtd->ecc_stats.badblocks++;
  407. return ret;
  408. }
  409. /**
  410. * nand_check_wp - [GENERIC] check if the chip is write protected
  411. * @mtd: MTD device structure
  412. *
  413. * Check, if the device is write protected. The function expects, that the
  414. * device is already selected.
  415. */
  416. static int nand_check_wp(struct mtd_info *mtd)
  417. {
  418. struct nand_chip *chip = mtd->priv;
  419. /* Broken xD cards report WP despite being writable */
  420. if (chip->options & NAND_BROKEN_XD)
  421. return 0;
  422. /* Check the WP bit */
  423. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  424. return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
  425. }
  426. /**
  427. * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  428. * @mtd: MTD device structure
  429. * @ofs: offset from device start
  430. * @getchip: 0, if the chip is already selected
  431. * @allowbbt: 1, if its allowed to access the bbt area
  432. *
  433. * Check, if the block is bad. Either by reading the bad block table or
  434. * calling of the scan function.
  435. */
  436. static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
  437. int allowbbt)
  438. {
  439. struct nand_chip *chip = mtd->priv;
  440. if (!(chip->options & NAND_BBT_SCANNED)) {
  441. chip->options |= NAND_BBT_SCANNED;
  442. chip->scan_bbt(mtd);
  443. }
  444. if (!chip->bbt)
  445. return chip->block_bad(mtd, ofs, getchip);
  446. /* Return info from the table */
  447. return nand_isbad_bbt(mtd, ofs, allowbbt);
  448. }
  449. /* Wait for the ready pin, after a command. The timeout is caught later. */
  450. void nand_wait_ready(struct mtd_info *mtd)
  451. {
  452. struct nand_chip *chip = mtd->priv;
  453. u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
  454. u32 time_start;
  455. time_start = get_timer(0);
  456. /* Wait until command is processed or timeout occurs */
  457. while (get_timer(time_start) < timeo) {
  458. if (chip->dev_ready)
  459. if (chip->dev_ready(mtd))
  460. break;
  461. }
  462. }
  463. /**
  464. * nand_command - [DEFAULT] Send command to NAND device
  465. * @mtd: MTD device structure
  466. * @command: the command to be sent
  467. * @column: the column address for this command, -1 if none
  468. * @page_addr: the page address for this command, -1 if none
  469. *
  470. * Send command to NAND device. This function is used for small page devices
  471. * (256/512 Bytes per page).
  472. */
  473. static void nand_command(struct mtd_info *mtd, unsigned int command,
  474. int column, int page_addr)
  475. {
  476. register struct nand_chip *chip = mtd->priv;
  477. int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
  478. uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
  479. /* Write out the command to the device */
  480. if (command == NAND_CMD_SEQIN) {
  481. int readcmd;
  482. if (column >= mtd->writesize) {
  483. /* OOB area */
  484. column -= mtd->writesize;
  485. readcmd = NAND_CMD_READOOB;
  486. } else if (column < 256) {
  487. /* First 256 bytes --> READ0 */
  488. readcmd = NAND_CMD_READ0;
  489. } else {
  490. column -= 256;
  491. readcmd = NAND_CMD_READ1;
  492. }
  493. chip->cmd_ctrl(mtd, readcmd, ctrl);
  494. ctrl &= ~NAND_CTRL_CHANGE;
  495. }
  496. chip->cmd_ctrl(mtd, command, ctrl);
  497. /* Address cycle, when necessary */
  498. ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
  499. /* Serially input address */
  500. if (column != -1) {
  501. /* Adjust columns for 16 bit buswidth */
  502. if (chip->options & NAND_BUSWIDTH_16)
  503. column >>= 1;
  504. chip->cmd_ctrl(mtd, column, ctrl);
  505. ctrl &= ~NAND_CTRL_CHANGE;
  506. }
  507. if (page_addr != -1) {
  508. chip->cmd_ctrl(mtd, page_addr, ctrl);
  509. ctrl &= ~NAND_CTRL_CHANGE;
  510. chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
  511. /* One more address cycle for devices > 32MiB */
  512. if (chip->chipsize > (32 << 20))
  513. chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
  514. }
  515. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  516. /*
  517. * Program and erase have their own busy handlers status and sequential
  518. * in needs no delay
  519. */
  520. switch (command) {
  521. case NAND_CMD_PAGEPROG:
  522. case NAND_CMD_ERASE1:
  523. case NAND_CMD_ERASE2:
  524. case NAND_CMD_SEQIN:
  525. case NAND_CMD_STATUS:
  526. return;
  527. case NAND_CMD_RESET:
  528. if (chip->dev_ready)
  529. break;
  530. udelay(chip->chip_delay);
  531. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  532. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  533. chip->cmd_ctrl(mtd,
  534. NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  535. while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
  536. (rst_sts_cnt--));
  537. return;
  538. /* This applies to read commands */
  539. default:
  540. /*
  541. * If we don't have access to the busy pin, we apply the given
  542. * command delay
  543. */
  544. if (!chip->dev_ready) {
  545. udelay(chip->chip_delay);
  546. return;
  547. }
  548. }
  549. /*
  550. * Apply this short delay always to ensure that we do wait tWB in
  551. * any case on any machine.
  552. */
  553. ndelay(100);
  554. nand_wait_ready(mtd);
  555. }
  556. /**
  557. * nand_command_lp - [DEFAULT] Send command to NAND large page device
  558. * @mtd: MTD device structure
  559. * @command: the command to be sent
  560. * @column: the column address for this command, -1 if none
  561. * @page_addr: the page address for this command, -1 if none
  562. *
  563. * Send command to NAND device. This is the version for the new large page
  564. * devices. We don't have the separate regions as we have in the small page
  565. * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
  566. */
  567. static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
  568. int column, int page_addr)
  569. {
  570. register struct nand_chip *chip = mtd->priv;
  571. uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
  572. /* Emulate NAND_CMD_READOOB */
  573. if (command == NAND_CMD_READOOB) {
  574. column += mtd->writesize;
  575. command = NAND_CMD_READ0;
  576. }
  577. /* Command latch cycle */
  578. chip->cmd_ctrl(mtd, command & 0xff,
  579. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  580. if (column != -1 || page_addr != -1) {
  581. int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
  582. /* Serially input address */
  583. if (column != -1) {
  584. /* Adjust columns for 16 bit buswidth */
  585. if (chip->options & NAND_BUSWIDTH_16)
  586. column >>= 1;
  587. chip->cmd_ctrl(mtd, column, ctrl);
  588. ctrl &= ~NAND_CTRL_CHANGE;
  589. chip->cmd_ctrl(mtd, column >> 8, ctrl);
  590. }
  591. if (page_addr != -1) {
  592. chip->cmd_ctrl(mtd, page_addr, ctrl);
  593. chip->cmd_ctrl(mtd, page_addr >> 8,
  594. NAND_NCE | NAND_ALE);
  595. /* One more address cycle for devices > 128MiB */
  596. if (chip->chipsize > (128 << 20))
  597. chip->cmd_ctrl(mtd, page_addr >> 16,
  598. NAND_NCE | NAND_ALE);
  599. }
  600. }
  601. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  602. /*
  603. * Program and erase have their own busy handlers status, sequential
  604. * in, and deplete1 need no delay.
  605. */
  606. switch (command) {
  607. case NAND_CMD_CACHEDPROG:
  608. case NAND_CMD_PAGEPROG:
  609. case NAND_CMD_ERASE1:
  610. case NAND_CMD_ERASE2:
  611. case NAND_CMD_SEQIN:
  612. case NAND_CMD_RNDIN:
  613. case NAND_CMD_STATUS:
  614. case NAND_CMD_DEPLETE1:
  615. return;
  616. case NAND_CMD_STATUS_ERROR:
  617. case NAND_CMD_STATUS_ERROR0:
  618. case NAND_CMD_STATUS_ERROR1:
  619. case NAND_CMD_STATUS_ERROR2:
  620. case NAND_CMD_STATUS_ERROR3:
  621. /* Read error status commands require only a short delay */
  622. udelay(chip->chip_delay);
  623. return;
  624. case NAND_CMD_RESET:
  625. if (chip->dev_ready)
  626. break;
  627. udelay(chip->chip_delay);
  628. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  629. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  630. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  631. NAND_NCE | NAND_CTRL_CHANGE);
  632. while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
  633. (rst_sts_cnt--));
  634. return;
  635. case NAND_CMD_RNDOUT:
  636. /* No ready / busy check necessary */
  637. chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
  638. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  639. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  640. NAND_NCE | NAND_CTRL_CHANGE);
  641. return;
  642. case NAND_CMD_READ0:
  643. chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
  644. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  645. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  646. NAND_NCE | NAND_CTRL_CHANGE);
  647. /* This applies to read commands */
  648. default:
  649. /*
  650. * If we don't have access to the busy pin, we apply the given
  651. * command delay.
  652. */
  653. if (!chip->dev_ready) {
  654. udelay(chip->chip_delay);
  655. return;
  656. }
  657. }
  658. /*
  659. * Apply this short delay always to ensure that we do wait tWB in
  660. * any case on any machine.
  661. */
  662. ndelay(100);
  663. nand_wait_ready(mtd);
  664. }
  665. /**
  666. * nand_get_device - [GENERIC] Get chip for selected access
  667. * @chip: the nand chip descriptor
  668. * @mtd: MTD device structure
  669. * @new_state: the state which is requested
  670. *
  671. * Get the device and lock it for exclusive access
  672. */
  673. static int
  674. nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
  675. {
  676. chip->state = new_state;
  677. return 0;
  678. }
  679. /**
  680. * nand_wait - [DEFAULT] wait until the command is done
  681. * @mtd: MTD device structure
  682. * @chip: NAND chip structure
  683. *
  684. * Wait for command done. This applies to erase and program only. Erase can
  685. * take up to 400ms and program up to 20ms according to general NAND and
  686. * SmartMedia specs.
  687. */
  688. static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
  689. {
  690. unsigned long timeo;
  691. int state = chip->state;
  692. u32 time_start;
  693. if (state == FL_ERASING)
  694. timeo = (CONFIG_SYS_HZ * 400) / 1000;
  695. else
  696. timeo = (CONFIG_SYS_HZ * 20) / 1000;
  697. if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
  698. chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
  699. else
  700. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  701. time_start = get_timer(0);
  702. while (1) {
  703. if (get_timer(time_start) > timeo) {
  704. printf("Timeout!");
  705. return 0x01;
  706. }
  707. if (chip->dev_ready) {
  708. if (chip->dev_ready(mtd))
  709. break;
  710. } else {
  711. if (chip->read_byte(mtd) & NAND_STATUS_READY)
  712. break;
  713. }
  714. }
  715. #ifdef PPCHAMELON_NAND_TIMER_HACK
  716. time_start = get_timer(0);
  717. while (get_timer(time_start) < 10)
  718. ;
  719. #endif /* PPCHAMELON_NAND_TIMER_HACK */
  720. return (int)chip->read_byte(mtd);
  721. }
  722. /**
  723. * nand_read_page_raw - [INTERN] read raw page data without ecc
  724. * @mtd: mtd info structure
  725. * @chip: nand chip info structure
  726. * @buf: buffer to store read data
  727. * @oob_required: caller requires OOB data read to chip->oob_poi
  728. * @page: page number to read
  729. *
  730. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  731. */
  732. static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  733. uint8_t *buf, int oob_required, int page)
  734. {
  735. chip->read_buf(mtd, buf, mtd->writesize);
  736. if (oob_required)
  737. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  738. return 0;
  739. }
  740. /**
  741. * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
  742. * @mtd: mtd info structure
  743. * @chip: nand chip info structure
  744. * @buf: buffer to store read data
  745. * @oob_required: caller requires OOB data read to chip->oob_poi
  746. * @page: page number to read
  747. *
  748. * We need a special oob layout and handling even when OOB isn't used.
  749. */
  750. static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
  751. struct nand_chip *chip, uint8_t *buf,
  752. int oob_required, int page)
  753. {
  754. int eccsize = chip->ecc.size;
  755. int eccbytes = chip->ecc.bytes;
  756. uint8_t *oob = chip->oob_poi;
  757. int steps, size;
  758. for (steps = chip->ecc.steps; steps > 0; steps--) {
  759. chip->read_buf(mtd, buf, eccsize);
  760. buf += eccsize;
  761. if (chip->ecc.prepad) {
  762. chip->read_buf(mtd, oob, chip->ecc.prepad);
  763. oob += chip->ecc.prepad;
  764. }
  765. chip->read_buf(mtd, oob, eccbytes);
  766. oob += eccbytes;
  767. if (chip->ecc.postpad) {
  768. chip->read_buf(mtd, oob, chip->ecc.postpad);
  769. oob += chip->ecc.postpad;
  770. }
  771. }
  772. size = mtd->oobsize - (oob - chip->oob_poi);
  773. if (size)
  774. chip->read_buf(mtd, oob, size);
  775. return 0;
  776. }
  777. /**
  778. * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
  779. * @mtd: mtd info structure
  780. * @chip: nand chip info structure
  781. * @buf: buffer to store read data
  782. * @oob_required: caller requires OOB data read to chip->oob_poi
  783. * @page: page number to read
  784. */
  785. static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  786. uint8_t *buf, int oob_required, int page)
  787. {
  788. int i, eccsize = chip->ecc.size;
  789. int eccbytes = chip->ecc.bytes;
  790. int eccsteps = chip->ecc.steps;
  791. uint8_t *p = buf;
  792. uint8_t *ecc_calc = chip->buffers->ecccalc;
  793. uint8_t *ecc_code = chip->buffers->ecccode;
  794. uint32_t *eccpos = chip->ecc.layout->eccpos;
  795. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  796. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  797. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  798. for (i = 0; i < chip->ecc.total; i++)
  799. ecc_code[i] = chip->oob_poi[eccpos[i]];
  800. eccsteps = chip->ecc.steps;
  801. p = buf;
  802. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  803. int stat;
  804. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  805. if (stat < 0)
  806. mtd->ecc_stats.failed++;
  807. else
  808. mtd->ecc_stats.corrected += stat;
  809. }
  810. return 0;
  811. }
  812. /**
  813. * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
  814. * @mtd: mtd info structure
  815. * @chip: nand chip info structure
  816. * @data_offs: offset of requested data within the page
  817. * @readlen: data length
  818. * @bufpoi: buffer to store read data
  819. */
  820. static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  821. uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
  822. {
  823. int start_step, end_step, num_steps;
  824. uint32_t *eccpos = chip->ecc.layout->eccpos;
  825. uint8_t *p;
  826. int data_col_addr, i, gaps = 0;
  827. int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
  828. int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
  829. int index = 0;
  830. /* Column address within the page aligned to ECC size (256bytes) */
  831. start_step = data_offs / chip->ecc.size;
  832. end_step = (data_offs + readlen - 1) / chip->ecc.size;
  833. num_steps = end_step - start_step + 1;
  834. /* Data size aligned to ECC ecc.size */
  835. datafrag_len = num_steps * chip->ecc.size;
  836. eccfrag_len = num_steps * chip->ecc.bytes;
  837. data_col_addr = start_step * chip->ecc.size;
  838. /* If we read not a page aligned data */
  839. if (data_col_addr != 0)
  840. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
  841. p = bufpoi + data_col_addr;
  842. chip->read_buf(mtd, p, datafrag_len);
  843. /* Calculate ECC */
  844. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
  845. chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
  846. /*
  847. * The performance is faster if we position offsets according to
  848. * ecc.pos. Let's make sure that there are no gaps in ECC positions.
  849. */
  850. for (i = 0; i < eccfrag_len - 1; i++) {
  851. if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
  852. eccpos[i + start_step * chip->ecc.bytes + 1]) {
  853. gaps = 1;
  854. break;
  855. }
  856. }
  857. if (gaps) {
  858. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
  859. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  860. } else {
  861. /*
  862. * Send the command to read the particular ECC bytes take care
  863. * about buswidth alignment in read_buf.
  864. */
  865. index = start_step * chip->ecc.bytes;
  866. aligned_pos = eccpos[index] & ~(busw - 1);
  867. aligned_len = eccfrag_len;
  868. if (eccpos[index] & (busw - 1))
  869. aligned_len++;
  870. if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
  871. aligned_len++;
  872. chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
  873. mtd->writesize + aligned_pos, -1);
  874. chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
  875. }
  876. for (i = 0; i < eccfrag_len; i++)
  877. chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
  878. p = bufpoi + data_col_addr;
  879. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
  880. int stat;
  881. stat = chip->ecc.correct(mtd, p,
  882. &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
  883. if (stat < 0)
  884. mtd->ecc_stats.failed++;
  885. else
  886. mtd->ecc_stats.corrected += stat;
  887. }
  888. return 0;
  889. }
  890. /**
  891. * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
  892. * @mtd: mtd info structure
  893. * @chip: nand chip info structure
  894. * @buf: buffer to store read data
  895. * @oob_required: caller requires OOB data read to chip->oob_poi
  896. * @page: page number to read
  897. *
  898. * Not for syndrome calculating ECC controllers which need a special oob layout.
  899. */
  900. static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  901. uint8_t *buf, int oob_required, int page)
  902. {
  903. int i, eccsize = chip->ecc.size;
  904. int eccbytes = chip->ecc.bytes;
  905. int eccsteps = chip->ecc.steps;
  906. uint8_t *p = buf;
  907. uint8_t *ecc_calc = chip->buffers->ecccalc;
  908. uint8_t *ecc_code = chip->buffers->ecccode;
  909. uint32_t *eccpos = chip->ecc.layout->eccpos;
  910. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  911. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  912. chip->read_buf(mtd, p, eccsize);
  913. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  914. }
  915. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  916. for (i = 0; i < chip->ecc.total; i++)
  917. ecc_code[i] = chip->oob_poi[eccpos[i]];
  918. eccsteps = chip->ecc.steps;
  919. p = buf;
  920. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  921. int stat;
  922. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  923. if (stat < 0)
  924. mtd->ecc_stats.failed++;
  925. else
  926. mtd->ecc_stats.corrected += stat;
  927. }
  928. return 0;
  929. }
  930. /**
  931. * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
  932. * @mtd: mtd info structure
  933. * @chip: nand chip info structure
  934. * @buf: buffer to store read data
  935. * @oob_required: caller requires OOB data read to chip->oob_poi
  936. * @page: page number to read
  937. *
  938. * Hardware ECC for large page chips, require OOB to be read first. For this
  939. * ECC mode, the write_page method is re-used from ECC_HW. These methods
  940. * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
  941. * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
  942. * the data area, by overwriting the NAND manufacturer bad block markings.
  943. */
  944. static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
  945. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  946. {
  947. int i, eccsize = chip->ecc.size;
  948. int eccbytes = chip->ecc.bytes;
  949. int eccsteps = chip->ecc.steps;
  950. uint8_t *p = buf;
  951. uint8_t *ecc_code = chip->buffers->ecccode;
  952. uint32_t *eccpos = chip->ecc.layout->eccpos;
  953. uint8_t *ecc_calc = chip->buffers->ecccalc;
  954. /* Read the OOB area first */
  955. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  956. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  957. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  958. for (i = 0; i < chip->ecc.total; i++)
  959. ecc_code[i] = chip->oob_poi[eccpos[i]];
  960. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  961. int stat;
  962. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  963. chip->read_buf(mtd, p, eccsize);
  964. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  965. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  966. if (stat < 0)
  967. mtd->ecc_stats.failed++;
  968. else
  969. mtd->ecc_stats.corrected += stat;
  970. }
  971. return 0;
  972. }
  973. /**
  974. * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
  975. * @mtd: mtd info structure
  976. * @chip: nand chip info structure
  977. * @buf: buffer to store read data
  978. * @oob_required: caller requires OOB data read to chip->oob_poi
  979. * @page: page number to read
  980. *
  981. * The hw generator calculates the error syndrome automatically. Therefore we
  982. * need a special oob layout and handling.
  983. */
  984. static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  985. uint8_t *buf, int oob_required, int page)
  986. {
  987. int i, eccsize = chip->ecc.size;
  988. int eccbytes = chip->ecc.bytes;
  989. int eccsteps = chip->ecc.steps;
  990. uint8_t *p = buf;
  991. uint8_t *oob = chip->oob_poi;
  992. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  993. int stat;
  994. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  995. chip->read_buf(mtd, p, eccsize);
  996. if (chip->ecc.prepad) {
  997. chip->read_buf(mtd, oob, chip->ecc.prepad);
  998. oob += chip->ecc.prepad;
  999. }
  1000. chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
  1001. chip->read_buf(mtd, oob, eccbytes);
  1002. stat = chip->ecc.correct(mtd, p, oob, NULL);
  1003. if (stat < 0)
  1004. mtd->ecc_stats.failed++;
  1005. else
  1006. mtd->ecc_stats.corrected += stat;
  1007. oob += eccbytes;
  1008. if (chip->ecc.postpad) {
  1009. chip->read_buf(mtd, oob, chip->ecc.postpad);
  1010. oob += chip->ecc.postpad;
  1011. }
  1012. }
  1013. /* Calculate remaining oob bytes */
  1014. i = mtd->oobsize - (oob - chip->oob_poi);
  1015. if (i)
  1016. chip->read_buf(mtd, oob, i);
  1017. return 0;
  1018. }
  1019. /**
  1020. * nand_transfer_oob - [INTERN] Transfer oob to client buffer
  1021. * @chip: nand chip structure
  1022. * @oob: oob destination address
  1023. * @ops: oob ops structure
  1024. * @len: size of oob to transfer
  1025. */
  1026. static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  1027. struct mtd_oob_ops *ops, size_t len)
  1028. {
  1029. switch (ops->mode) {
  1030. case MTD_OPS_PLACE_OOB:
  1031. case MTD_OPS_RAW:
  1032. memcpy(oob, chip->oob_poi + ops->ooboffs, len);
  1033. return oob + len;
  1034. case MTD_OPS_AUTO_OOB: {
  1035. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  1036. uint32_t boffs = 0, roffs = ops->ooboffs;
  1037. size_t bytes = 0;
  1038. for (; free->length && len; free++, len -= bytes) {
  1039. /* Read request not from offset 0? */
  1040. if (unlikely(roffs)) {
  1041. if (roffs >= free->length) {
  1042. roffs -= free->length;
  1043. continue;
  1044. }
  1045. boffs = free->offset + roffs;
  1046. bytes = min_t(size_t, len,
  1047. (free->length - roffs));
  1048. roffs = 0;
  1049. } else {
  1050. bytes = min_t(size_t, len, free->length);
  1051. boffs = free->offset;
  1052. }
  1053. memcpy(oob, chip->oob_poi + boffs, bytes);
  1054. oob += bytes;
  1055. }
  1056. return oob;
  1057. }
  1058. default:
  1059. BUG();
  1060. }
  1061. return NULL;
  1062. }
  1063. /**
  1064. * nand_do_read_ops - [INTERN] Read data with ECC
  1065. * @mtd: MTD device structure
  1066. * @from: offset to read from
  1067. * @ops: oob ops structure
  1068. *
  1069. * Internal function. Called with chip held.
  1070. */
  1071. static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
  1072. struct mtd_oob_ops *ops)
  1073. {
  1074. int chipnr, page, realpage, col, bytes, aligned, oob_required;
  1075. struct nand_chip *chip = mtd->priv;
  1076. struct mtd_ecc_stats stats;
  1077. int ret = 0;
  1078. uint32_t readlen = ops->len;
  1079. uint32_t oobreadlen = ops->ooblen;
  1080. uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
  1081. mtd->oobavail : mtd->oobsize;
  1082. uint8_t *bufpoi, *oob, *buf;
  1083. unsigned int max_bitflips = 0;
  1084. stats = mtd->ecc_stats;
  1085. chipnr = (int)(from >> chip->chip_shift);
  1086. chip->select_chip(mtd, chipnr);
  1087. realpage = (int)(from >> chip->page_shift);
  1088. page = realpage & chip->pagemask;
  1089. col = (int)(from & (mtd->writesize - 1));
  1090. buf = ops->datbuf;
  1091. oob = ops->oobbuf;
  1092. oob_required = oob ? 1 : 0;
  1093. while (1) {
  1094. WATCHDOG_RESET();
  1095. bytes = min(mtd->writesize - col, readlen);
  1096. aligned = (bytes == mtd->writesize);
  1097. /* Is the current page in the buffer? */
  1098. if (realpage != chip->pagebuf || oob) {
  1099. bufpoi = aligned ? buf : chip->buffers->databuf;
  1100. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  1101. /*
  1102. * Now read the page into the buffer. Absent an error,
  1103. * the read methods return max bitflips per ecc step.
  1104. */
  1105. if (unlikely(ops->mode == MTD_OPS_RAW))
  1106. ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
  1107. oob_required,
  1108. page);
  1109. else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
  1110. !oob)
  1111. ret = chip->ecc.read_subpage(mtd, chip,
  1112. col, bytes, bufpoi);
  1113. else
  1114. ret = chip->ecc.read_page(mtd, chip, bufpoi,
  1115. oob_required, page);
  1116. if (ret < 0) {
  1117. if (!aligned)
  1118. /* Invalidate page cache */
  1119. chip->pagebuf = -1;
  1120. break;
  1121. }
  1122. max_bitflips = max_t(unsigned int, max_bitflips, ret);
  1123. /* Transfer not aligned data */
  1124. if (!aligned) {
  1125. if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
  1126. !(mtd->ecc_stats.failed - stats.failed) &&
  1127. (ops->mode != MTD_OPS_RAW)) {
  1128. chip->pagebuf = realpage;
  1129. chip->pagebuf_bitflips = ret;
  1130. } else {
  1131. /* Invalidate page cache */
  1132. chip->pagebuf = -1;
  1133. }
  1134. memcpy(buf, chip->buffers->databuf + col, bytes);
  1135. }
  1136. buf += bytes;
  1137. if (unlikely(oob)) {
  1138. int toread = min(oobreadlen, max_oobsize);
  1139. if (toread) {
  1140. oob = nand_transfer_oob(chip,
  1141. oob, ops, toread);
  1142. oobreadlen -= toread;
  1143. }
  1144. }
  1145. } else {
  1146. memcpy(buf, chip->buffers->databuf + col, bytes);
  1147. buf += bytes;
  1148. max_bitflips = max_t(unsigned int, max_bitflips,
  1149. chip->pagebuf_bitflips);
  1150. }
  1151. readlen -= bytes;
  1152. if (!readlen)
  1153. break;
  1154. /* For subsequent reads align to page boundary */
  1155. col = 0;
  1156. /* Increment page address */
  1157. realpage++;
  1158. page = realpage & chip->pagemask;
  1159. /* Check, if we cross a chip boundary */
  1160. if (!page) {
  1161. chipnr++;
  1162. chip->select_chip(mtd, -1);
  1163. chip->select_chip(mtd, chipnr);
  1164. }
  1165. }
  1166. ops->retlen = ops->len - (size_t) readlen;
  1167. if (oob)
  1168. ops->oobretlen = ops->ooblen - oobreadlen;
  1169. if (ret)
  1170. return ret;
  1171. if (mtd->ecc_stats.failed - stats.failed)
  1172. return -EBADMSG;
  1173. return max_bitflips;
  1174. }
  1175. /**
  1176. * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
  1177. * @mtd: MTD device structure
  1178. * @from: offset to read from
  1179. * @len: number of bytes to read
  1180. * @retlen: pointer to variable to store the number of read bytes
  1181. * @buf: the databuffer to put data
  1182. *
  1183. * Get hold of the chip and call nand_do_read.
  1184. */
  1185. static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
  1186. size_t *retlen, uint8_t *buf)
  1187. {
  1188. struct nand_chip *chip = mtd->priv;
  1189. struct mtd_oob_ops ops;
  1190. int ret;
  1191. nand_get_device(chip, mtd, FL_READING);
  1192. ops.len = len;
  1193. ops.datbuf = buf;
  1194. ops.oobbuf = NULL;
  1195. ops.mode = MTD_OPS_PLACE_OOB;
  1196. ret = nand_do_read_ops(mtd, from, &ops);
  1197. *retlen = ops.retlen;
  1198. nand_release_device(mtd);
  1199. return ret;
  1200. }
  1201. /**
  1202. * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
  1203. * @mtd: mtd info structure
  1204. * @chip: nand chip info structure
  1205. * @page: page number to read
  1206. */
  1207. static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  1208. int page)
  1209. {
  1210. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  1211. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1212. return 0;
  1213. }
  1214. /**
  1215. * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
  1216. * with syndromes
  1217. * @mtd: mtd info structure
  1218. * @chip: nand chip info structure
  1219. * @page: page number to read
  1220. */
  1221. static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  1222. int page)
  1223. {
  1224. uint8_t *buf = chip->oob_poi;
  1225. int length = mtd->oobsize;
  1226. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  1227. int eccsize = chip->ecc.size;
  1228. uint8_t *bufpoi = buf;
  1229. int i, toread, sndrnd = 0, pos;
  1230. chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
  1231. for (i = 0; i < chip->ecc.steps; i++) {
  1232. if (sndrnd) {
  1233. pos = eccsize + i * (eccsize + chunk);
  1234. if (mtd->writesize > 512)
  1235. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
  1236. else
  1237. chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
  1238. } else
  1239. sndrnd = 1;
  1240. toread = min_t(int, length, chunk);
  1241. chip->read_buf(mtd, bufpoi, toread);
  1242. bufpoi += toread;
  1243. length -= toread;
  1244. }
  1245. if (length > 0)
  1246. chip->read_buf(mtd, bufpoi, length);
  1247. return 0;
  1248. }
  1249. /**
  1250. * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
  1251. * @mtd: mtd info structure
  1252. * @chip: nand chip info structure
  1253. * @page: page number to write
  1254. */
  1255. static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  1256. int page)
  1257. {
  1258. int status = 0;
  1259. const uint8_t *buf = chip->oob_poi;
  1260. int length = mtd->oobsize;
  1261. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  1262. chip->write_buf(mtd, buf, length);
  1263. /* Send command to program the OOB data */
  1264. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1265. status = chip->waitfunc(mtd, chip);
  1266. return status & NAND_STATUS_FAIL ? -EIO : 0;
  1267. }
  1268. /**
  1269. * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
  1270. * with syndrome - only for large page flash
  1271. * @mtd: mtd info structure
  1272. * @chip: nand chip info structure
  1273. * @page: page number to write
  1274. */
  1275. static int nand_write_oob_syndrome(struct mtd_info *mtd,
  1276. struct nand_chip *chip, int page)
  1277. {
  1278. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  1279. int eccsize = chip->ecc.size, length = mtd->oobsize;
  1280. int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
  1281. const uint8_t *bufpoi = chip->oob_poi;
  1282. /*
  1283. * data-ecc-data-ecc ... ecc-oob
  1284. * or
  1285. * data-pad-ecc-pad-data-pad .... ecc-pad-oob
  1286. */
  1287. if (!chip->ecc.prepad && !chip->ecc.postpad) {
  1288. pos = steps * (eccsize + chunk);
  1289. steps = 0;
  1290. } else
  1291. pos = eccsize;
  1292. chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
  1293. for (i = 0; i < steps; i++) {
  1294. if (sndcmd) {
  1295. if (mtd->writesize <= 512) {
  1296. uint32_t fill = 0xFFFFFFFF;
  1297. len = eccsize;
  1298. while (len > 0) {
  1299. int num = min_t(int, len, 4);
  1300. chip->write_buf(mtd, (uint8_t *)&fill,
  1301. num);
  1302. len -= num;
  1303. }
  1304. } else {
  1305. pos = eccsize + i * (eccsize + chunk);
  1306. chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
  1307. }
  1308. } else
  1309. sndcmd = 1;
  1310. len = min_t(int, length, chunk);
  1311. chip->write_buf(mtd, bufpoi, len);
  1312. bufpoi += len;
  1313. length -= len;
  1314. }
  1315. if (length > 0)
  1316. chip->write_buf(mtd, bufpoi, length);
  1317. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1318. status = chip->waitfunc(mtd, chip);
  1319. return status & NAND_STATUS_FAIL ? -EIO : 0;
  1320. }
  1321. /**
  1322. * nand_do_read_oob - [INTERN] NAND read out-of-band
  1323. * @mtd: MTD device structure
  1324. * @from: offset to read from
  1325. * @ops: oob operations description structure
  1326. *
  1327. * NAND read out-of-band data from the spare area.
  1328. */
  1329. static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
  1330. struct mtd_oob_ops *ops)
  1331. {
  1332. int page, realpage, chipnr;
  1333. struct nand_chip *chip = mtd->priv;
  1334. struct mtd_ecc_stats stats;
  1335. int readlen = ops->ooblen;
  1336. int len;
  1337. uint8_t *buf = ops->oobbuf;
  1338. int ret = 0;
  1339. MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
  1340. __func__, (unsigned long long)from, readlen);
  1341. stats = mtd->ecc_stats;
  1342. if (ops->mode == MTD_OPS_AUTO_OOB)
  1343. len = chip->ecc.layout->oobavail;
  1344. else
  1345. len = mtd->oobsize;
  1346. if (unlikely(ops->ooboffs >= len)) {
  1347. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
  1348. "outside oob\n", __func__);
  1349. return -EINVAL;
  1350. }
  1351. /* Do not allow reads past end of device */
  1352. if (unlikely(from >= mtd->size ||
  1353. ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
  1354. (from >> chip->page_shift)) * len)) {
  1355. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
  1356. "of device\n", __func__);
  1357. return -EINVAL;
  1358. }
  1359. chipnr = (int)(from >> chip->chip_shift);
  1360. chip->select_chip(mtd, chipnr);
  1361. /* Shift to get page */
  1362. realpage = (int)(from >> chip->page_shift);
  1363. page = realpage & chip->pagemask;
  1364. while (1) {
  1365. WATCHDOG_RESET();
  1366. if (ops->mode == MTD_OPS_RAW)
  1367. ret = chip->ecc.read_oob_raw(mtd, chip, page);
  1368. else
  1369. ret = chip->ecc.read_oob(mtd, chip, page);
  1370. if (ret < 0)
  1371. break;
  1372. len = min(len, readlen);
  1373. buf = nand_transfer_oob(chip, buf, ops, len);
  1374. readlen -= len;
  1375. if (!readlen)
  1376. break;
  1377. /* Increment page address */
  1378. realpage++;
  1379. page = realpage & chip->pagemask;
  1380. /* Check, if we cross a chip boundary */
  1381. if (!page) {
  1382. chipnr++;
  1383. chip->select_chip(mtd, -1);
  1384. chip->select_chip(mtd, chipnr);
  1385. }
  1386. }
  1387. ops->oobretlen = ops->ooblen - readlen;
  1388. if (ret < 0)
  1389. return ret;
  1390. if (mtd->ecc_stats.failed - stats.failed)
  1391. return -EBADMSG;
  1392. return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
  1393. }
  1394. /**
  1395. * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
  1396. * @mtd: MTD device structure
  1397. * @from: offset to read from
  1398. * @ops: oob operation description structure
  1399. *
  1400. * NAND read data and/or out-of-band data.
  1401. */
  1402. static int nand_read_oob(struct mtd_info *mtd, loff_t from,
  1403. struct mtd_oob_ops *ops)
  1404. {
  1405. struct nand_chip *chip = mtd->priv;
  1406. int ret = -ENOTSUPP;
  1407. ops->retlen = 0;
  1408. /* Do not allow reads past end of device */
  1409. if (ops->datbuf && (from + ops->len) > mtd->size) {
  1410. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
  1411. "beyond end of device\n", __func__);
  1412. return -EINVAL;
  1413. }
  1414. nand_get_device(chip, mtd, FL_READING);
  1415. switch (ops->mode) {
  1416. case MTD_OPS_PLACE_OOB:
  1417. case MTD_OPS_AUTO_OOB:
  1418. case MTD_OPS_RAW:
  1419. break;
  1420. default:
  1421. goto out;
  1422. }
  1423. if (!ops->datbuf)
  1424. ret = nand_do_read_oob(mtd, from, ops);
  1425. else
  1426. ret = nand_do_read_ops(mtd, from, ops);
  1427. out:
  1428. nand_release_device(mtd);
  1429. return ret;
  1430. }
  1431. /**
  1432. * nand_write_page_raw - [INTERN] raw page write function
  1433. * @mtd: mtd info structure
  1434. * @chip: nand chip info structure
  1435. * @buf: data buffer
  1436. * @oob_required: must write chip->oob_poi to OOB
  1437. *
  1438. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  1439. */
  1440. static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1441. const uint8_t *buf, int oob_required)
  1442. {
  1443. chip->write_buf(mtd, buf, mtd->writesize);
  1444. if (oob_required)
  1445. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1446. return 0;
  1447. }
  1448. /**
  1449. * nand_write_page_raw_syndrome - [INTERN] raw page write function
  1450. * @mtd: mtd info structure
  1451. * @chip: nand chip info structure
  1452. * @buf: data buffer
  1453. * @oob_required: must write chip->oob_poi to OOB
  1454. *
  1455. * We need a special oob layout and handling even when ECC isn't checked.
  1456. */
  1457. static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  1458. struct nand_chip *chip,
  1459. const uint8_t *buf, int oob_required)
  1460. {
  1461. int eccsize = chip->ecc.size;
  1462. int eccbytes = chip->ecc.bytes;
  1463. uint8_t *oob = chip->oob_poi;
  1464. int steps, size;
  1465. for (steps = chip->ecc.steps; steps > 0; steps--) {
  1466. chip->write_buf(mtd, buf, eccsize);
  1467. buf += eccsize;
  1468. if (chip->ecc.prepad) {
  1469. chip->write_buf(mtd, oob, chip->ecc.prepad);
  1470. oob += chip->ecc.prepad;
  1471. }
  1472. chip->read_buf(mtd, oob, eccbytes);
  1473. oob += eccbytes;
  1474. if (chip->ecc.postpad) {
  1475. chip->write_buf(mtd, oob, chip->ecc.postpad);
  1476. oob += chip->ecc.postpad;
  1477. }
  1478. }
  1479. size = mtd->oobsize - (oob - chip->oob_poi);
  1480. if (size)
  1481. chip->write_buf(mtd, oob, size);
  1482. return 0;
  1483. }
  1484. /**
  1485. * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
  1486. * @mtd: mtd info structure
  1487. * @chip: nand chip info structure
  1488. * @buf: data buffer
  1489. * @oob_required: must write chip->oob_poi to OOB
  1490. */
  1491. static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  1492. const uint8_t *buf, int oob_required)
  1493. {
  1494. int i, eccsize = chip->ecc.size;
  1495. int eccbytes = chip->ecc.bytes;
  1496. int eccsteps = chip->ecc.steps;
  1497. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1498. const uint8_t *p = buf;
  1499. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1500. /* Software ECC calculation */
  1501. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1502. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1503. for (i = 0; i < chip->ecc.total; i++)
  1504. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  1505. return chip->ecc.write_page_raw(mtd, chip, buf, 1);
  1506. }
  1507. /**
  1508. * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
  1509. * @mtd: mtd info structure
  1510. * @chip: nand chip info structure
  1511. * @buf: data buffer
  1512. * @oob_required: must write chip->oob_poi to OOB
  1513. */
  1514. static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  1515. const uint8_t *buf, int oob_required)
  1516. {
  1517. int i, eccsize = chip->ecc.size;
  1518. int eccbytes = chip->ecc.bytes;
  1519. int eccsteps = chip->ecc.steps;
  1520. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1521. const uint8_t *p = buf;
  1522. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1523. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1524. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  1525. chip->write_buf(mtd, p, eccsize);
  1526. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1527. }
  1528. for (i = 0; i < chip->ecc.total; i++)
  1529. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  1530. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1531. return 0;
  1532. }
  1533. /**
  1534. * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
  1535. * @mtd: mtd info structure
  1536. * @chip: nand chip info structure
  1537. * @buf: data buffer
  1538. * @oob_required: must write chip->oob_poi to OOB
  1539. *
  1540. * The hw generator calculates the error syndrome automatically. Therefore we
  1541. * need a special oob layout and handling.
  1542. */
  1543. static int nand_write_page_syndrome(struct mtd_info *mtd,
  1544. struct nand_chip *chip,
  1545. const uint8_t *buf, int oob_required)
  1546. {
  1547. int i, eccsize = chip->ecc.size;
  1548. int eccbytes = chip->ecc.bytes;
  1549. int eccsteps = chip->ecc.steps;
  1550. const uint8_t *p = buf;
  1551. uint8_t *oob = chip->oob_poi;
  1552. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1553. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  1554. chip->write_buf(mtd, p, eccsize);
  1555. if (chip->ecc.prepad) {
  1556. chip->write_buf(mtd, oob, chip->ecc.prepad);
  1557. oob += chip->ecc.prepad;
  1558. }
  1559. chip->ecc.calculate(mtd, p, oob);
  1560. chip->write_buf(mtd, oob, eccbytes);
  1561. oob += eccbytes;
  1562. if (chip->ecc.postpad) {
  1563. chip->write_buf(mtd, oob, chip->ecc.postpad);
  1564. oob += chip->ecc.postpad;
  1565. }
  1566. }
  1567. /* Calculate remaining oob bytes */
  1568. i = mtd->oobsize - (oob - chip->oob_poi);
  1569. if (i)
  1570. chip->write_buf(mtd, oob, i);
  1571. return 0;
  1572. }
  1573. /**
  1574. * nand_write_page - [REPLACEABLE] write one page
  1575. * @mtd: MTD device structure
  1576. * @chip: NAND chip descriptor
  1577. * @buf: the data to write
  1578. * @oob_required: must write chip->oob_poi to OOB
  1579. * @page: page number to write
  1580. * @cached: cached programming
  1581. * @raw: use _raw version of write_page
  1582. */
  1583. static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  1584. const uint8_t *buf, int oob_required, int page,
  1585. int cached, int raw)
  1586. {
  1587. int status;
  1588. chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
  1589. if (unlikely(raw))
  1590. status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
  1591. else
  1592. status = chip->ecc.write_page(mtd, chip, buf, oob_required);
  1593. if (status < 0)
  1594. return status;
  1595. /*
  1596. * Cached progamming disabled for now. Not sure if it's worth the
  1597. * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
  1598. */
  1599. cached = 0;
  1600. if (!cached || !(chip->options & NAND_CACHEPRG)) {
  1601. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1602. status = chip->waitfunc(mtd, chip);
  1603. /*
  1604. * See if operation failed and additional status checks are
  1605. * available.
  1606. */
  1607. if ((status & NAND_STATUS_FAIL) && (chip->errstat))
  1608. status = chip->errstat(mtd, chip, FL_WRITING, status,
  1609. page);
  1610. if (status & NAND_STATUS_FAIL)
  1611. return -EIO;
  1612. } else {
  1613. chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
  1614. status = chip->waitfunc(mtd, chip);
  1615. }
  1616. #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
  1617. /* Send command to read back the data */
  1618. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  1619. if (chip->verify_buf(mtd, buf, mtd->writesize))
  1620. return -EIO;
  1621. /* Make sure the next page prog is preceded by a status read */
  1622. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  1623. #endif
  1624. return 0;
  1625. }
  1626. /**
  1627. * nand_fill_oob - [INTERN] Transfer client buffer to oob
  1628. * @mtd: MTD device structure
  1629. * @oob: oob data buffer
  1630. * @len: oob data write length
  1631. * @ops: oob ops structure
  1632. */
  1633. static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
  1634. struct mtd_oob_ops *ops)
  1635. {
  1636. struct nand_chip *chip = mtd->priv;
  1637. /*
  1638. * Initialise to all 0xFF, to avoid the possibility of left over OOB
  1639. * data from a previous OOB read.
  1640. */
  1641. memset(chip->oob_poi, 0xff, mtd->oobsize);
  1642. switch (ops->mode) {
  1643. case MTD_OPS_PLACE_OOB:
  1644. case MTD_OPS_RAW:
  1645. memcpy(chip->oob_poi + ops->ooboffs, oob, len);
  1646. return oob + len;
  1647. case MTD_OPS_AUTO_OOB: {
  1648. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  1649. uint32_t boffs = 0, woffs = ops->ooboffs;
  1650. size_t bytes = 0;
  1651. for (; free->length && len; free++, len -= bytes) {
  1652. /* Write request not from offset 0? */
  1653. if (unlikely(woffs)) {
  1654. if (woffs >= free->length) {
  1655. woffs -= free->length;
  1656. continue;
  1657. }
  1658. boffs = free->offset + woffs;
  1659. bytes = min_t(size_t, len,
  1660. (free->length - woffs));
  1661. woffs = 0;
  1662. } else {
  1663. bytes = min_t(size_t, len, free->length);
  1664. boffs = free->offset;
  1665. }
  1666. memcpy(chip->oob_poi + boffs, oob, bytes);
  1667. oob += bytes;
  1668. }
  1669. return oob;
  1670. }
  1671. default:
  1672. BUG();
  1673. }
  1674. return NULL;
  1675. }
  1676. #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
  1677. /**
  1678. * nand_do_write_ops - [INTERN] NAND write with ECC
  1679. * @mtd: MTD device structure
  1680. * @to: offset to write to
  1681. * @ops: oob operations description structure
  1682. *
  1683. * NAND write with ECC.
  1684. */
  1685. static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
  1686. struct mtd_oob_ops *ops)
  1687. {
  1688. int chipnr, realpage, page, blockmask, column;
  1689. struct nand_chip *chip = mtd->priv;
  1690. uint32_t writelen = ops->len;
  1691. uint32_t oobwritelen = ops->ooblen;
  1692. uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
  1693. mtd->oobavail : mtd->oobsize;
  1694. uint8_t *oob = ops->oobbuf;
  1695. uint8_t *buf = ops->datbuf;
  1696. int ret, subpage;
  1697. int oob_required = oob ? 1 : 0;
  1698. ops->retlen = 0;
  1699. if (!writelen)
  1700. return 0;
  1701. column = to & (mtd->writesize - 1);
  1702. subpage = column || (writelen & (mtd->writesize - 1));
  1703. if (subpage && oob)
  1704. return -EINVAL;
  1705. chipnr = (int)(to >> chip->chip_shift);
  1706. chip->select_chip(mtd, chipnr);
  1707. /* Check, if it is write protected */
  1708. if (nand_check_wp(mtd)) {
  1709. printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
  1710. return -EIO;
  1711. }
  1712. realpage = (int)(to >> chip->page_shift);
  1713. page = realpage & chip->pagemask;
  1714. blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
  1715. /* Invalidate the page cache, when we write to the cached page */
  1716. if (to <= (chip->pagebuf << chip->page_shift) &&
  1717. (chip->pagebuf << chip->page_shift) < (to + ops->len))
  1718. chip->pagebuf = -1;
  1719. /* Don't allow multipage oob writes with offset */
  1720. if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
  1721. return -EINVAL;
  1722. while (1) {
  1723. WATCHDOG_RESET();
  1724. int bytes = mtd->writesize;
  1725. int cached = writelen > bytes && page != blockmask;
  1726. uint8_t *wbuf = buf;
  1727. /* Partial page write? */
  1728. if (unlikely(column || writelen < mtd->writesize)) {
  1729. cached = 0;
  1730. bytes = min_t(int, bytes - column, (int) writelen);
  1731. chip->pagebuf = -1;
  1732. memset(chip->buffers->databuf, 0xff, mtd->writesize);
  1733. memcpy(&chip->buffers->databuf[column], buf, bytes);
  1734. wbuf = chip->buffers->databuf;
  1735. }
  1736. if (unlikely(oob)) {
  1737. size_t len = min(oobwritelen, oobmaxlen);
  1738. oob = nand_fill_oob(mtd, oob, len, ops);
  1739. oobwritelen -= len;
  1740. } else {
  1741. /* We still need to erase leftover OOB data */
  1742. memset(chip->oob_poi, 0xff, mtd->oobsize);
  1743. }
  1744. ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
  1745. cached, (ops->mode == MTD_OPS_RAW));
  1746. if (ret)
  1747. break;
  1748. writelen -= bytes;
  1749. if (!writelen)
  1750. break;
  1751. column = 0;
  1752. buf += bytes;
  1753. realpage++;
  1754. page = realpage & chip->pagemask;
  1755. /* Check, if we cross a chip boundary */
  1756. if (!page) {
  1757. chipnr++;
  1758. chip->select_chip(mtd, -1);
  1759. chip->select_chip(mtd, chipnr);
  1760. }
  1761. }
  1762. ops->retlen = ops->len - writelen;
  1763. if (unlikely(oob))
  1764. ops->oobretlen = ops->ooblen;
  1765. return ret;
  1766. }
  1767. /**
  1768. * nand_write - [MTD Interface] NAND write with ECC
  1769. * @mtd: MTD device structure
  1770. * @to: offset to write to
  1771. * @len: number of bytes to write
  1772. * @retlen: pointer to variable to store the number of written bytes
  1773. * @buf: the data to write
  1774. *
  1775. * NAND write with ECC.
  1776. */
  1777. static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
  1778. size_t *retlen, const uint8_t *buf)
  1779. {
  1780. struct nand_chip *chip = mtd->priv;
  1781. struct mtd_oob_ops ops;
  1782. int ret;
  1783. nand_get_device(chip, mtd, FL_WRITING);
  1784. ops.len = len;
  1785. ops.datbuf = (uint8_t *)buf;
  1786. ops.oobbuf = NULL;
  1787. ops.mode = MTD_OPS_PLACE_OOB;
  1788. ret = nand_do_write_ops(mtd, to, &ops);
  1789. *retlen = ops.retlen;
  1790. nand_release_device(mtd);
  1791. return ret;
  1792. }
  1793. /**
  1794. * nand_do_write_oob - [MTD Interface] NAND write out-of-band
  1795. * @mtd: MTD device structure
  1796. * @to: offset to write to
  1797. * @ops: oob operation description structure
  1798. *
  1799. * NAND write out-of-band.
  1800. */
  1801. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  1802. struct mtd_oob_ops *ops)
  1803. {
  1804. int chipnr, page, status, len;
  1805. struct nand_chip *chip = mtd->priv;
  1806. MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
  1807. __func__, (unsigned int)to, (int)ops->ooblen);
  1808. if (ops->mode == MTD_OPS_AUTO_OOB)
  1809. len = chip->ecc.layout->oobavail;
  1810. else
  1811. len = mtd->oobsize;
  1812. /* Do not allow write past end of page */
  1813. if ((ops->ooboffs + ops->ooblen) > len) {
  1814. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
  1815. "past end of page\n", __func__);
  1816. return -EINVAL;
  1817. }
  1818. if (unlikely(ops->ooboffs >= len)) {
  1819. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
  1820. "write outside oob\n", __func__);
  1821. return -EINVAL;
  1822. }
  1823. /* Do not allow write past end of device */
  1824. if (unlikely(to >= mtd->size ||
  1825. ops->ooboffs + ops->ooblen >
  1826. ((mtd->size >> chip->page_shift) -
  1827. (to >> chip->page_shift)) * len)) {
  1828. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
  1829. "end of device\n", __func__);
  1830. return -EINVAL;
  1831. }
  1832. chipnr = (int)(to >> chip->chip_shift);
  1833. chip->select_chip(mtd, chipnr);
  1834. /* Shift to get page */
  1835. page = (int)(to >> chip->page_shift);
  1836. /*
  1837. * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
  1838. * of my DiskOnChip 2000 test units) will clear the whole data page too
  1839. * if we don't do this. I have no clue why, but I seem to have 'fixed'
  1840. * it in the doc2000 driver in August 1999. dwmw2.
  1841. */
  1842. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  1843. /* Check, if it is write protected */
  1844. if (nand_check_wp(mtd))
  1845. return -EROFS;
  1846. /* Invalidate the page cache, if we write to the cached page */
  1847. if (page == chip->pagebuf)
  1848. chip->pagebuf = -1;
  1849. nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
  1850. if (ops->mode == MTD_OPS_RAW)
  1851. status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
  1852. else
  1853. status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
  1854. if (status)
  1855. return status;
  1856. ops->oobretlen = ops->ooblen;
  1857. return 0;
  1858. }
  1859. /**
  1860. * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
  1861. * @mtd: MTD device structure
  1862. * @to: offset to write to
  1863. * @ops: oob operation description structure
  1864. */
  1865. static int nand_write_oob(struct mtd_info *mtd, loff_t to,
  1866. struct mtd_oob_ops *ops)
  1867. {
  1868. struct nand_chip *chip = mtd->priv;
  1869. int ret = -ENOTSUPP;
  1870. ops->retlen = 0;
  1871. /* Do not allow writes past end of device */
  1872. if (ops->datbuf && (to + ops->len) > mtd->size) {
  1873. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
  1874. "end of device\n", __func__);
  1875. return -EINVAL;
  1876. }
  1877. nand_get_device(chip, mtd, FL_WRITING);
  1878. switch (ops->mode) {
  1879. case MTD_OPS_PLACE_OOB:
  1880. case MTD_OPS_AUTO_OOB:
  1881. case MTD_OPS_RAW:
  1882. break;
  1883. default:
  1884. goto out;
  1885. }
  1886. if (!ops->datbuf)
  1887. ret = nand_do_write_oob(mtd, to, ops);
  1888. else
  1889. ret = nand_do_write_ops(mtd, to, ops);
  1890. out:
  1891. nand_release_device(mtd);
  1892. return ret;
  1893. }
  1894. /**
  1895. * single_erase_cmd - [GENERIC] NAND standard block erase command function
  1896. * @mtd: MTD device structure
  1897. * @page: the page address of the block which will be erased
  1898. *
  1899. * Standard erase command for NAND chips.
  1900. */
  1901. static void single_erase_cmd(struct mtd_info *mtd, int page)
  1902. {
  1903. struct nand_chip *chip = mtd->priv;
  1904. /* Send commands to erase a block */
  1905. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  1906. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  1907. }
  1908. /**
  1909. * multi_erase_cmd - [GENERIC] AND specific block erase command function
  1910. * @mtd: MTD device structure
  1911. * @page: the page address of the block which will be erased
  1912. *
  1913. * AND multi block erase command function. Erase 4 consecutive blocks.
  1914. */
  1915. static void multi_erase_cmd(struct mtd_info *mtd, int page)
  1916. {
  1917. struct nand_chip *chip = mtd->priv;
  1918. /* Send commands to erase a block */
  1919. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
  1920. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
  1921. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
  1922. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  1923. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  1924. }
  1925. /**
  1926. * nand_erase - [MTD Interface] erase block(s)
  1927. * @mtd: MTD device structure
  1928. * @instr: erase instruction
  1929. *
  1930. * Erase one ore more blocks.
  1931. */
  1932. static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
  1933. {
  1934. return nand_erase_nand(mtd, instr, 0);
  1935. }
  1936. #define BBT_PAGE_MASK 0xffffff3f
  1937. /**
  1938. * nand_erase_nand - [INTERN] erase block(s)
  1939. * @mtd: MTD device structure
  1940. * @instr: erase instruction
  1941. * @allowbbt: allow erasing the bbt area
  1942. *
  1943. * Erase one ore more blocks.
  1944. */
  1945. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  1946. int allowbbt)
  1947. {
  1948. int page, status, pages_per_block, ret, chipnr;
  1949. struct nand_chip *chip = mtd->priv;
  1950. loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
  1951. unsigned int bbt_masked_page = 0xffffffff;
  1952. loff_t len;
  1953. MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
  1954. __func__, (unsigned long long)instr->addr,
  1955. (unsigned long long)instr->len);
  1956. if (check_offs_len(mtd, instr->addr, instr->len))
  1957. return -EINVAL;
  1958. /* Grab the lock and see if the device is available */
  1959. nand_get_device(chip, mtd, FL_ERASING);
  1960. /* Shift to get first page */
  1961. page = (int)(instr->addr >> chip->page_shift);
  1962. chipnr = (int)(instr->addr >> chip->chip_shift);
  1963. /* Calculate pages in each block */
  1964. pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
  1965. /* Select the NAND device */
  1966. chip->select_chip(mtd, chipnr);
  1967. /* Check, if it is write protected */
  1968. if (nand_check_wp(mtd)) {
  1969. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
  1970. __func__);
  1971. instr->state = MTD_ERASE_FAILED;
  1972. goto erase_exit;
  1973. }
  1974. /*
  1975. * If BBT requires refresh, set the BBT page mask to see if the BBT
  1976. * should be rewritten. Otherwise the mask is set to 0xffffffff which
  1977. * can not be matched. This is also done when the bbt is actually
  1978. * erased to avoid recursive updates.
  1979. */
  1980. if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
  1981. bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
  1982. /* Loop through the pages */
  1983. len = instr->len;
  1984. instr->state = MTD_ERASING;
  1985. while (len) {
  1986. WATCHDOG_RESET();
  1987. /* Check if we have a bad block, we do not erase bad blocks! */
  1988. if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
  1989. chip->page_shift, 0, allowbbt)) {
  1990. pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
  1991. __func__, page);
  1992. instr->state = MTD_ERASE_FAILED;
  1993. goto erase_exit;
  1994. }
  1995. /*
  1996. * Invalidate the page cache, if we erase the block which
  1997. * contains the current cached page.
  1998. */
  1999. if (page <= chip->pagebuf && chip->pagebuf <
  2000. (page + pages_per_block))
  2001. chip->pagebuf = -1;
  2002. chip->erase_cmd(mtd, page & chip->pagemask);
  2003. status = chip->waitfunc(mtd, chip);
  2004. /*
  2005. * See if operation failed and additional status checks are
  2006. * available
  2007. */
  2008. if ((status & NAND_STATUS_FAIL) && (chip->errstat))
  2009. status = chip->errstat(mtd, chip, FL_ERASING,
  2010. status, page);
  2011. /* See if block erase succeeded */
  2012. if (status & NAND_STATUS_FAIL) {
  2013. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
  2014. "page 0x%08x\n", __func__, page);
  2015. instr->state = MTD_ERASE_FAILED;
  2016. instr->fail_addr =
  2017. ((loff_t)page << chip->page_shift);
  2018. goto erase_exit;
  2019. }
  2020. /*
  2021. * If BBT requires refresh, set the BBT rewrite flag to the
  2022. * page being erased.
  2023. */
  2024. if (bbt_masked_page != 0xffffffff &&
  2025. (page & BBT_PAGE_MASK) == bbt_masked_page)
  2026. rewrite_bbt[chipnr] =
  2027. ((loff_t)page << chip->page_shift);
  2028. /* Increment page address and decrement length */
  2029. len -= (1 << chip->phys_erase_shift);
  2030. page += pages_per_block;
  2031. /* Check, if we cross a chip boundary */
  2032. if (len && !(page & chip->pagemask)) {
  2033. chipnr++;
  2034. chip->select_chip(mtd, -1);
  2035. chip->select_chip(mtd, chipnr);
  2036. /*
  2037. * If BBT requires refresh and BBT-PERCHIP, set the BBT
  2038. * page mask to see if this BBT should be rewritten.
  2039. */
  2040. if (bbt_masked_page != 0xffffffff &&
  2041. (chip->bbt_td->options & NAND_BBT_PERCHIP))
  2042. bbt_masked_page = chip->bbt_td->pages[chipnr] &
  2043. BBT_PAGE_MASK;
  2044. }
  2045. }
  2046. instr->state = MTD_ERASE_DONE;
  2047. erase_exit:
  2048. ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
  2049. /* Deselect and wake up anyone waiting on the device */
  2050. nand_release_device(mtd);
  2051. /* Do call back function */
  2052. if (!ret)
  2053. mtd_erase_callback(instr);
  2054. /*
  2055. * If BBT requires refresh and erase was successful, rewrite any
  2056. * selected bad block tables.
  2057. */
  2058. if (bbt_masked_page == 0xffffffff || ret)
  2059. return ret;
  2060. for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
  2061. if (!rewrite_bbt[chipnr])
  2062. continue;
  2063. /* Update the BBT for chip */
  2064. MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
  2065. "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
  2066. rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
  2067. nand_update_bbt(mtd, rewrite_bbt[chipnr]);
  2068. }
  2069. /* Return more or less happy */
  2070. return ret;
  2071. }
  2072. /**
  2073. * nand_sync - [MTD Interface] sync
  2074. * @mtd: MTD device structure
  2075. *
  2076. * Sync is actually a wait for chip ready function.
  2077. */
  2078. static void nand_sync(struct mtd_info *mtd)
  2079. {
  2080. struct nand_chip *chip = mtd->priv;
  2081. MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
  2082. /* Grab the lock and see if the device is available */
  2083. nand_get_device(chip, mtd, FL_SYNCING);
  2084. /* Release it and go back */
  2085. nand_release_device(mtd);
  2086. }
  2087. /**
  2088. * nand_block_isbad - [MTD Interface] Check if block at offset is bad
  2089. * @mtd: MTD device structure
  2090. * @offs: offset relative to mtd start
  2091. */
  2092. static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
  2093. {
  2094. return nand_block_checkbad(mtd, offs, 1, 0);
  2095. }
  2096. /**
  2097. * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
  2098. * @mtd: MTD device structure
  2099. * @ofs: offset relative to mtd start
  2100. */
  2101. static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
  2102. {
  2103. struct nand_chip *chip = mtd->priv;
  2104. int ret;
  2105. ret = nand_block_isbad(mtd, ofs);
  2106. if (ret) {
  2107. /* If it was bad already, return success and do nothing */
  2108. if (ret > 0)
  2109. return 0;
  2110. return ret;
  2111. }
  2112. return chip->block_markbad(mtd, ofs);
  2113. }
  2114. /**
  2115. * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
  2116. * @mtd: MTD device structure
  2117. * @chip: nand chip info structure
  2118. * @addr: feature address.
  2119. * @subfeature_param: the subfeature parameters, a four bytes array.
  2120. */
  2121. static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
  2122. int addr, uint8_t *subfeature_param)
  2123. {
  2124. int status;
  2125. if (!chip->onfi_version)
  2126. return -EINVAL;
  2127. chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
  2128. chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
  2129. status = chip->waitfunc(mtd, chip);
  2130. if (status & NAND_STATUS_FAIL)
  2131. return -EIO;
  2132. return 0;
  2133. }
  2134. /**
  2135. * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
  2136. * @mtd: MTD device structure
  2137. * @chip: nand chip info structure
  2138. * @addr: feature address.
  2139. * @subfeature_param: the subfeature parameters, a four bytes array.
  2140. */
  2141. static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
  2142. int addr, uint8_t *subfeature_param)
  2143. {
  2144. if (!chip->onfi_version)
  2145. return -EINVAL;
  2146. /* clear the sub feature parameters */
  2147. memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
  2148. chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
  2149. chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
  2150. return 0;
  2151. }
  2152. /* Set default functions */
  2153. static void nand_set_defaults(struct nand_chip *chip, int busw)
  2154. {
  2155. /* check for proper chip_delay setup, set 20us if not */
  2156. if (!chip->chip_delay)
  2157. chip->chip_delay = 20;
  2158. /* check, if a user supplied command function given */
  2159. if (chip->cmdfunc == NULL)
  2160. chip->cmdfunc = nand_command;
  2161. /* check, if a user supplied wait function given */
  2162. if (chip->waitfunc == NULL)
  2163. chip->waitfunc = nand_wait;
  2164. if (!chip->select_chip)
  2165. chip->select_chip = nand_select_chip;
  2166. if (!chip->read_byte)
  2167. chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
  2168. if (!chip->read_word)
  2169. chip->read_word = nand_read_word;
  2170. if (!chip->block_bad)
  2171. chip->block_bad = nand_block_bad;
  2172. if (!chip->block_markbad)
  2173. chip->block_markbad = nand_default_block_markbad;
  2174. if (!chip->write_buf)
  2175. chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
  2176. if (!chip->read_buf)
  2177. chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
  2178. if (!chip->verify_buf)
  2179. chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
  2180. if (!chip->scan_bbt)
  2181. chip->scan_bbt = nand_default_bbt;
  2182. if (!chip->controller)
  2183. chip->controller = &chip->hwcontrol;
  2184. }
  2185. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  2186. /* Sanitize ONFI strings so we can safely print them */
  2187. static void sanitize_string(char *s, size_t len)
  2188. {
  2189. ssize_t i;
  2190. /* Null terminate */
  2191. s[len - 1] = 0;
  2192. /* Remove non printable chars */
  2193. for (i = 0; i < len - 1; i++) {
  2194. if (s[i] < ' ' || s[i] > 127)
  2195. s[i] = '?';
  2196. }
  2197. /* Remove trailing spaces */
  2198. strim(s);
  2199. }
  2200. static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
  2201. {
  2202. int i;
  2203. while (len--) {
  2204. crc ^= *p++ << 8;
  2205. for (i = 0; i < 8; i++)
  2206. crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
  2207. }
  2208. return crc;
  2209. }
  2210. /*
  2211. * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
  2212. */
  2213. static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
  2214. int *busw)
  2215. {
  2216. struct nand_onfi_params *p = &chip->onfi_params;
  2217. int i;
  2218. int val;
  2219. /* Try ONFI for unknown chip or LP */
  2220. chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
  2221. if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
  2222. chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
  2223. return 0;
  2224. chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
  2225. for (i = 0; i < 3; i++) {
  2226. chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
  2227. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
  2228. le16_to_cpu(p->crc)) {
  2229. pr_info("ONFI param page %d valid\n", i);
  2230. break;
  2231. }
  2232. }
  2233. if (i == 3)
  2234. return 0;
  2235. /* Check version */
  2236. val = le16_to_cpu(p->revision);
  2237. if (val & (1 << 5))
  2238. chip->onfi_version = 23;
  2239. else if (val & (1 << 4))
  2240. chip->onfi_version = 22;
  2241. else if (val & (1 << 3))
  2242. chip->onfi_version = 21;
  2243. else if (val & (1 << 2))
  2244. chip->onfi_version = 20;
  2245. else if (val & (1 << 1))
  2246. chip->onfi_version = 10;
  2247. else
  2248. chip->onfi_version = 0;
  2249. if (!chip->onfi_version) {
  2250. pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
  2251. return 0;
  2252. }
  2253. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  2254. sanitize_string(p->model, sizeof(p->model));
  2255. if (!mtd->name)
  2256. mtd->name = p->model;
  2257. mtd->writesize = le32_to_cpu(p->byte_per_page);
  2258. mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
  2259. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  2260. chip->chipsize = le32_to_cpu(p->blocks_per_lun);
  2261. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  2262. *busw = 0;
  2263. if (le16_to_cpu(p->features) & 1)
  2264. *busw = NAND_BUSWIDTH_16;
  2265. pr_info("ONFI flash detected\n");
  2266. return 1;
  2267. }
  2268. #else
  2269. static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
  2270. struct nand_chip *chip,
  2271. int *busw)
  2272. {
  2273. return 0;
  2274. }
  2275. #endif
  2276. /*
  2277. * nand_id_has_period - Check if an ID string has a given wraparound period
  2278. * @id_data: the ID string
  2279. * @arrlen: the length of the @id_data array
  2280. * @period: the period of repitition
  2281. *
  2282. * Check if an ID string is repeated within a given sequence of bytes at
  2283. * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
  2284. * period of 2). This is a helper function for nand_id_len(). Returns non-zero
  2285. * if the repetition has a period of @period; otherwise, returns zero.
  2286. */
  2287. static int nand_id_has_period(u8 *id_data, int arrlen, int period)
  2288. {
  2289. int i, j;
  2290. for (i = 0; i < period; i++)
  2291. for (j = i + period; j < arrlen; j += period)
  2292. if (id_data[i] != id_data[j])
  2293. return 0;
  2294. return 1;
  2295. }
  2296. /*
  2297. * nand_id_len - Get the length of an ID string returned by CMD_READID
  2298. * @id_data: the ID string
  2299. * @arrlen: the length of the @id_data array
  2300. * Returns the length of the ID string, according to known wraparound/trailing
  2301. * zero patterns. If no pattern exists, returns the length of the array.
  2302. */
  2303. static int nand_id_len(u8 *id_data, int arrlen)
  2304. {
  2305. int last_nonzero, period;
  2306. /* Find last non-zero byte */
  2307. for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
  2308. if (id_data[last_nonzero])
  2309. break;
  2310. /* All zeros */
  2311. if (last_nonzero < 0)
  2312. return 0;
  2313. /* Calculate wraparound period */
  2314. for (period = 1; period < arrlen; period++)
  2315. if (nand_id_has_period(id_data, arrlen, period))
  2316. break;
  2317. /* There's a repeated pattern */
  2318. if (period < arrlen)
  2319. return period;
  2320. /* There are trailing zeros */
  2321. if (last_nonzero < arrlen - 1)
  2322. return last_nonzero + 1;
  2323. /* No pattern detected */
  2324. return arrlen;
  2325. }
  2326. /*
  2327. * Many new NAND share similar device ID codes, which represent the size of the
  2328. * chip. The rest of the parameters must be decoded according to generic or
  2329. * manufacturer-specific "extended ID" decoding patterns.
  2330. */
  2331. static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
  2332. u8 id_data[8], int *busw)
  2333. {
  2334. int extid, id_len;
  2335. /* The 3rd id byte holds MLC / multichip data */
  2336. chip->cellinfo = id_data[2];
  2337. /* The 4th id byte is the important one */
  2338. extid = id_data[3];
  2339. id_len = nand_id_len(id_data, 8);
  2340. /*
  2341. * Field definitions are in the following datasheets:
  2342. * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
  2343. * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
  2344. * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
  2345. *
  2346. * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
  2347. * ID to decide what to do.
  2348. */
  2349. if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
  2350. (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
  2351. id_data[5] != 0x00) {
  2352. /* Calc pagesize */
  2353. mtd->writesize = 2048 << (extid & 0x03);
  2354. extid >>= 2;
  2355. /* Calc oobsize */
  2356. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  2357. case 1:
  2358. mtd->oobsize = 128;
  2359. break;
  2360. case 2:
  2361. mtd->oobsize = 218;
  2362. break;
  2363. case 3:
  2364. mtd->oobsize = 400;
  2365. break;
  2366. case 4:
  2367. mtd->oobsize = 436;
  2368. break;
  2369. case 5:
  2370. mtd->oobsize = 512;
  2371. break;
  2372. case 6:
  2373. default: /* Other cases are "reserved" (unknown) */
  2374. mtd->oobsize = 640;
  2375. break;
  2376. }
  2377. extid >>= 2;
  2378. /* Calc blocksize */
  2379. mtd->erasesize = (128 * 1024) <<
  2380. (((extid >> 1) & 0x04) | (extid & 0x03));
  2381. *busw = 0;
  2382. } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
  2383. (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
  2384. unsigned int tmp;
  2385. /* Calc pagesize */
  2386. mtd->writesize = 2048 << (extid & 0x03);
  2387. extid >>= 2;
  2388. /* Calc oobsize */
  2389. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  2390. case 0:
  2391. mtd->oobsize = 128;
  2392. break;
  2393. case 1:
  2394. mtd->oobsize = 224;
  2395. break;
  2396. case 2:
  2397. mtd->oobsize = 448;
  2398. break;
  2399. case 3:
  2400. mtd->oobsize = 64;
  2401. break;
  2402. case 4:
  2403. mtd->oobsize = 32;
  2404. break;
  2405. case 5:
  2406. mtd->oobsize = 16;
  2407. break;
  2408. default:
  2409. mtd->oobsize = 640;
  2410. break;
  2411. }
  2412. extid >>= 2;
  2413. /* Calc blocksize */
  2414. tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
  2415. if (tmp < 0x03)
  2416. mtd->erasesize = (128 * 1024) << tmp;
  2417. else if (tmp == 0x03)
  2418. mtd->erasesize = 768 * 1024;
  2419. else
  2420. mtd->erasesize = (64 * 1024) << tmp;
  2421. *busw = 0;
  2422. } else {
  2423. /* Calc pagesize */
  2424. mtd->writesize = 1024 << (extid & 0x03);
  2425. extid >>= 2;
  2426. /* Calc oobsize */
  2427. mtd->oobsize = (8 << (extid & 0x01)) *
  2428. (mtd->writesize >> 9);
  2429. extid >>= 2;
  2430. /* Calc blocksize. Blocksize is multiples of 64KiB */
  2431. mtd->erasesize = (64 * 1024) << (extid & 0x03);
  2432. extid >>= 2;
  2433. /* Get buswidth information */
  2434. *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
  2435. }
  2436. }
  2437. /*
  2438. * Old devices have chip data hardcoded in the device ID table. nand_decode_id
  2439. * decodes a matching ID table entry and assigns the MTD size parameters for
  2440. * the chip.
  2441. */
  2442. static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
  2443. const struct nand_flash_dev *type, u8 id_data[8],
  2444. int *busw)
  2445. {
  2446. int maf_id = id_data[0];
  2447. mtd->erasesize = type->erasesize;
  2448. mtd->writesize = type->pagesize;
  2449. mtd->oobsize = mtd->writesize / 32;
  2450. *busw = type->options & NAND_BUSWIDTH_16;
  2451. /*
  2452. * Check for Spansion/AMD ID + repeating 5th, 6th byte since
  2453. * some Spansion chips have erasesize that conflicts with size
  2454. * listed in nand_ids table.
  2455. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
  2456. */
  2457. if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
  2458. && id_data[6] == 0x00 && id_data[7] == 0x00
  2459. && mtd->writesize == 512) {
  2460. mtd->erasesize = 128 * 1024;
  2461. mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
  2462. }
  2463. }
  2464. /*
  2465. * Set the bad block marker/indicator (BBM/BBI) patterns according to some
  2466. * heuristic patterns using various detected parameters (e.g., manufacturer,
  2467. * page size, cell-type information).
  2468. */
  2469. static void nand_decode_bbm_options(struct mtd_info *mtd,
  2470. struct nand_chip *chip, u8 id_data[8])
  2471. {
  2472. int maf_id = id_data[0];
  2473. /* Set the bad block position */
  2474. if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
  2475. chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
  2476. else
  2477. chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
  2478. /*
  2479. * Bad block marker is stored in the last page of each block on Samsung
  2480. * and Hynix MLC devices; stored in first two pages of each block on
  2481. * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
  2482. * AMD/Spansion, and Macronix. All others scan only the first page.
  2483. */
  2484. if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
  2485. (maf_id == NAND_MFR_SAMSUNG ||
  2486. maf_id == NAND_MFR_HYNIX))
  2487. chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
  2488. else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
  2489. (maf_id == NAND_MFR_SAMSUNG ||
  2490. maf_id == NAND_MFR_HYNIX ||
  2491. maf_id == NAND_MFR_TOSHIBA ||
  2492. maf_id == NAND_MFR_AMD ||
  2493. maf_id == NAND_MFR_MACRONIX)) ||
  2494. (mtd->writesize == 2048 &&
  2495. maf_id == NAND_MFR_MICRON))
  2496. chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
  2497. }
  2498. /*
  2499. * Get the flash and manufacturer id and lookup if the type is supported.
  2500. */
  2501. static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
  2502. struct nand_chip *chip,
  2503. int busw,
  2504. int *maf_id, int *dev_id,
  2505. const struct nand_flash_dev *type)
  2506. {
  2507. const char *name;
  2508. int i, maf_idx;
  2509. u8 id_data[8];
  2510. /* Select the device */
  2511. chip->select_chip(mtd, 0);
  2512. /*
  2513. * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
  2514. * after power-up.
  2515. */
  2516. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  2517. /* Send the command for reading device ID */
  2518. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  2519. /* Read manufacturer and device IDs */
  2520. *maf_id = chip->read_byte(mtd);
  2521. *dev_id = chip->read_byte(mtd);
  2522. /*
  2523. * Try again to make sure, as some systems the bus-hold or other
  2524. * interface concerns can cause random data which looks like a
  2525. * possibly credible NAND flash to appear. If the two results do
  2526. * not match, ignore the device completely.
  2527. */
  2528. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  2529. /* Read entire ID string */
  2530. for (i = 0; i < 8; i++)
  2531. id_data[i] = chip->read_byte(mtd);
  2532. if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
  2533. pr_info("%s: second ID read did not match "
  2534. "%02x,%02x against %02x,%02x\n", __func__,
  2535. *maf_id, *dev_id, id_data[0], id_data[1]);
  2536. return ERR_PTR(-ENODEV);
  2537. }
  2538. if (!type)
  2539. type = nand_flash_ids;
  2540. for (; type->name != NULL; type++)
  2541. if (*dev_id == type->id)
  2542. break;
  2543. chip->onfi_version = 0;
  2544. if (!type->name || !type->pagesize) {
  2545. /* Check is chip is ONFI compliant */
  2546. if (nand_flash_detect_onfi(mtd, chip, &busw))
  2547. goto ident_done;
  2548. }
  2549. if (!type->name)
  2550. return ERR_PTR(-ENODEV);
  2551. if (!mtd->name)
  2552. mtd->name = type->name;
  2553. chip->chipsize = (uint64_t)type->chipsize << 20;
  2554. if (!type->pagesize && chip->init_size) {
  2555. /* Set the pagesize, oobsize, erasesize by the driver */
  2556. busw = chip->init_size(mtd, chip, id_data);
  2557. } else if (!type->pagesize) {
  2558. /* Decode parameters from extended ID */
  2559. nand_decode_ext_id(mtd, chip, id_data, &busw);
  2560. } else {
  2561. nand_decode_id(mtd, chip, type, id_data, &busw);
  2562. }
  2563. /* Get chip options, preserve non chip based options */
  2564. chip->options |= type->options;
  2565. /*
  2566. * Check if chip is not a Samsung device. Do not clear the
  2567. * options for chips which do not have an extended id.
  2568. */
  2569. if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
  2570. chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
  2571. ident_done:
  2572. /* Try to identify manufacturer */
  2573. for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
  2574. if (nand_manuf_ids[maf_idx].id == *maf_id)
  2575. break;
  2576. }
  2577. /*
  2578. * Check, if buswidth is correct. Hardware drivers should set
  2579. * chip correct!
  2580. */
  2581. if (busw != (chip->options & NAND_BUSWIDTH_16)) {
  2582. pr_info("NAND device: Manufacturer ID:"
  2583. " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
  2584. *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
  2585. pr_warn("NAND bus width %d instead %d bit\n",
  2586. (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
  2587. busw ? 16 : 8);
  2588. return ERR_PTR(-EINVAL);
  2589. }
  2590. nand_decode_bbm_options(mtd, chip, id_data);
  2591. /* Calculate the address shift from the page size */
  2592. chip->page_shift = ffs(mtd->writesize) - 1;
  2593. /* Convert chipsize to number of pages per chip -1 */
  2594. chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
  2595. chip->bbt_erase_shift = chip->phys_erase_shift =
  2596. ffs(mtd->erasesize) - 1;
  2597. if (chip->chipsize & 0xffffffff)
  2598. chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
  2599. else {
  2600. chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
  2601. chip->chip_shift += 32 - 1;
  2602. }
  2603. chip->badblockbits = 8;
  2604. /* Check for AND chips with 4 page planes */
  2605. if (chip->options & NAND_4PAGE_ARRAY)
  2606. chip->erase_cmd = multi_erase_cmd;
  2607. else
  2608. chip->erase_cmd = single_erase_cmd;
  2609. /* Do not replace user supplied command function! */
  2610. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  2611. chip->cmdfunc = nand_command_lp;
  2612. name = type->name;
  2613. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  2614. if (chip->onfi_version)
  2615. name = chip->onfi_params.model;
  2616. #endif
  2617. pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
  2618. " page size: %d, OOB size: %d\n",
  2619. *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
  2620. name,
  2621. mtd->writesize, mtd->oobsize);
  2622. return type;
  2623. }
  2624. /**
  2625. * nand_scan_ident - [NAND Interface] Scan for the NAND device
  2626. * @mtd: MTD device structure
  2627. * @maxchips: number of chips to scan for
  2628. * @table: alternative NAND ID table
  2629. *
  2630. * This is the first phase of the normal nand_scan() function. It reads the
  2631. * flash ID and sets up MTD fields accordingly.
  2632. *
  2633. * The mtd->owner field must be set to the module of the caller.
  2634. */
  2635. int nand_scan_ident(struct mtd_info *mtd, int maxchips,
  2636. const struct nand_flash_dev *table)
  2637. {
  2638. int i, busw, nand_maf_id, nand_dev_id;
  2639. struct nand_chip *chip = mtd->priv;
  2640. const struct nand_flash_dev *type;
  2641. /* Get buswidth to select the correct functions */
  2642. busw = chip->options & NAND_BUSWIDTH_16;
  2643. /* Set the default functions */
  2644. nand_set_defaults(chip, busw);
  2645. /* Read the flash type */
  2646. type = nand_get_flash_type(mtd, chip, busw,
  2647. &nand_maf_id, &nand_dev_id, table);
  2648. if (IS_ERR(type)) {
  2649. #ifndef CONFIG_SYS_NAND_QUIET_TEST
  2650. pr_warn("No NAND device found\n");
  2651. #endif
  2652. chip->select_chip(mtd, -1);
  2653. return PTR_ERR(type);
  2654. }
  2655. /* Check for a chip array */
  2656. for (i = 1; i < maxchips; i++) {
  2657. chip->select_chip(mtd, i);
  2658. /* See comment in nand_get_flash_type for reset */
  2659. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  2660. /* Send the command for reading device ID */
  2661. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  2662. /* Read manufacturer and device IDs */
  2663. if (nand_maf_id != chip->read_byte(mtd) ||
  2664. nand_dev_id != chip->read_byte(mtd))
  2665. break;
  2666. }
  2667. #ifdef DEBUG
  2668. if (i > 1)
  2669. pr_info("%d NAND chips detected\n", i);
  2670. #endif
  2671. /* Store the number of chips and calc total size for mtd */
  2672. chip->numchips = i;
  2673. mtd->size = i * chip->chipsize;
  2674. return 0;
  2675. }
  2676. /**
  2677. * nand_scan_tail - [NAND Interface] Scan for the NAND device
  2678. * @mtd: MTD device structure
  2679. *
  2680. * This is the second phase of the normal nand_scan() function. It fills out
  2681. * all the uninitialized function pointers with the defaults and scans for a
  2682. * bad block table if appropriate.
  2683. */
  2684. int nand_scan_tail(struct mtd_info *mtd)
  2685. {
  2686. int i;
  2687. struct nand_chip *chip = mtd->priv;
  2688. /* New bad blocks should be marked in OOB, flash-based BBT, or both */
  2689. BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
  2690. !(chip->bbt_options & NAND_BBT_USE_FLASH));
  2691. if (!(chip->options & NAND_OWN_BUFFERS))
  2692. chip->buffers = memalign(ARCH_DMA_MINALIGN,
  2693. sizeof(*chip->buffers));
  2694. if (!chip->buffers)
  2695. return -ENOMEM;
  2696. /* Set the internal oob buffer location, just after the page data */
  2697. chip->oob_poi = chip->buffers->databuf + mtd->writesize;
  2698. /*
  2699. * If no default placement scheme is given, select an appropriate one.
  2700. */
  2701. if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
  2702. switch (mtd->oobsize) {
  2703. case 8:
  2704. chip->ecc.layout = &nand_oob_8;
  2705. break;
  2706. case 16:
  2707. chip->ecc.layout = &nand_oob_16;
  2708. break;
  2709. case 64:
  2710. chip->ecc.layout = &nand_oob_64;
  2711. break;
  2712. case 128:
  2713. chip->ecc.layout = &nand_oob_128;
  2714. break;
  2715. default:
  2716. pr_warn("No oob scheme defined for oobsize %d\n",
  2717. mtd->oobsize);
  2718. }
  2719. }
  2720. if (!chip->write_page)
  2721. chip->write_page = nand_write_page;
  2722. /* set for ONFI nand */
  2723. if (!chip->onfi_set_features)
  2724. chip->onfi_set_features = nand_onfi_set_features;
  2725. if (!chip->onfi_get_features)
  2726. chip->onfi_get_features = nand_onfi_get_features;
  2727. /*
  2728. * Check ECC mode, default to software if 3byte/512byte hardware ECC is
  2729. * selected and we have 256 byte pagesize fallback to software ECC
  2730. */
  2731. switch (chip->ecc.mode) {
  2732. case NAND_ECC_HW_OOB_FIRST:
  2733. /* Similar to NAND_ECC_HW, but a separate read_page handle */
  2734. if (!chip->ecc.calculate || !chip->ecc.correct ||
  2735. !chip->ecc.hwctl) {
  2736. pr_warn("No ECC functions supplied; "
  2737. "hardware ECC not possible\n");
  2738. BUG();
  2739. }
  2740. if (!chip->ecc.read_page)
  2741. chip->ecc.read_page = nand_read_page_hwecc_oob_first;
  2742. case NAND_ECC_HW:
  2743. /* Use standard hwecc read page function? */
  2744. if (!chip->ecc.read_page)
  2745. chip->ecc.read_page = nand_read_page_hwecc;
  2746. if (!chip->ecc.write_page)
  2747. chip->ecc.write_page = nand_write_page_hwecc;
  2748. if (!chip->ecc.read_page_raw)
  2749. chip->ecc.read_page_raw = nand_read_page_raw;
  2750. if (!chip->ecc.write_page_raw)
  2751. chip->ecc.write_page_raw = nand_write_page_raw;
  2752. if (!chip->ecc.read_oob)
  2753. chip->ecc.read_oob = nand_read_oob_std;
  2754. if (!chip->ecc.write_oob)
  2755. chip->ecc.write_oob = nand_write_oob_std;
  2756. case NAND_ECC_HW_SYNDROME:
  2757. if ((!chip->ecc.calculate || !chip->ecc.correct ||
  2758. !chip->ecc.hwctl) &&
  2759. (!chip->ecc.read_page ||
  2760. chip->ecc.read_page == nand_read_page_hwecc ||
  2761. !chip->ecc.write_page ||
  2762. chip->ecc.write_page == nand_write_page_hwecc)) {
  2763. pr_warn("No ECC functions supplied; "
  2764. "hardware ECC not possible\n");
  2765. BUG();
  2766. }
  2767. /* Use standard syndrome read/write page function? */
  2768. if (!chip->ecc.read_page)
  2769. chip->ecc.read_page = nand_read_page_syndrome;
  2770. if (!chip->ecc.write_page)
  2771. chip->ecc.write_page = nand_write_page_syndrome;
  2772. if (!chip->ecc.read_page_raw)
  2773. chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
  2774. if (!chip->ecc.write_page_raw)
  2775. chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
  2776. if (!chip->ecc.read_oob)
  2777. chip->ecc.read_oob = nand_read_oob_syndrome;
  2778. if (!chip->ecc.write_oob)
  2779. chip->ecc.write_oob = nand_write_oob_syndrome;
  2780. if (mtd->writesize >= chip->ecc.size) {
  2781. if (!chip->ecc.strength) {
  2782. pr_warn("Driver must set ecc.strength when using hardware ECC\n");
  2783. BUG();
  2784. }
  2785. break;
  2786. }
  2787. pr_warn("%d byte HW ECC not possible on "
  2788. "%d byte page size, fallback to SW ECC\n",
  2789. chip->ecc.size, mtd->writesize);
  2790. chip->ecc.mode = NAND_ECC_SOFT;
  2791. case NAND_ECC_SOFT:
  2792. chip->ecc.calculate = nand_calculate_ecc;
  2793. chip->ecc.correct = nand_correct_data;
  2794. chip->ecc.read_page = nand_read_page_swecc;
  2795. chip->ecc.read_subpage = nand_read_subpage;
  2796. chip->ecc.write_page = nand_write_page_swecc;
  2797. chip->ecc.read_page_raw = nand_read_page_raw;
  2798. chip->ecc.write_page_raw = nand_write_page_raw;
  2799. chip->ecc.read_oob = nand_read_oob_std;
  2800. chip->ecc.write_oob = nand_write_oob_std;
  2801. if (!chip->ecc.size)
  2802. chip->ecc.size = 256;
  2803. chip->ecc.bytes = 3;
  2804. chip->ecc.strength = 1;
  2805. break;
  2806. case NAND_ECC_SOFT_BCH:
  2807. if (!mtd_nand_has_bch()) {
  2808. pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
  2809. return -EINVAL;
  2810. }
  2811. chip->ecc.calculate = nand_bch_calculate_ecc;
  2812. chip->ecc.correct = nand_bch_correct_data;
  2813. chip->ecc.read_page = nand_read_page_swecc;
  2814. chip->ecc.read_subpage = nand_read_subpage;
  2815. chip->ecc.write_page = nand_write_page_swecc;
  2816. chip->ecc.read_page_raw = nand_read_page_raw;
  2817. chip->ecc.write_page_raw = nand_write_page_raw;
  2818. chip->ecc.read_oob = nand_read_oob_std;
  2819. chip->ecc.write_oob = nand_write_oob_std;
  2820. /*
  2821. * Board driver should supply ecc.size and ecc.bytes values to
  2822. * select how many bits are correctable; see nand_bch_init()
  2823. * for details. Otherwise, default to 4 bits for large page
  2824. * devices.
  2825. */
  2826. if (!chip->ecc.size && (mtd->oobsize >= 64)) {
  2827. chip->ecc.size = 512;
  2828. chip->ecc.bytes = 7;
  2829. }
  2830. chip->ecc.priv = nand_bch_init(mtd,
  2831. chip->ecc.size,
  2832. chip->ecc.bytes,
  2833. &chip->ecc.layout);
  2834. if (!chip->ecc.priv)
  2835. pr_warn("BCH ECC initialization failed!\n");
  2836. chip->ecc.strength =
  2837. chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
  2838. break;
  2839. case NAND_ECC_NONE:
  2840. pr_warn("NAND_ECC_NONE selected by board driver. "
  2841. "This is not recommended !!\n");
  2842. chip->ecc.read_page = nand_read_page_raw;
  2843. chip->ecc.write_page = nand_write_page_raw;
  2844. chip->ecc.read_oob = nand_read_oob_std;
  2845. chip->ecc.read_page_raw = nand_read_page_raw;
  2846. chip->ecc.write_page_raw = nand_write_page_raw;
  2847. chip->ecc.write_oob = nand_write_oob_std;
  2848. chip->ecc.size = mtd->writesize;
  2849. chip->ecc.bytes = 0;
  2850. break;
  2851. default:
  2852. pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
  2853. BUG();
  2854. }
  2855. /* For many systems, the standard OOB write also works for raw */
  2856. if (!chip->ecc.read_oob_raw)
  2857. chip->ecc.read_oob_raw = chip->ecc.read_oob;
  2858. if (!chip->ecc.write_oob_raw)
  2859. chip->ecc.write_oob_raw = chip->ecc.write_oob;
  2860. /*
  2861. * The number of bytes available for a client to place data into
  2862. * the out of band area.
  2863. */
  2864. chip->ecc.layout->oobavail = 0;
  2865. for (i = 0; chip->ecc.layout->oobfree[i].length
  2866. && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
  2867. chip->ecc.layout->oobavail +=
  2868. chip->ecc.layout->oobfree[i].length;
  2869. mtd->oobavail = chip->ecc.layout->oobavail;
  2870. /*
  2871. * Set the number of read / write steps for one page depending on ECC
  2872. * mode.
  2873. */
  2874. chip->ecc.steps = mtd->writesize / chip->ecc.size;
  2875. if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
  2876. pr_warn("Invalid ECC parameters\n");
  2877. BUG();
  2878. }
  2879. chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
  2880. /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
  2881. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
  2882. !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
  2883. switch (chip->ecc.steps) {
  2884. case 2:
  2885. mtd->subpage_sft = 1;
  2886. break;
  2887. case 4:
  2888. case 8:
  2889. case 16:
  2890. mtd->subpage_sft = 2;
  2891. break;
  2892. }
  2893. }
  2894. chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
  2895. /* Initialize state */
  2896. chip->state = FL_READY;
  2897. /* De-select the device */
  2898. chip->select_chip(mtd, -1);
  2899. /* Invalidate the pagebuffer reference */
  2900. chip->pagebuf = -1;
  2901. /* Large page NAND with SOFT_ECC should support subpage reads */
  2902. if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
  2903. chip->options |= NAND_SUBPAGE_READ;
  2904. /* Fill in remaining MTD driver data */
  2905. mtd->type = MTD_NANDFLASH;
  2906. mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
  2907. MTD_CAP_NANDFLASH;
  2908. mtd->_erase = nand_erase;
  2909. mtd->_point = NULL;
  2910. mtd->_unpoint = NULL;
  2911. mtd->_read = nand_read;
  2912. mtd->_write = nand_write;
  2913. mtd->_read_oob = nand_read_oob;
  2914. mtd->_write_oob = nand_write_oob;
  2915. mtd->_sync = nand_sync;
  2916. mtd->_lock = NULL;
  2917. mtd->_unlock = NULL;
  2918. mtd->_block_isbad = nand_block_isbad;
  2919. mtd->_block_markbad = nand_block_markbad;
  2920. /* propagate ecc info to mtd_info */
  2921. mtd->ecclayout = chip->ecc.layout;
  2922. mtd->ecc_strength = chip->ecc.strength;
  2923. /*
  2924. * Initialize bitflip_threshold to its default prior scan_bbt() call.
  2925. * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
  2926. * properly set.
  2927. */
  2928. if (!mtd->bitflip_threshold)
  2929. mtd->bitflip_threshold = mtd->ecc_strength;
  2930. /* Check, if we should skip the bad block table scan */
  2931. if (chip->options & NAND_SKIP_BBTSCAN)
  2932. chip->options |= NAND_BBT_SCANNED;
  2933. return 0;
  2934. }
  2935. /**
  2936. * nand_scan - [NAND Interface] Scan for the NAND device
  2937. * @mtd: MTD device structure
  2938. * @maxchips: number of chips to scan for
  2939. *
  2940. * This fills out all the uninitialized function pointers with the defaults.
  2941. * The flash ID is read and the mtd/chip structures are filled with the
  2942. * appropriate values. The mtd->owner field must be set to the module of the
  2943. * caller.
  2944. */
  2945. int nand_scan(struct mtd_info *mtd, int maxchips)
  2946. {
  2947. int ret;
  2948. ret = nand_scan_ident(mtd, maxchips, NULL);
  2949. if (!ret)
  2950. ret = nand_scan_tail(mtd);
  2951. return ret;
  2952. }
  2953. /**
  2954. * nand_release - [NAND Interface] Free resources held by the NAND device
  2955. * @mtd: MTD device structure
  2956. */
  2957. void nand_release(struct mtd_info *mtd)
  2958. {
  2959. struct nand_chip *chip = mtd->priv;
  2960. if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
  2961. nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
  2962. #ifdef CONFIG_MTD_PARTITIONS
  2963. /* Deregister partitions */
  2964. del_mtd_partitions(mtd);
  2965. #endif
  2966. /* Free bad block table memory */
  2967. kfree(chip->bbt);
  2968. if (!(chip->options & NAND_OWN_BUFFERS))
  2969. kfree(chip->buffers);
  2970. /* Free bad block descriptor memory */
  2971. if (chip->badblock_pattern && chip->badblock_pattern->options
  2972. & NAND_BBT_DYNAMICSTRUCT)
  2973. kfree(chip->badblock_pattern);
  2974. }