fsl_upm.c 4.4 KB

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  1. /*
  2. * FSL UPM NAND driver
  3. *
  4. * Copyright (C) 2007 MontaVista Software, Inc.
  5. * Anton Vorontsov <avorontsov@ru.mvista.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <asm/errno.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/fsl_upm.h>
  15. #include <nand.h>
  16. static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
  17. {
  18. clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
  19. (void)in_be32(upm->mxmr);
  20. }
  21. static void fsl_upm_end_pattern(struct fsl_upm *upm)
  22. {
  23. clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
  24. while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
  25. eieio();
  26. }
  27. static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
  28. void __iomem *io_addr, u32 mar)
  29. {
  30. out_be32(upm->mar, mar);
  31. (void)in_be32(upm->mar);
  32. switch (width) {
  33. case 8:
  34. out_8(io_addr, 0x0);
  35. break;
  36. case 16:
  37. out_be16(io_addr, 0x0);
  38. break;
  39. case 32:
  40. out_be32(io_addr, 0x0);
  41. break;
  42. }
  43. }
  44. static void fun_wait(struct fsl_upm_nand *fun)
  45. {
  46. if (fun->dev_ready) {
  47. while (!fun->dev_ready(fun->chip_nr))
  48. debug("unexpected busy state\n");
  49. } else {
  50. /*
  51. * If the R/B pin is not connected,
  52. * a short delay is necessary.
  53. */
  54. udelay(1);
  55. }
  56. }
  57. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  58. static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
  59. {
  60. struct nand_chip *chip = mtd->priv;
  61. struct fsl_upm_nand *fun = chip->priv;
  62. if (chip_nr >= 0) {
  63. fun->chip_nr = chip_nr;
  64. chip->IO_ADDR_R = chip->IO_ADDR_W =
  65. fun->upm.io_addr + fun->chip_offset * chip_nr;
  66. } else if (chip_nr == -1) {
  67. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  68. }
  69. }
  70. #endif
  71. static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  72. {
  73. struct nand_chip *chip = mtd->priv;
  74. struct fsl_upm_nand *fun = chip->priv;
  75. void __iomem *io_addr;
  76. u32 mar;
  77. if (!(ctrl & fun->last_ctrl)) {
  78. fsl_upm_end_pattern(&fun->upm);
  79. if (cmd == NAND_CMD_NONE)
  80. return;
  81. fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  82. }
  83. if (ctrl & NAND_CTRL_CHANGE) {
  84. if (ctrl & NAND_ALE)
  85. fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
  86. else if (ctrl & NAND_CLE)
  87. fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
  88. }
  89. mar = cmd << (32 - fun->width);
  90. io_addr = fun->upm.io_addr;
  91. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  92. if (fun->chip_nr > 0) {
  93. io_addr += fun->chip_offset * fun->chip_nr;
  94. if (fun->upm_mar_chip_offset)
  95. mar |= fun->upm_mar_chip_offset * fun->chip_nr;
  96. }
  97. #endif
  98. fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
  99. /*
  100. * Some boards/chips needs this. At least the MPC8360E-RDK
  101. * needs it. Probably weird chip, because I don't see any
  102. * need for this on MPC8555E + Samsung K9F1G08U0A. Usually
  103. * here are 0-2 unexpected busy states per block read.
  104. */
  105. if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
  106. fun_wait(fun);
  107. }
  108. static u8 upm_nand_read_byte(struct mtd_info *mtd)
  109. {
  110. struct nand_chip *chip = mtd->priv;
  111. return in_8(chip->IO_ADDR_R);
  112. }
  113. static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  114. {
  115. int i;
  116. struct nand_chip *chip = mtd->priv;
  117. struct fsl_upm_nand *fun = chip->priv;
  118. for (i = 0; i < len; i++) {
  119. out_8(chip->IO_ADDR_W, buf[i]);
  120. if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
  121. fun_wait(fun);
  122. }
  123. if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
  124. fun_wait(fun);
  125. }
  126. static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  127. {
  128. int i;
  129. struct nand_chip *chip = mtd->priv;
  130. for (i = 0; i < len; i++)
  131. buf[i] = in_8(chip->IO_ADDR_R);
  132. }
  133. static int upm_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
  134. {
  135. int i;
  136. struct nand_chip *chip = mtd->priv;
  137. for (i = 0; i < len; i++) {
  138. if (buf[i] != in_8(chip->IO_ADDR_R))
  139. return -EFAULT;
  140. }
  141. return 0;
  142. }
  143. static int nand_dev_ready(struct mtd_info *mtd)
  144. {
  145. struct nand_chip *chip = mtd->priv;
  146. struct fsl_upm_nand *fun = chip->priv;
  147. return fun->dev_ready(fun->chip_nr);
  148. }
  149. int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
  150. {
  151. if (fun->width != 8 && fun->width != 16 && fun->width != 32)
  152. return -ENOSYS;
  153. fun->last_ctrl = NAND_CLE;
  154. chip->priv = fun;
  155. chip->chip_delay = fun->chip_delay;
  156. chip->ecc.mode = NAND_ECC_SOFT;
  157. chip->cmd_ctrl = fun_cmd_ctrl;
  158. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  159. chip->select_chip = fun_select_chip;
  160. #endif
  161. chip->read_byte = upm_nand_read_byte;
  162. chip->read_buf = upm_nand_read_buf;
  163. chip->write_buf = upm_nand_write_buf;
  164. chip->verify_buf = upm_nand_verify_buf;
  165. if (fun->dev_ready)
  166. chip->dev_ready = nand_dev_ready;
  167. return 0;
  168. }