README.mxsimage 6.5 KB

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  1. Freescale i.MX233/i.MX28 SB image generator via mkimage
  2. =======================================================
  3. This tool allows user to produce SB BootStream encrypted with a zero key.
  4. Such a BootStream is then bootable on i.MX23/i.MX28.
  5. Usage -- producing image:
  6. =========================
  7. The mxsimage tool is targeted to be a simple replacement for the elftosb2 .
  8. To generate an image, write an image configuration file and run:
  9. mkimage -A arm -O u-boot -T mxsimage -n <path to configuration file> \
  10. <output bootstream file>
  11. The output bootstream file is usually using the .sb file extension. Note
  12. that the example configuration files for producing bootable BootStream with
  13. the U-Boot bootloader can be found under arch/arm/boot/cpu/arm926ejs/mxs/
  14. directory. See the following files:
  15. mxsimage.mx23.cfg -- This is an example configuration for i.MX23
  16. mxsimage.mx28.cfg -- This is an example configuration for i.MX28
  17. Each configuration file uses very simple instruction semantics and a few
  18. additional rules have to be followed so that a useful image can be produced.
  19. These semantics and rules will be outlined now.
  20. - Each line of the configuration file contains exactly one instruction.
  21. - Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 .
  22. - The configuration file is a concatenation of blocks called "sections" and
  23. optionally "DCD blocks" (see below).
  24. - Each "section" is started by the "SECTION" instruction.
  25. - The "SECTION" instruction has the following semantics:
  26. SECTION u32_section_number [BOOTABLE]
  27. - u32_section_number :: User-selected ID of the section
  28. - BOOTABLE :: Sets the section as bootable
  29. - A bootable section is one from which the BootROM starts executing
  30. subsequent instructions or code. Exactly one section must be selected
  31. as bootable, usually the one containing the instructions and data to
  32. load the bootloader.
  33. - A "SECTION" must be immediatelly followed by a "TAG" instruction.
  34. - The "TAG" instruction has the following semantics:
  35. TAG [LAST]
  36. - LAST :: Flag denoting the last section in the file
  37. - After a "TAG" unstruction, any of the following instructions may follow
  38. in any order and any quantity:
  39. NOOP
  40. - This instruction does nothing
  41. LOAD u32_address string_filename
  42. - Instructs the BootROM to load file pointed by "string_filename" onto
  43. address "u32_address".
  44. LOAD IVT u32_address u32_IVT_entry_point
  45. - Crafts and loads IVT onto address "u32_address" with the entry point
  46. of u32_IVT_entry_point.
  47. - i.MX28-specific instruction!
  48. LOAD DCD u32_address u32_DCD_block_ID
  49. - Loads the DCD block with ID "u32_DCD_block_ID" onto address
  50. "u32_address" and executes the contents of this DCD block
  51. - i.MX28-specific instruction!
  52. FILL u32_address u32_pattern u32_length
  53. - Starts to write memory from addres "u32_address" with a pattern
  54. specified by "u32_pattern". Writes exactly "u32_length" bytes of the
  55. pattern.
  56. JUMP [HAB] u32_address [u32_r0_arg]
  57. - Jumps onto memory address specified by "u32_address" by setting this
  58. address in PT. The BootROM will pass the "u32_r0_arg" value in ARM
  59. register "r0" to the executed code if this option is specified.
  60. Otherwise, ARM register "r0" will default to value 0x00000000. The
  61. optional "HAB" flag is i.MX28-specific flag turning on the HAB boot.
  62. CALL [HAB] u32_address [u32_r0_arg]
  63. - See JUMP instruction above, as the operation is exactly the same with
  64. one difference. The CALL instruction does allow returning into the
  65. BootROM from the executed code. U-Boot makes use of this in it's SPL
  66. code.
  67. MODE string_mode
  68. - Restart the CPU and start booting from device specified by the
  69. "string_mode" argument. The "string_mode" differs for each CPU
  70. and can be:
  71. i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH
  72. JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1
  73. i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH
  74. JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1
  75. - An optional "DCD" blocks can be added at the begining of the configuration
  76. file. Note that the DCD is only supported on i.MX28.
  77. - The DCD blocks must be inserted before the first "section" in the
  78. configuration file.
  79. - The DCD block has the following semantics:
  80. DCD u32_DCD_block_ID
  81. - u32_DCD_block_ID :: The ID number of the DCD block, must match
  82. the ID number used by "LOAD DCD" instruction.
  83. - The DCD block must be followed by one of the following instructions. All
  84. of the instructions operate either on 1, 2 or 4 bytes. This is selected by
  85. the 'n' suffix of the instruction:
  86. WRITE.n u32_address u32_value
  87. - Write the "u32_value" to the "u32_address" address.
  88. ORR.n u32_address u32_value
  89. - Read the "u32_address", perform a bitwise-OR with the "u32_value" and
  90. write the result back to "u32_address".
  91. ANDC.n u32_address u32_value
  92. - Read the "u32_address", perform a bitwise-AND with the complement of
  93. "u32_value" and write the result back to "u32_address".
  94. EQZ.n u32_address u32_count
  95. - Read the "u32_address" at most "u32_count" times and test if the value
  96. read is zero. If it is, break the loop earlier.
  97. NEZ.n u32_address u32_count
  98. - Read the "u32_address" at most "u32_count" times and test if the value
  99. read is non-zero. If it is, break the loop earlier.
  100. EQ.n u32_address u32_mask
  101. - Read the "u32_address" in a loop and test if the result masked with
  102. "u32_mask" equals the "u32_mask". If the values are equal, break the
  103. reading loop.
  104. NEQ.n u32_address u32_mask
  105. - Read the "u32_address" in a loop and test if the result masked with
  106. "u32_mask" does not equal the "u32_mask". If the values are not equal,
  107. break the reading loop.
  108. NOOP
  109. - This instruction does nothing.
  110. - If the verbose output from the BootROM is enabled, the BootROM will produce a
  111. letter on the Debug UART for each instruction it started processing. Here is a
  112. mapping between the above instructions and the BootROM verbose output:
  113. H -- SB Image header loaded
  114. T -- TAG instruction
  115. N -- NOOP instruction
  116. L -- LOAD instruction
  117. F -- FILL instruction
  118. J -- JUMP instruction
  119. C -- CALL instruction
  120. M -- MODE instruction
  121. Usage -- verifying image:
  122. =========================
  123. The mxsimage can also verify and dump contents of an image. Use the following
  124. syntax to verify and dump contents of an image:
  125. mkimage -l <input bootstream file>
  126. This will output all the information from the SB image header and all the
  127. instructions contained in the SB image. It will also check if the various
  128. checksums in the SB image are correct.