or1ksim.cfg 18 KB

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  1. /* sim.cfg -- Simulator configuration script file
  2. Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
  3. This file is part of OpenRISC 1000 Architectural Simulator.
  4. It contains the default configuration and help about configuring
  5. the simulator.
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. /* INTRODUCTION
  9. The ork1sim has various parameters, that are set in configuration files
  10. like this one. The user can switch between configurations at startup by
  11. specifying the required configuration file with the -f <filename.cfg> option.
  12. If no configuration file is specified or1ksim searches for the default
  13. configuration file sim.cfg. First it searches for './sim.cfg'. If this
  14. file is not found, it searches for '~/or1k/sim.cfg'. If this file is
  15. not found too, it reverts to the built-in default configuration.
  16. NOTE: Users should not rely on the built-in configuration, since the
  17. default configuration may differ between version.
  18. Rather create a configuration file that sets all critical values.
  19. This file may contain (standard C) comments only - no // support.
  20. Configure files may be be included, using:
  21. include "file_name_to_include"
  22. Like normal configuration files, the included file is divided into
  23. sections. Each section is described in detail also.
  24. Some section have subsections. One example of such a subsection is:
  25. device <index>
  26. instance specific parameters...
  27. enddevice
  28. which creates a device instance.
  29. */
  30. /* MEMORY SECTION
  31. This section specifies how the memory is generated and the blocks
  32. it consists of.
  33. type = random/unknown/pattern
  34. Specifies the initial memory values.
  35. 'random' generates random memory using seed 'random_seed'.
  36. 'pattern' fills memory with 'pattern'.
  37. 'unknown' does not specify how memory should be generated,
  38. leaving the memory in a undefined state. This is the fastest
  39. option.
  40. random_seed = <value>
  41. random seed for randomizer, used if type = 'random'.
  42. pattern = <value>
  43. pattern to fill memory, used if type = 'pattern'.
  44. nmemories = <value>
  45. number of memory instances connected
  46. baseaddr = <hex_value>
  47. memory start address
  48. size = <hex_value>
  49. memory size
  50. name = "<string>"
  51. memory block name
  52. ce = <value>
  53. chip enable index of the memory instance
  54. mc = <value>
  55. memory controller this memory is connected to
  56. delayr = <value>
  57. cycles, required for read access, -1 if instance does not support reading
  58. delayw = <value>
  59. cycles, required for write access, -1 if instance does not support writing
  60. log = "<filename>"
  61. filename, where to log memory accesses to, no log, if log command is not specified
  62. */
  63. section memory
  64. pattern = 0x00
  65. type = unknown /* Fastest */
  66. name = "FLASH"
  67. ce = 0
  68. mc = 0
  69. baseaddr = 0xf0000000
  70. size = 0x01000000
  71. delayr = 1
  72. delayw = -1
  73. end
  74. section memory
  75. pattern = 0x00
  76. type = unknown /* Fastest */
  77. name = "RAM"
  78. ce = 1
  79. mc = 0
  80. baseaddr = 0x00000000
  81. size = 0x02000000
  82. delayr = 1
  83. delayw = 1
  84. end
  85. section memory
  86. pattern = 0x00
  87. type = unknown /* Fastest */
  88. name = "SRAM"
  89. mc = 0
  90. ce = 2
  91. baseaddr = 0xa4000000
  92. size = 0x00100000
  93. delayr = 1
  94. delayw = 2
  95. end
  96. /* IMMU SECTION
  97. This section configures the Instruction Memory Manangement Unit
  98. enabled = 0/1
  99. '0': disabled
  100. '1': enabled
  101. (NOTE: UPR bit is set)
  102. nsets = <value>
  103. number of ITLB sets; must be power of two
  104. nways = <value>
  105. number of ITLB ways
  106. pagesize = <value>
  107. instruction page size; must be power of two
  108. entrysize = <value>
  109. instruction entry size in bytes
  110. ustates = <value>
  111. number of ITLB usage states (2, 3, 4 etc., max is 4)
  112. hitdelay = <value>
  113. number of cycles immu hit costs
  114. missdelay = <value>
  115. number of cycles immu miss costs
  116. */
  117. section immu
  118. enabled = 1
  119. nsets = 64
  120. nways = 1
  121. pagesize = 8192
  122. hitdelay = 0
  123. missdelay = 0
  124. end
  125. /* DMMU SECTION
  126. This section configures the Data Memory Manangement Unit
  127. enabled = 0/1
  128. '0': disabled
  129. '1': enabled
  130. (NOTE: UPR bit is set)
  131. nsets = <value>
  132. number of DTLB sets; must be power of two
  133. nways = <value>
  134. number of DTLB ways
  135. pagesize = <value>
  136. data page size; must be power of two
  137. entrysize = <value>
  138. data entry size in bytes
  139. ustates = <value>
  140. number of DTLB usage states (2, 3, 4 etc., max is 4)
  141. hitdelay = <value>
  142. number of cycles dmmu hit costs
  143. missdelay = <value>
  144. number of cycles dmmu miss costs
  145. */
  146. section dmmu
  147. enabled = 1
  148. nsets = 64
  149. nways = 1
  150. pagesize = 8192
  151. hitdelay = 0
  152. missdelay = 0
  153. end
  154. /* IC SECTION
  155. This section configures the Instruction Cache
  156. enabled = 0/1
  157. '0': disabled
  158. '1': enabled
  159. (NOTE: UPR bit is set)
  160. nsets = <value>
  161. number of IC sets; must be power of two
  162. nways = <value>
  163. number of IC ways
  164. blocksize = <value>
  165. IC block size in bytes; must be power of two
  166. ustates = <value>
  167. number of IC usage states (2, 3, 4 etc., max is 4)
  168. hitdelay = <value>
  169. number of cycles ic hit costs
  170. missdelay = <value>
  171. number of cycles ic miss costs
  172. */
  173. section ic
  174. enabled = 1
  175. nsets = 512
  176. nways = 1
  177. blocksize = 16
  178. hitdelay = 1
  179. missdelay = 1
  180. end
  181. /* DC SECTION
  182. This section configures the Data Cache
  183. enabled = 0/1
  184. '0': disabled
  185. '1': enabled
  186. (NOTE: UPR bit is set)
  187. nsets = <value>
  188. number of DC sets; must be power of two
  189. nways = <value>
  190. number of DC ways
  191. blocksize = <value>
  192. DC block size in bytes; must be power of two
  193. ustates = <value>
  194. number of DC usage states (2, 3, 4 etc., max is 4)
  195. load_hitdelay = <value>
  196. number of cycles dc load hit costs
  197. load_missdelay = <value>
  198. number of cycles dc load miss costs
  199. store_hitdelay = <value>
  200. number of cycles dc load hit costs
  201. store_missdelay = <value>
  202. number of cycles dc load miss costs
  203. */
  204. section dc
  205. enabled = 1
  206. nsets = 512
  207. nways = 1
  208. blocksize = 16
  209. load_hitdelay = 1
  210. load_missdelay = 1
  211. store_hitdelay = 1
  212. store_missdelay = 1
  213. end
  214. /* SIM SECTION
  215. This section specifies how or1ksim should behave.
  216. verbose = 0/1
  217. '0': don't print extra messages
  218. '1': print extra messages
  219. debug = 0-9
  220. 0 : no debug messages
  221. 1-9: debug message level.
  222. higher numbers produce more messages
  223. profile = 0/1
  224. '0': don't generate profiling file 'sim.profile'
  225. '1': don't generate profiling file 'sim.profile'
  226. prof_fn = "<filename>"
  227. optional filename for the profiling file.
  228. valid only if 'profile' is set
  229. mprofile = 0/1
  230. '0': don't generate memory profiling file 'sim.mprofile'
  231. '1': generate memory profiling file 'sim.mprofile'
  232. mprof_fn = "<filename>"
  233. optional filename for the memory profiling file.
  234. valid only if 'mprofile' is set
  235. history = 0/1
  236. '0': don't track execution flow
  237. '1': track execution flow
  238. Execution flow can be tracked for the simulator's
  239. 'hist' command. Useful for back-trace debugging.
  240. iprompt = 0/1
  241. '0': start in <not interactive prompt> (so what do we start in ???)
  242. '1': start in interactive prompt.
  243. exe_log = 0/1
  244. '0': don't generate execution log.
  245. '1': generate execution log.
  246. exe_log = default/hardware/simple/software
  247. type of execution log, default is used when not specified
  248. exe_log_start = <value>
  249. index of first instruction to start logging, default = 0
  250. exe_log_end = <value>
  251. index of last instruction to end logging; not limited, if omitted
  252. exe_log_marker = <value>
  253. <value> specifies number of instructions before horizontal marker is
  254. printed; if zero, markers are disabled (default)
  255. exe_log_fn = "<filename>"
  256. filename for the exection log file.
  257. valid only if 'exe_log' is set
  258. clkcycle = <value>[ps|ns|us|ms]
  259. specifies time measurement for one cycle
  260. */
  261. section sim
  262. verbose = 1
  263. debug = 0
  264. profile = 0
  265. history = 0
  266. clkcycle = 10ns
  267. end
  268. /* SECTION VAPI
  269. This section configures the Verification API, used for Advanced
  270. Core Verification.
  271. enabled = 0/1
  272. '0': disbable VAPI server
  273. '1': enable/start VAPI server
  274. server_port = <value>
  275. TCP/IP port to start VAPI server on
  276. log_enabled = 0/1
  277. '0': disable VAPI requests logging
  278. '1': enable VAPI requests logging
  279. hide_device_id = 0/1
  280. '0': don't log device id (for compatability with old version)
  281. '1': log device id
  282. vapi_fn = <filename>
  283. filename for the log file.
  284. valid only if log_enabled is set
  285. */
  286. section VAPI
  287. enabled = 0
  288. server_port = 9998
  289. log_enabled = 0
  290. vapi_log_fn = "vapi.log"
  291. end
  292. /* CPU SECTION
  293. This section specifies various CPU parameters.
  294. ver = <value>
  295. rev = <value>
  296. specifies version and revision of the CPU used
  297. upr = <value>
  298. changes the upr register
  299. sr = <value>
  300. sets the initial Supervision Register value
  301. supervisor mode (SM) and fixed one (FO) set = 0x8001
  302. exception prefix high (EPH, vectors@0xf0000000) = 0x4000
  303. together, (SM | FO | EPH) = 0xc001
  304. superscalar = 0/1
  305. '0': CPU is scalar
  306. '1': CPU is superscalar
  307. (modify cpu/or32/execute.c to tune superscalar model)
  308. hazards = 0/1
  309. '0': don't track data hazards in superscalar CPU
  310. '1': track data hazards in superscalar CPU
  311. If tracked, data hazards can be displayed using the
  312. simulator's 'r' command.
  313. dependstats = 0/1
  314. '0': don't calculate inter-instruction dependencies.
  315. '1': calculate inter-instruction dependencies.
  316. If calculated, inter-instruction dependencies can be
  317. displayed using the simulator's 'stat' command.
  318. sbuf_len = <value>
  319. length of store buffer (<= 256), 0 = disabled
  320. */
  321. section cpu
  322. ver = 0x12
  323. cfg = 0x00
  324. rev = 0x01
  325. sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */
  326. /* upr = */
  327. superscalar = 0
  328. hazards = 0
  329. dependstats = 0
  330. sbuf_len = 0
  331. end
  332. /* PM SECTION
  333. This section specifies Power Management parameters
  334. enabled = 0/1
  335. '0': disable power management
  336. '1': enable power management
  337. */
  338. section pm
  339. enabled = 0
  340. end
  341. /* BPB SECTION
  342. This section specifies how branch prediction should behave.
  343. enabled = 0/1
  344. '0': disable branch prediction
  345. '1': enable branch prediction
  346. btic = 0/1
  347. '0': disable branch target instruction cache model
  348. '1': enable branch target instruction cache model
  349. sbp_bf_fwd = 0/1
  350. Static branch prediction for 'l.bf'
  351. '0': don't use forward prediction
  352. '1': use forward prediction
  353. sbp_bnf_fwd = 0/1
  354. Static branch prediction for 'l.bnf'
  355. '0': don't use forward prediction
  356. '1': use forward prediction
  357. hitdelay = <value>
  358. number of cycles bpb hit costs
  359. missdelay = <value>
  360. number of cycles bpb miss costs
  361. */
  362. section bpb
  363. enabled = 0
  364. btic = 0
  365. sbp_bf_fwd = 0
  366. sbp_bnf_fwd = 0
  367. hitdelay = 0
  368. missdelay = 0
  369. end
  370. /* DEBUG SECTION
  371. This sections specifies how the debug unit should behave.
  372. enabled = 0/1
  373. '0': disable debug unit
  374. '1': enable debug unit
  375. gdb_enabled = 0/1
  376. '0': don't start gdb server
  377. '1': start gdb server at port 'server_port'
  378. server_port = <value>
  379. TCP/IP port to start gdb server on
  380. valid only if gdb_enabled is set
  381. vapi_id = <hex_value>
  382. Used to create "fake" vapi log file containing the JTAG proxy messages.
  383. */
  384. section debug
  385. enabled = 0
  386. /* gdb_enabled = 0 */
  387. /* server_port = 9999*/
  388. rsp_enabled = 1
  389. rsp_port = 50001
  390. end
  391. /* MC SECTION
  392. This section configures the memory controller
  393. enabled = 0/1
  394. '0': disable memory controller
  395. '1': enable memory controller
  396. baseaddr = <hex_value>
  397. address of first MC register
  398. POC = <hex_value>
  399. Power On Configuration register
  400. index = <value>
  401. Index of this memory controller amongst all the memory controllers
  402. */
  403. section mc
  404. enabled = 0
  405. baseaddr = 0x93000000
  406. POC = 0x00000008 /* Power on configuration register */
  407. index = 0
  408. end
  409. /* UART SECTION
  410. This section configures the UARTs
  411. enabled = <0|1>
  412. Enable/disable the peripheral. By default if it is enabled.
  413. baseaddr = <hex_value>
  414. address of first UART register for this device
  415. channel = <channeltype>:<args>
  416. The channel parameter indicates the source of received UART characters
  417. and the sink for transmitted UART characters.
  418. The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
  419. (without quotes).
  420. A) To send/receive characters from a pair of files, use a file
  421. channel:
  422. channel=file:<rxfile>,<txfile>
  423. B) To create an interactive terminal window, use an xterm channel:
  424. channel=xterm:[<xterm_arg>]*
  425. C) To create a bidirectional tcp socket which one could, for example,
  426. access via telnet, use a tcp channel:
  427. channel=tcp:<port number>
  428. D) To cause the UART to read/write from existing numeric file
  429. descriptors, use an fd channel:
  430. channel=fd:<rx file descriptor num>,<tx file descriptor num>
  431. E) To connect the UART to a physical serial port, create a tty
  432. channel:
  433. channel=tty:device=/dev/ttyS0,baud=9600
  434. irq = <value>
  435. irq number for this device
  436. 16550 = 0/1
  437. '0': this device is a UART16450
  438. '1': this device is a UART16550
  439. jitter = <value>
  440. in msecs... time to block, -1 to disable it
  441. vapi_id = <hex_value>
  442. VAPI id of this instance
  443. */
  444. section uart
  445. enabled = 1
  446. baseaddr = 0x90000000
  447. irq = 2
  448. /* channel = "file:uart0.rx,uart0.tx" */
  449. /* channel = "tcp:10084" */
  450. channel = "xterm:"
  451. jitter = -1 /* async behaviour */
  452. 16550 = 1
  453. end
  454. /* DMA SECTION
  455. This section configures the DMAs
  456. enabled = <0|1>
  457. Enable/disable the peripheral. By default if it is enabled.
  458. baseaddr = <hex_value>
  459. address of first DMA register for this device
  460. irq = <value>
  461. irq number for this device
  462. vapi_id = <hex_value>
  463. VAPI id of this instance
  464. */
  465. section dma
  466. enabled = 1
  467. baseaddr = 0x9a000000
  468. irq = 11
  469. end
  470. /* ETHERNET SECTION
  471. This section configures the ETHERNETs
  472. enabled = <0|1>
  473. Enable/disable the peripheral. By default if it is enabled.
  474. baseaddr = <hex_value>
  475. address of first ethernet register for this device
  476. dma = <value>
  477. which controller is this ethernet "connected" to
  478. irq = <value>
  479. ethernet mac IRQ level
  480. rtx_type = <value>
  481. use 0 - file interface, 1 - socket interface
  482. rx_channel = <value>
  483. DMA channel used for RX
  484. tx_channel = <value>
  485. DMA channel used for TX
  486. rxfile = "<filename>"
  487. filename, where to read data from
  488. txfile = "<filename>"
  489. filename, where to write data to
  490. sockif = "<ifacename>"
  491. interface name of ethernet socket
  492. vapi_id = <hex_value>
  493. VAPI id of this instance
  494. */
  495. section ethernet
  496. enabled = 1
  497. baseaddr = 0x92000000
  498. /* dma = 0 */
  499. irq = 4
  500. rtx_type = "tap"
  501. tap_dev = "tap0"
  502. /* tx_channel = 0 */
  503. /* rx_channel = 1 */
  504. rxfile = "eth0.rx"
  505. txfile = "eth0.tx"
  506. sockif = "eth0"
  507. end
  508. /* GPIO SECTION
  509. This section configures the GPIOs
  510. enabled = <0|1>
  511. Enable/disable the peripheral. By default if it is enabled.
  512. baseaddr = <hex_value>
  513. address of first GPIO register for this device
  514. irq = <value>
  515. irq number for this device
  516. base_vapi_id = <hex_value>
  517. first VAPI id of this instance
  518. GPIO uses 8 consecutive VAPI IDs
  519. */
  520. section gpio
  521. enabled = 0
  522. baseaddr = 0x91000000
  523. irq = 3
  524. base_vapi_id = 0x0200
  525. end
  526. /* VGA SECTION
  527. This section configures the VGA/LCD controller
  528. enabled = <0|1>
  529. Enable/disable the peripheral. By default if it is enabled.
  530. baseaddr = <hex_value>
  531. address of first VGA register
  532. irq = <value>
  533. irq number for this device
  534. refresh_rate = <value>
  535. number of cycles between screen dumps
  536. filename = "<filename>"
  537. template name for generated names (e.g. "primary" produces "primary0023.bmp")
  538. */
  539. section vga
  540. enabled = 0
  541. baseaddr = 0x97100000
  542. irq = 8
  543. refresh_rate = 100000
  544. filename = "primary"
  545. end
  546. /* TICK TIMER SECTION
  547. This section configures tick timer
  548. enabled = 0/1
  549. whether tick timer is enabled
  550. */
  551. section pic
  552. enabled = 1
  553. edge_trigger = 1
  554. end
  555. /* FB SECTION
  556. This section configures the frame buffer
  557. enabled = <0|1>
  558. Enable/disable the peripheral. By default if it is enabled.
  559. baseaddr = <hex_value>
  560. base address of frame buffer
  561. paladdr = <hex_value>
  562. base address of first palette entry
  563. refresh_rate = <value>
  564. number of cycles between screen dumps
  565. filename = "<filename>"
  566. template name for generated names (e.g. "primary" produces "primary0023.bmp")
  567. */
  568. section fb
  569. enabled = 0
  570. baseaddr = 0x97000000
  571. refresh_rate = 1000000
  572. filename = "primary"
  573. end
  574. /* KBD SECTION
  575. This section configures the PS/2 compatible keyboard
  576. baseaddr = <hex_value>
  577. base address of the keyboard device
  578. rxfile = "<filename>"
  579. filename, where to read data from
  580. */
  581. section kbd
  582. enabled = 0
  583. irq = 5
  584. baseaddr = 0x94000000
  585. rxfile = "kbd.rx"
  586. end
  587. /* ATA SECTION
  588. This section configures the ATA/ATAPI host controller
  589. baseaddr = <hex_value>
  590. address of first ATA register
  591. enabled = <0|1>
  592. Enable/disable the peripheral. By default if it is enabled.
  593. irq = <value>
  594. irq number for this device
  595. debug = <value>
  596. debug level for ata models.
  597. 0: no debug messages
  598. 1: verbose messages
  599. 3: normal messages (more messages than verbose)
  600. 5: debug messages (normal debug messages)
  601. 7: flow control messages (debug statemachine flows)
  602. 9: low priority message (display everything the code does)
  603. dev_type0/1 = <value>
  604. ata device 0 type
  605. 0: NO_CONNeCT: none (not connected)
  606. 1: FILE : simulated harddisk
  607. 2: LOCAL : local system harddisk
  608. dev_file0/1 = "<filename>"
  609. filename for simulated ATA device
  610. valid only if dev_type0 == 1
  611. dev_size0/1 = <value>
  612. size of simulated hard-disk (in MBytes)
  613. valid only if dev_type0 == 1
  614. dev_packet0/1 = <value>
  615. 0: simulated ATA device does NOT implement PACKET command feature set
  616. 1: simulated ATA device does implement PACKET command feature set
  617. FIXME: irq number
  618. */
  619. section ata
  620. enabled = 0
  621. baseaddr = 0x9e000000
  622. irq = 15
  623. end