vovpn-gw.c 15 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
  4. *
  5. * Support for the Elmeg VoVPN Gateway Module
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <ioports.h>
  11. #include <mpc8260.h>
  12. #include <asm/m8260_pci.h>
  13. #include <miiphy.h>
  14. #include <linux/compiler.h>
  15. #include "m88e6060.h"
  16. /*
  17. * I/O Port configuration table
  18. *
  19. * if conf is 1, then that port pin will be configured at boot time
  20. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  21. */
  22. const iop_conf_t iop_conf_tab[4][32] = {
  23. /* Port A configuration */
  24. { /* conf ppar psor pdir podr pdat */
  25. /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */
  26. /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */
  27. /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */
  28. /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */
  29. /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */
  30. /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */
  31. /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  32. /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  33. /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  34. /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  35. /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  36. /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */
  37. /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */
  38. /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */
  39. /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */
  40. /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */
  41. /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */
  42. /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */
  43. /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */
  44. /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */
  45. /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */
  46. /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */
  47. /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
  48. /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
  49. /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  50. /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  51. /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  52. /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  53. /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  54. /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  55. /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  56. /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */
  57. },
  58. /* Port B configuration */
  59. { /* conf ppar psor pdir podr pdat */
  60. /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */
  61. /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */
  62. /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */
  63. /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */
  64. /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */
  65. /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */
  66. /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */
  67. /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */
  68. /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */
  69. /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */
  70. /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */
  71. /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */
  72. /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */
  73. /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */
  74. /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  75. /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  76. /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  77. /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  78. /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  79. /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  80. /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  81. /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  82. /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  83. /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  84. /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  85. /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  86. /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  87. /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  88. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  89. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  90. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  91. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
  92. },
  93. /* Port C */
  94. { /* conf ppar psor pdir podr pdat */
  95. /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  96. /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  97. /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */
  98. /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */
  99. /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */
  100. /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */
  101. /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */
  102. /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */
  103. /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */
  104. /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */
  105. /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */
  106. /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */
  107. /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */
  108. /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */
  109. /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */
  110. /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */
  111. /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */
  112. /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */
  113. /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */
  114. /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */
  115. /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */
  116. /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */
  117. /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */
  118. /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */
  119. /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */
  120. /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */
  121. /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  122. /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  123. /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  124. /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  125. /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */
  126. /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */
  127. },
  128. /* Port D */
  129. { /* conf ppar psor pdir podr pdat */
  130. /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */
  131. /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */
  132. /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */
  133. /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  134. /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  135. /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  136. /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */
  137. /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */
  138. /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */
  139. /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */
  140. /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */
  141. /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
  142. /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */
  143. /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */
  144. /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */
  145. /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */
  146. /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */
  147. /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */
  148. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  149. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  150. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  151. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  152. /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  153. /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  154. /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */
  155. /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  156. /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  157. /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  158. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  159. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  160. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  161. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
  162. }
  163. };
  164. void reset_phy (void)
  165. {
  166. volatile ioport_t *iop;
  167. #if defined(CONFIG_CMD_NET)
  168. int i;
  169. unsigned short val;
  170. #endif
  171. iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
  172. /* Reset the PHY */
  173. iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */
  174. #if defined(CONFIG_CMD_NET)
  175. udelay(20000);
  176. iop->pdat |= 0x00080000;
  177. for (i=0; i<100; i++) {
  178. udelay(20000);
  179. if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
  180. break;
  181. }
  182. }
  183. /* initialize switch */
  184. m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
  185. #endif
  186. }
  187. static unsigned long UPMATable[] = {
  188. 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
  189. 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
  190. 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
  191. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
  192. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
  193. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
  194. 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
  195. 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
  196. 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
  197. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
  198. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
  199. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
  200. 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
  201. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
  202. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
  203. 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
  204. };
  205. int board_early_init_f (void)
  206. {
  207. volatile immap_t *immap;
  208. volatile memctl8260_t *memctl;
  209. volatile unsigned char *dummy;
  210. int i;
  211. immap = (immap_t *) CONFIG_SYS_IMMR;
  212. memctl = &immap->im_memctl;
  213. #if 0
  214. /* CS2-5 - DSP via UPMA */
  215. dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
  216. memctl->memc_mar = 0;
  217. memctl->memc_mamr = MxMR_OP_WARR;
  218. for (i = 0; i < 64; i++) {
  219. memctl->memc_mdr = UPMATable[i];
  220. *dummy = 0;
  221. }
  222. memctl->memc_mamr = 0x00044440;
  223. #else
  224. /* CS7 - DPRAM via UPMA */
  225. dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
  226. memctl->memc_mar = 0;
  227. memctl->memc_mamr = MxMR_OP_WARR;
  228. for (i = 0; i < 64; i++) {
  229. memctl->memc_mdr = UPMATable[i];
  230. *dummy = 0;
  231. }
  232. memctl->memc_mamr = 0x00044440;
  233. #endif
  234. return 0;
  235. }
  236. int misc_init_r (void)
  237. {
  238. volatile ioport_t *iop;
  239. __maybe_unused unsigned char temp;
  240. #if 0
  241. /* DUMP UPMA RAM */
  242. volatile immap_t *immap;
  243. volatile memctl8260_t *memctl;
  244. volatile unsigned char *dummy;
  245. unsigned char c;
  246. int i;
  247. immap = (immap_t *) CONFIG_SYS_IMMR;
  248. memctl = &immap->im_memctl;
  249. dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
  250. memctl->memc_mar = 0;
  251. memctl->memc_mamr = MxMR_OP_RARR;
  252. for (i = 0; i < 64; i++) {
  253. c = *dummy;
  254. printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
  255. memctl->memc_mamr,
  256. memctl->memc_mar,
  257. memctl->memc_mdr );
  258. }
  259. memctl->memc_mamr = 0x00044440;
  260. #endif
  261. /* enable buffers (DSP, DPRAM) */
  262. iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
  263. iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */
  264. /* destroy DPRAM magic */
  265. *(volatile unsigned char *)0xf0500000 = 0x00;
  266. /* clear any pending DPRAM irq */
  267. temp = *(volatile unsigned char *)0xf05003ff;
  268. /* write module-id into DPRAM */
  269. *(volatile unsigned char *)0xf0500201 = 0x50;
  270. return 0;
  271. }
  272. #if defined(CONFIG_HAVE_OWN_RESET)
  273. int
  274. do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  275. {
  276. volatile ioport_t *iop;
  277. iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
  278. iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
  279. return 1;
  280. }
  281. #endif /* CONFIG_HAVE_OWN_RESET */
  282. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
  283. phys_size_t initdram (int board_type)
  284. {
  285. #ifndef CONFIG_SYS_RAMBOOT
  286. volatile immap_t *immap;
  287. volatile memctl8260_t *memctl;
  288. volatile uchar *ramaddr;
  289. int i;
  290. uchar c;
  291. immap = (immap_t *) CONFIG_SYS_IMMR;
  292. memctl = &immap->im_memctl;
  293. ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
  294. c = 0xff;
  295. immap->im_siu_conf.sc_ppc_acr = 0x02;
  296. immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
  297. immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
  298. immap->im_siu_conf.sc_tescr1 = 0x00000000;
  299. immap->im_siu_conf.sc_tescr2 = 0x00000000;
  300. memctl->memc_mptpr = CONFIG_SYS_MPTPR;
  301. memctl->memc_psrt = CONFIG_SYS_PSRT;
  302. memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
  303. memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM;
  304. /* Precharge all banks */
  305. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
  306. *ramaddr = c;
  307. /* CBR refresh */
  308. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
  309. for (i = 0; i < 8; i++)
  310. *ramaddr = c;
  311. /* Mode Register write */
  312. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
  313. *ramaddr = c;
  314. /* Refresh enable */
  315. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
  316. *ramaddr = c;
  317. #endif /* CONFIG_SYS_RAMBOOT */
  318. return (CONFIG_SYS_SDRAM_SIZE);
  319. }
  320. int checkboard (void)
  321. {
  322. #ifdef CONFIG_CLKIN_66MHz
  323. puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
  324. #else
  325. puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
  326. #endif
  327. return 0;
  328. }