mpc8360emds.c 12 KB

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  1. /*
  2. * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
  3. * Dave Liu <daveliu@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <ioports.h>
  9. #include <mpc83xx.h>
  10. #include <i2c.h>
  11. #include <miiphy.h>
  12. #include <phy.h>
  13. #if defined(CONFIG_PCI)
  14. #include <pci.h>
  15. #endif
  16. #include <spd_sdram.h>
  17. #include <asm/mmu.h>
  18. #include <asm/io.h>
  19. #include <asm/fsl_enet.h>
  20. #include <asm/mmu.h>
  21. #if defined(CONFIG_OF_LIBFDT)
  22. #include <libfdt.h>
  23. #endif
  24. #include <hwconfig.h>
  25. #include <fdt_support.h>
  26. #if defined(CONFIG_PQ_MDS_PIB)
  27. #include "../common/pq-mds-pib.h"
  28. #endif
  29. #include "../../../drivers/qe/uec.h"
  30. const qe_iop_conf_t qe_iop_conf_tab[] = {
  31. /* GETH1 */
  32. {0, 3, 1, 0, 1}, /* TxD0 */
  33. {0, 4, 1, 0, 1}, /* TxD1 */
  34. {0, 5, 1, 0, 1}, /* TxD2 */
  35. {0, 6, 1, 0, 1}, /* TxD3 */
  36. {1, 6, 1, 0, 3}, /* TxD4 */
  37. {1, 7, 1, 0, 1}, /* TxD5 */
  38. {1, 9, 1, 0, 2}, /* TxD6 */
  39. {1, 10, 1, 0, 2}, /* TxD7 */
  40. {0, 9, 2, 0, 1}, /* RxD0 */
  41. {0, 10, 2, 0, 1}, /* RxD1 */
  42. {0, 11, 2, 0, 1}, /* RxD2 */
  43. {0, 12, 2, 0, 1}, /* RxD3 */
  44. {0, 13, 2, 0, 1}, /* RxD4 */
  45. {1, 1, 2, 0, 2}, /* RxD5 */
  46. {1, 0, 2, 0, 2}, /* RxD6 */
  47. {1, 4, 2, 0, 2}, /* RxD7 */
  48. {0, 7, 1, 0, 1}, /* TX_EN */
  49. {0, 8, 1, 0, 1}, /* TX_ER */
  50. {0, 15, 2, 0, 1}, /* RX_DV */
  51. {0, 16, 2, 0, 1}, /* RX_ER */
  52. {0, 0, 2, 0, 1}, /* RX_CLK */
  53. {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
  54. {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
  55. /* GETH2 */
  56. {0, 17, 1, 0, 1}, /* TxD0 */
  57. {0, 18, 1, 0, 1}, /* TxD1 */
  58. {0, 19, 1, 0, 1}, /* TxD2 */
  59. {0, 20, 1, 0, 1}, /* TxD3 */
  60. {1, 2, 1, 0, 1}, /* TxD4 */
  61. {1, 3, 1, 0, 2}, /* TxD5 */
  62. {1, 5, 1, 0, 3}, /* TxD6 */
  63. {1, 8, 1, 0, 3}, /* TxD7 */
  64. {0, 23, 2, 0, 1}, /* RxD0 */
  65. {0, 24, 2, 0, 1}, /* RxD1 */
  66. {0, 25, 2, 0, 1}, /* RxD2 */
  67. {0, 26, 2, 0, 1}, /* RxD3 */
  68. {0, 27, 2, 0, 1}, /* RxD4 */
  69. {1, 12, 2, 0, 2}, /* RxD5 */
  70. {1, 13, 2, 0, 3}, /* RxD6 */
  71. {1, 11, 2, 0, 2}, /* RxD7 */
  72. {0, 21, 1, 0, 1}, /* TX_EN */
  73. {0, 22, 1, 0, 1}, /* TX_ER */
  74. {0, 29, 2, 0, 1}, /* RX_DV */
  75. {0, 30, 2, 0, 1}, /* RX_ER */
  76. {0, 31, 2, 0, 1}, /* RX_CLK */
  77. {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
  78. {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
  79. {0, 1, 3, 0, 2}, /* MDIO */
  80. {0, 2, 1, 0, 1}, /* MDC */
  81. {5, 0, 1, 0, 2}, /* UART2_SOUT */
  82. {5, 1, 2, 0, 3}, /* UART2_CTS */
  83. {5, 2, 1, 0, 1}, /* UART2_RTS */
  84. {5, 3, 2, 0, 2}, /* UART2_SIN */
  85. {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  86. };
  87. /* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
  88. static int board_handle_erratum2(void)
  89. {
  90. const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  91. return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
  92. REVID_MINOR(immr->sysconf.spridr) == 1;
  93. }
  94. int board_early_init_f(void)
  95. {
  96. const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  97. u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
  98. /* Enable flash write */
  99. bcsr[0xa] &= ~0x04;
  100. /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
  101. if (REVID_MAJOR(immr->sysconf.spridr) == 2)
  102. bcsr[0xe] = 0x30;
  103. /* Enable second UART */
  104. bcsr[0x9] &= ~0x01;
  105. if (board_handle_erratum2()) {
  106. void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
  107. /*
  108. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  109. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  110. */
  111. setbits_be32(immap, 0x0c003000);
  112. /*
  113. * IMMR + 0x14AC[20:27] = 10101010
  114. * (data delay for both UCC's)
  115. */
  116. clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
  117. }
  118. return 0;
  119. }
  120. int board_early_init_r(void)
  121. {
  122. gd_t *gd;
  123. #ifdef CONFIG_PQ_MDS_PIB
  124. pib_init();
  125. #endif
  126. /*
  127. * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
  128. * So re-setup PCI MEM space used BAT5 after relocated to DDR
  129. */
  130. gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  131. if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
  132. write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
  133. write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
  134. }
  135. return 0;
  136. }
  137. #ifdef CONFIG_UEC_ETH
  138. static uec_info_t uec_info[] = {
  139. #ifdef CONFIG_UEC_ETH1
  140. STD_UEC_INFO(1),
  141. #endif
  142. #ifdef CONFIG_UEC_ETH2
  143. STD_UEC_INFO(2),
  144. #endif
  145. };
  146. int board_eth_init(bd_t *bd)
  147. {
  148. if (board_handle_erratum2()) {
  149. int i;
  150. for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
  151. uec_info[i].enet_interface_type =
  152. PHY_INTERFACE_MODE_RGMII_RXID;
  153. uec_info[i].speed = SPEED_1000;
  154. }
  155. }
  156. return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
  157. }
  158. #endif /* CONFIG_UEC_ETH */
  159. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  160. extern void ddr_enable_ecc(unsigned int dram_size);
  161. #endif
  162. int fixed_sdram(void);
  163. static int sdram_init(unsigned int base);
  164. phys_size_t initdram(int board_type)
  165. {
  166. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  167. u32 msize = 0;
  168. u32 lbc_sdram_size;
  169. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  170. return -1;
  171. /* DDR SDRAM - Main SODIMM */
  172. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
  173. #if defined(CONFIG_SPD_EEPROM)
  174. msize = spd_sdram();
  175. #else
  176. msize = fixed_sdram();
  177. #endif
  178. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  179. /*
  180. * Initialize DDR ECC byte
  181. */
  182. ddr_enable_ecc(msize * 1024 * 1024);
  183. #endif
  184. /*
  185. * Initialize SDRAM if it is on local bus.
  186. */
  187. lbc_sdram_size = sdram_init(msize * 1024 * 1024);
  188. if (!msize)
  189. msize = lbc_sdram_size;
  190. /* return total bus SDRAM size(bytes) -- DDR */
  191. return (msize * 1024 * 1024);
  192. }
  193. #if !defined(CONFIG_SPD_EEPROM)
  194. /*************************************************************************
  195. * fixed sdram init -- doesn't use serial presence detect.
  196. ************************************************************************/
  197. int fixed_sdram(void)
  198. {
  199. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  200. u32 msize = CONFIG_SYS_DDR_SIZE;
  201. u32 ddr_size = msize << 20;
  202. u32 ddr_size_log2 = __ilog2(ddr_size);
  203. u32 half_ddr_size = ddr_size >> 1;
  204. im->sysconf.ddrlaw[0].bar =
  205. CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
  206. im->sysconf.ddrlaw[0].ar =
  207. LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  208. #if (CONFIG_SYS_DDR_SIZE != 256)
  209. #warning Currenly any ddr size other than 256 is not supported
  210. #endif
  211. #ifdef CONFIG_DDR_II
  212. im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
  213. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  214. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  215. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  216. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  217. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  218. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  219. im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  220. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  221. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  222. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  223. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  224. #else
  225. #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
  226. #warning Chip select bounds is only configurable in 16MB increments
  227. #endif
  228. im->ddr.csbnds[0].csbnds =
  229. ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  230. (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
  231. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  232. im->ddr.csbnds[1].csbnds =
  233. (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
  234. CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  235. (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
  236. CSBNDS_EA_SHIFT) & CSBNDS_EA);
  237. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  238. im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
  239. im->ddr.cs_config[2] = 0;
  240. im->ddr.cs_config[3] = 0;
  241. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  242. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  243. im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
  244. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  245. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  246. #endif
  247. udelay(200);
  248. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  249. return msize;
  250. }
  251. #endif /*!CONFIG_SYS_SPD_EEPROM */
  252. int checkboard(void)
  253. {
  254. puts("Board: Freescale MPC8360EMDS\n");
  255. return 0;
  256. }
  257. /*
  258. * if MPC8360EMDS is soldered with SDRAM
  259. */
  260. #ifdef CONFIG_SYS_LB_SDRAM
  261. /*
  262. * Initialize SDRAM memory on the Local Bus.
  263. */
  264. static int sdram_init(unsigned int base)
  265. {
  266. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  267. fsl_lbc_t *lbc = LBC_BASE_ADDR;
  268. const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
  269. int rem = base % sdram_size;
  270. uint *sdram_addr;
  271. /* window base address should be aligned to the window size */
  272. if (rem)
  273. base = base - rem + sdram_size;
  274. /*
  275. * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
  276. * After relocated to DDR, reuse BAT5 for PCI MEM space
  277. */
  278. if (base > CONFIG_MAX_MEM_MAPPED) {
  279. unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
  280. unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
  281. /* Setup the BAT6 for SDRAM */
  282. write_bat(DBAT6, batu, batl);
  283. write_bat(IBAT6, batu, batl);
  284. }
  285. sdram_addr = (uint *)base;
  286. /*
  287. * Setup SDRAM Base and Option Registers
  288. */
  289. set_lbc_br(2, base | CONFIG_SYS_BR2);
  290. set_lbc_or(2, CONFIG_SYS_OR2);
  291. immap->sysconf.lblaw[2].bar = base;
  292. immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
  293. /*setup mtrpt, lsrt and lbcr for LB bus */
  294. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  295. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  296. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  297. asm("sync");
  298. /*
  299. * Configure the SDRAM controller Machine Mode Register.
  300. */
  301. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
  302. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
  303. asm("sync");
  304. *sdram_addr = 0xff;
  305. udelay(100);
  306. /*
  307. * We need do 8 times auto refresh operation.
  308. */
  309. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
  310. asm("sync");
  311. *sdram_addr = 0xff; /* 1 times */
  312. udelay(100);
  313. *sdram_addr = 0xff; /* 2 times */
  314. udelay(100);
  315. *sdram_addr = 0xff; /* 3 times */
  316. udelay(100);
  317. *sdram_addr = 0xff; /* 4 times */
  318. udelay(100);
  319. *sdram_addr = 0xff; /* 5 times */
  320. udelay(100);
  321. *sdram_addr = 0xff; /* 6 times */
  322. udelay(100);
  323. *sdram_addr = 0xff; /* 7 times */
  324. udelay(100);
  325. *sdram_addr = 0xff; /* 8 times */
  326. udelay(100);
  327. /* Mode register write operation */
  328. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
  329. asm("sync");
  330. *(sdram_addr + 0xcc) = 0xff;
  331. udelay(100);
  332. /* Normal operation */
  333. lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
  334. asm("sync");
  335. *sdram_addr = 0xff;
  336. udelay(100);
  337. /*
  338. * In non-aligned case we don't [normally] use that memory because
  339. * there is a hole.
  340. */
  341. if (rem)
  342. return 0;
  343. return CONFIG_SYS_LBC_SDRAM_SIZE;
  344. }
  345. #else
  346. static int sdram_init(unsigned int base) { return 0; }
  347. #endif
  348. #if defined(CONFIG_OF_BOARD_SETUP)
  349. static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
  350. {
  351. if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
  352. return;
  353. do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
  354. "peripheral", sizeof("peripheral"), 1);
  355. }
  356. void ft_board_setup(void *blob, bd_t *bd)
  357. {
  358. ft_cpu_setup(blob, bd);
  359. #ifdef CONFIG_PCI
  360. ft_pci_setup(blob, bd);
  361. #endif
  362. ft_board_fixup_qe_usb(blob, bd);
  363. /*
  364. * mpc8360ea pb mds errata 2: RGMII timing
  365. * if on mpc8360ea rev. 2.1,
  366. * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
  367. */
  368. if (board_handle_erratum2()) {
  369. int nodeoffset;
  370. const char *prop;
  371. int path;
  372. nodeoffset = fdt_path_offset(blob, "/aliases");
  373. if (nodeoffset >= 0) {
  374. #if defined(CONFIG_HAS_ETH0)
  375. /* fixup UCC 1 if using rgmii-id mode */
  376. prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
  377. if (prop) {
  378. path = fdt_path_offset(blob, prop);
  379. prop = fdt_getprop(blob, path,
  380. "phy-connection-type", 0);
  381. if (prop && (strcmp(prop, "rgmii-id") == 0))
  382. fdt_fixup_phy_connection(blob, path,
  383. PHY_INTERFACE_MODE_RGMII_RXID);
  384. }
  385. #endif
  386. #if defined(CONFIG_HAS_ETH1)
  387. /* fixup UCC 2 if using rgmii-id mode */
  388. prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
  389. if (prop) {
  390. path = fdt_path_offset(blob, prop);
  391. prop = fdt_getprop(blob, path,
  392. "phy-connection-type", 0);
  393. if (prop && (strcmp(prop, "rgmii-id") == 0))
  394. fdt_fixup_phy_connection(blob, path,
  395. PHY_INTERFACE_MODE_RGMII_RXID);
  396. }
  397. #endif
  398. }
  399. }
  400. }
  401. #endif