README 5.1 KB

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  1. Overview
  2. --------
  3. The BSC9132 is a highly integrated device that targets the evolving
  4. Microcell, Picocell, and Enterprise-Femto base station market subsegments.
  5. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
  6. core technologies with MAPLE-B2P baseband acceleration processing elements
  7. to address the need for a high performance, low cost, integrated solution
  8. that handles all required processing layers without the need for an
  9. external device except for an RF transceiver or, in a Micro base station
  10. configuration, a host device that handles the L3/L4 and handover between
  11. sectors.
  12. The BSC9132 SoC includes the following function and features:
  13. - Power Architecture subsystem including two e500 processors with
  14. 512-Kbyte shared L2 cache
  15. - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
  16. cache
  17. - 32 Kbyte of shared M3 memory
  18. - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
  19. Processing (MAPLE-B2P)
  20. - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
  21. ECC), up to 1333 MHz data rate
  22. - Dedicated security engine featuring trusted boot
  23. - Two DMA controllers
  24. - OCNDMA with four bidirectional channels
  25. - SysDMA with sixteen bidirectional channels
  26. - Interfaces
  27. - Four-lane SerDes PHY
  28. - PCI Express controller complies with the PEX Specification-Rev 2.0
  29. - Two Common Public Radio Interface (CPRI) controller lanes
  30. - High-speed USB 2.0 host and device controller with ULPI interface
  31. - Enhanced secure digital (SD/MMC) host controller (eSDHC)
  32. - Antenna interface controller (AIC), supporting four industry
  33. standard JESD207/four custom ADI RF interfaces
  34. - ADI lanes support both full duplex FDD support & half duplex TDD
  35. - Universal Subscriber Identity Module (USIM) interface that
  36. facilitates communication to SIM cards or Eurochip pre-paid phone
  37. cards
  38. - Two DUART, two eSPI, and two I2C controllers
  39. - Integrated Flash memory controller (IFC)
  40. - GPIO
  41. - Sixteen 32-bit timers
  42. The SC3850 core subsystem consists of the following:
  43. - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
  44. - 32 KB, 8-way, level 1 data cache (L1 DCache)
  45. - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
  46. - Memory management unit (MMU)
  47. - Global interrupt controller ( GIC)
  48. - Debug and profiling unit (DPU)
  49. - Two 32-bit quad timers
  50. BSC9132QDS board Overview
  51. -------------------------
  52. 2Gbyte DDR3 (on board DDR), Dual Ranki
  53. 32Mbyte 16bit NOR flash
  54. 128Mbyte 2K page size NAND Flash
  55. 256 Kbit M24256 I2C EEPROM
  56. 128 Mbit SPI Flash memory
  57. SD slot
  58. USB-ULPI
  59. eTSEC1: Connected to SGMII PHY
  60. eTSEC2: Connected to SGMII PHY
  61. PCIe
  62. CPRI
  63. SerDes
  64. I2C RTC
  65. DUART interface: supports one UARTs up to 115200 bps for console display
  66. Frequency Combinations Supported
  67. --------------------------------
  68. Core MHz/CCB MHz/DDR(MT/s)
  69. 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
  70. (SYSCLK = 100MHz, DDRCLK = 100MHz)
  71. 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
  72. (SYSCLK = 100MHz, DDRCLK = 133MHz)
  73. Boot Methods Supported
  74. -----------------------
  75. 1. NOR Flash
  76. 2. NAND Flash
  77. 3. SD Card
  78. 4. SPI flash
  79. Default Boot Method
  80. --------------------
  81. NOR boot
  82. Building U-boot
  83. --------------
  84. To build the u-boot for BSC9132QDS:
  85. 1. NOR Flash
  86. make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
  87. make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
  88. 2. NAND Flash : It is currently not supported
  89. 3. SPI Flash
  90. make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
  91. make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
  92. 4. SD Card
  93. make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
  94. make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
  95. Memory map
  96. -----------
  97. 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
  98. 0x8000_0000 0x8FFF_FFFF NOR Flash 256M
  99. 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
  100. 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
  101. 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
  102. 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
  103. 0xC000_0000 0xC000_7FFF M3 Memory 32K
  104. 0xC001_0000 0xC001_FFFF PCI Express I/O 64K
  105. 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
  106. 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
  107. 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
  108. 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
  109. 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
  110. 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
  111. 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
  112. 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
  113. Flashing Images
  114. ---------------
  115. To place a new u-boot image in the NAND flash and then boot
  116. with that new image temporarily, use this:
  117. tftp 1000000 u-boot-nand.bin
  118. nand erase 0 100000
  119. nand write 1000000 0 100000
  120. reset
  121. Using the Device Tree Source File
  122. ---------------------------------
  123. To create the DTB (Device Tree Binary) image file,
  124. use a command similar to this:
  125. dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
  126. Likely, that .dts file will come from here;
  127. linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
  128. Booting Linux
  129. -------------
  130. Place a linux uImage in the TFTP disk area.
  131. tftp 1000000 uImage
  132. tftp 2000000 rootfs.ext2.gz.uboot
  133. tftp c00000 bsc9132qds.dtb
  134. bootm 1000000 2000000 c00000