traps.c 12 KB

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  1. /*
  2. * U-boot - traps.c Routines related to interrupts and exceptions
  3. *
  4. * Copyright (c) 2005-2008 Analog Devices Inc.
  5. *
  6. * This file is based on
  7. * No original Copyright holder listed,
  8. * Probabily original (C) Roman Zippel (assigned DJD, 1999)
  9. *
  10. * Copyright 2003 Metrowerks - for Blackfin
  11. * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
  12. * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
  13. *
  14. * (C) Copyright 2000-2004
  15. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  16. *
  17. * Licensed under the GPL-2 or later.
  18. */
  19. #include <common.h>
  20. #include <kgdb.h>
  21. #include <linux/types.h>
  22. #include <asm/traps.h>
  23. #include <asm/cplb.h>
  24. #include <asm/io.h>
  25. #include <asm/mach-common/bits/core.h>
  26. #include <asm/mach-common/bits/mpu.h>
  27. #include <asm/mach-common/bits/trace.h>
  28. #include <asm/deferred.h>
  29. #include "cpu.h"
  30. #ifdef CONFIG_DEBUG_DUMP
  31. # define ENABLE_DUMP 1
  32. #else
  33. # define ENABLE_DUMP 0
  34. #endif
  35. #define trace_buffer_save(x) \
  36. do { \
  37. if (!ENABLE_DUMP) \
  38. break; \
  39. (x) = bfin_read_TBUFCTL(); \
  40. bfin_write_TBUFCTL((x) & ~TBUFEN); \
  41. } while (0)
  42. #define trace_buffer_restore(x) \
  43. do { \
  44. if (!ENABLE_DUMP) \
  45. break; \
  46. bfin_write_TBUFCTL((x)); \
  47. } while (0);
  48. /* The purpose of this map is to provide a mapping of address<->cplb settings
  49. * rather than an exact map of what is actually addressable on the part. This
  50. * map covers all current Blackfin parts. If you try to access an address that
  51. * is in this map but not actually on the part, you won't get an exception and
  52. * reboot, you'll get an external hardware addressing error and reboot. Since
  53. * only the ends matter (you did something wrong and the board reset), the means
  54. * are largely irrelevant.
  55. */
  56. struct memory_map {
  57. uint32_t start, end;
  58. uint32_t data_flags, inst_flags;
  59. };
  60. const struct memory_map const bfin_memory_map[] = {
  61. { /* external memory */
  62. .start = 0x00000000,
  63. .end = 0x20000000,
  64. .data_flags = SDRAM_DGENERIC,
  65. .inst_flags = SDRAM_IGENERIC,
  66. },
  67. { /* async banks */
  68. .start = 0x20000000,
  69. .end = 0x30000000,
  70. .data_flags = SDRAM_EBIU,
  71. .inst_flags = SDRAM_INON_CHBL,
  72. },
  73. { /* everything on chip */
  74. .start = 0xE0000000,
  75. .end = 0xFFFFFFFF,
  76. .data_flags = L1_DMEMORY,
  77. .inst_flags = L1_IMEMORY,
  78. }
  79. };
  80. #ifdef CONFIG_EXCEPTION_DEFER
  81. unsigned int deferred_regs[deferred_regs_last];
  82. #endif
  83. /*
  84. * Handle all exceptions while running in EVT3 or EVT5
  85. */
  86. int trap_c(struct pt_regs *regs, uint32_t level)
  87. {
  88. uint32_t ret = 0;
  89. uint32_t trapnr = (regs->seqstat & EXCAUSE);
  90. unsigned long tflags;
  91. bool data = false;
  92. /*
  93. * Keep the trace buffer so that a miss here points people
  94. * to the right place (their code). Crashes here rarely
  95. * happen. If they do, only the Blackfin maintainer cares.
  96. */
  97. trace_buffer_save(tflags);
  98. switch (trapnr) {
  99. /* 0x26 - Data CPLB Miss */
  100. case VEC_CPLB_M:
  101. if (ANOMALY_05000261) {
  102. static uint32_t last_cplb_fault_retx;
  103. /*
  104. * Work around an anomaly: if we see a new DCPLB fault,
  105. * return without doing anything. Then,
  106. * if we get the same fault again, handle it.
  107. */
  108. if (last_cplb_fault_retx != regs->retx) {
  109. last_cplb_fault_retx = regs->retx;
  110. break;
  111. }
  112. }
  113. data = true;
  114. /* fall through */
  115. /* 0x27 - Instruction CPLB Miss */
  116. case VEC_CPLB_I_M: {
  117. volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
  118. uint32_t new_cplb_addr = 0, new_cplb_data = 0;
  119. static size_t last_evicted;
  120. size_t i;
  121. #ifdef CONFIG_EXCEPTION_DEFER
  122. /* This should never happen */
  123. if (level == 5)
  124. bfin_panic(regs);
  125. #endif
  126. new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
  127. for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
  128. /* if the exception is inside this range, lets use it */
  129. if (new_cplb_addr >= bfin_memory_map[i].start &&
  130. new_cplb_addr < bfin_memory_map[i].end)
  131. break;
  132. }
  133. if (i == ARRAY_SIZE(bfin_memory_map)) {
  134. printf("%cCPLB exception outside of memory map at 0x%p\n",
  135. (data ? 'D' : 'I'), (void *)new_cplb_addr);
  136. bfin_panic(regs);
  137. } else
  138. debug("CPLB addr %p matches map 0x%p - 0x%p\n",
  139. (void *)new_cplb_addr,
  140. (void *)bfin_memory_map[i].start,
  141. (void *)bfin_memory_map[i].end);
  142. new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
  143. if (data) {
  144. CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
  145. CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
  146. } else {
  147. CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
  148. CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
  149. }
  150. /* find the next unlocked entry and evict it */
  151. i = last_evicted & 0xF;
  152. debug("last evicted = %zu\n", i);
  153. CPLB_DATA = CPLB_DATA_BASE + i;
  154. while (*CPLB_DATA & CPLB_LOCK) {
  155. debug("skipping %zu %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
  156. i = (i + 1) & 0xF; /* wrap around */
  157. CPLB_DATA = CPLB_DATA_BASE + i;
  158. }
  159. CPLB_ADDR = CPLB_ADDR_BASE + i;
  160. debug("evicting entry %zu: 0x%p 0x%08X\n", i,
  161. (void *)*CPLB_ADDR, *CPLB_DATA);
  162. last_evicted = i + 1;
  163. /* need to turn off cplbs whenever we muck with the cplb table */
  164. #if ENDCPLB != ENICPLB
  165. # error cplb enable bit violates my sanity
  166. #endif
  167. uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
  168. bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
  169. *CPLB_ADDR = new_cplb_addr;
  170. *CPLB_DATA = new_cplb_data;
  171. bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
  172. SSYNC();
  173. /* dump current table for debugging purposes */
  174. CPLB_ADDR = CPLB_ADDR_BASE;
  175. CPLB_DATA = CPLB_DATA_BASE;
  176. for (i = 0; i < 16; ++i)
  177. debug("%2zu 0x%p 0x%08X\n", i,
  178. (void *)*CPLB_ADDR++, *CPLB_DATA++);
  179. break;
  180. }
  181. #ifdef CONFIG_CMD_KGDB
  182. /* Single step
  183. * if we are in IRQ5, just ignore, otherwise defer, and handle it in kgdb
  184. */
  185. case VEC_STEP:
  186. if (level == 3) {
  187. /* If we just returned from an interrupt, the single step
  188. * event is for the RTI instruction.
  189. */
  190. if (regs->retx == regs->pc)
  191. break;
  192. /* we just return if we are single stepping through IRQ5 */
  193. if (regs->ipend & 0x20)
  194. break;
  195. /* Otherwise, turn single stepping off & fall through,
  196. * which defers to IRQ5
  197. */
  198. regs->syscfg &= ~1;
  199. }
  200. /* fall through */
  201. #endif
  202. default:
  203. #ifdef CONFIG_CMD_KGDB
  204. if (level == 3) {
  205. /* We need to handle this at EVT5, so try again */
  206. bfin_dump(regs);
  207. ret = 1;
  208. break;
  209. }
  210. if (debugger_exception_handler && (*debugger_exception_handler)(regs))
  211. break;
  212. #endif
  213. bfin_panic(regs);
  214. }
  215. trace_buffer_restore(tflags);
  216. return ret;
  217. }
  218. #ifndef CONFIG_KALLSYMS
  219. const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
  220. {
  221. *caddr = addr;
  222. return "N/A";
  223. }
  224. #endif
  225. static void decode_address(char *buf, unsigned long address)
  226. {
  227. unsigned long sym_addr;
  228. void *paddr = (void *)address;
  229. const char *sym = symbol_lookup(address, &sym_addr);
  230. if (sym) {
  231. sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
  232. return;
  233. }
  234. if (!address)
  235. sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
  236. else if (address >= CONFIG_SYS_MONITOR_BASE &&
  237. address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  238. sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
  239. else
  240. sprintf(buf, "<0x%p> /* unknown address */", paddr);
  241. }
  242. static char *strhwerrcause(uint16_t hwerrcause)
  243. {
  244. switch (hwerrcause) {
  245. case 0x02: return "system mmr error";
  246. case 0x03: return "external memory addressing error";
  247. case 0x12: return "performance monitor overflow";
  248. case 0x18: return "raise 5 instruction";
  249. default: return "undef";
  250. }
  251. }
  252. static char *strexcause(uint16_t excause)
  253. {
  254. switch (excause) {
  255. case 0x00 ... 0xf: return "custom exception";
  256. case 0x10: return "single step";
  257. case 0x11: return "trace buffer full";
  258. case 0x21: return "undef inst";
  259. case 0x22: return "illegal inst";
  260. case 0x23: return "dcplb prot violation";
  261. case 0x24: return "misaligned data";
  262. case 0x25: return "unrecoverable event";
  263. case 0x26: return "dcplb miss";
  264. case 0x27: return "multiple dcplb hit";
  265. case 0x28: return "emulation watchpoint";
  266. case 0x2a: return "misaligned inst";
  267. case 0x2b: return "icplb prot violation";
  268. case 0x2c: return "icplb miss";
  269. case 0x2d: return "multiple icplb hit";
  270. case 0x2e: return "illegal use of supervisor resource";
  271. default: return "undef";
  272. }
  273. }
  274. void dump(struct pt_regs *fp)
  275. {
  276. char buf[150];
  277. int i;
  278. uint16_t hwerrcause, excause;
  279. if (!ENABLE_DUMP)
  280. return;
  281. #ifndef CONFIG_CMD_KGDB
  282. /* fp->ipend is normally garbage, so load it ourself */
  283. fp->ipend = bfin_read_IPEND();
  284. #endif
  285. hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
  286. excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
  287. printf("SEQUENCER STATUS:\n");
  288. printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
  289. fp->seqstat, fp->ipend, fp->syscfg);
  290. printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
  291. printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause));
  292. for (i = 6; i <= 15; ++i) {
  293. if (fp->ipend & (1 << i)) {
  294. decode_address(buf, bfin_read32(EVT0 + 4*i));
  295. printf(" physical IVG%i asserted : %s\n", i, buf);
  296. }
  297. }
  298. decode_address(buf, fp->rete);
  299. printf(" RETE: %s\n", buf);
  300. decode_address(buf, fp->retn);
  301. printf(" RETN: %s\n", buf);
  302. decode_address(buf, fp->retx);
  303. printf(" RETX: %s\n", buf);
  304. decode_address(buf, fp->rets);
  305. printf(" RETS: %s\n", buf);
  306. /* we lie and store RETI in "pc" */
  307. decode_address(buf, fp->pc);
  308. printf(" RETI: %s\n", buf);
  309. if (fp->seqstat & EXCAUSE) {
  310. decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
  311. printf("DCPLB_FAULT_ADDR: %s\n", buf);
  312. decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
  313. printf("ICPLB_FAULT_ADDR: %s\n", buf);
  314. }
  315. printf("\nPROCESSOR STATE:\n");
  316. printf(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
  317. fp->r0, fp->r1, fp->r2, fp->r3);
  318. printf(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
  319. fp->r4, fp->r5, fp->r6, fp->r7);
  320. printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
  321. fp->p0, fp->p1, fp->p2, fp->p3);
  322. printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
  323. fp->p4, fp->p5, fp->fp, (unsigned long)fp);
  324. printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
  325. fp->lb0, fp->lt0, fp->lc0);
  326. printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
  327. fp->lb1, fp->lt1, fp->lc1);
  328. printf(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
  329. fp->b0, fp->l0, fp->m0, fp->i0);
  330. printf(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
  331. fp->b1, fp->l1, fp->m1, fp->i1);
  332. printf(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
  333. fp->b2, fp->l2, fp->m2, fp->i2);
  334. printf(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
  335. fp->b3, fp->l3, fp->m3, fp->i3);
  336. printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
  337. fp->a0w, fp->a0x, fp->a1w, fp->a1x);
  338. printf("USP : %08lx ASTAT: %08lx\n",
  339. fp->usp, fp->astat);
  340. printf("\n");
  341. }
  342. static void _dump_bfin_trace_buffer(void)
  343. {
  344. char buf[150];
  345. int i = 0;
  346. if (!ENABLE_DUMP)
  347. return;
  348. printf("Hardware Trace:\n");
  349. if (bfin_read_TBUFSTAT() & TBUFCNT) {
  350. for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
  351. decode_address(buf, bfin_read_TBUF());
  352. printf("%4i Target : %s\n", i, buf);
  353. decode_address(buf, bfin_read_TBUF());
  354. printf(" Source : %s\n", buf);
  355. }
  356. }
  357. }
  358. void dump_bfin_trace_buffer(void)
  359. {
  360. unsigned long tflags;
  361. trace_buffer_save(tflags);
  362. _dump_bfin_trace_buffer();
  363. trace_buffer_restore(tflags);
  364. }
  365. void bfin_dump(struct pt_regs *regs)
  366. {
  367. unsigned long tflags;
  368. trace_buffer_save(tflags);
  369. puts(
  370. "\n"
  371. "\n"
  372. "\n"
  373. "Ack! Something bad happened to the Blackfin!\n"
  374. "\n"
  375. );
  376. dump(regs);
  377. _dump_bfin_trace_buffer();
  378. puts("\n");
  379. trace_buffer_restore(tflags);
  380. }
  381. void bfin_panic(struct pt_regs *regs)
  382. {
  383. unsigned long tflags;
  384. trace_buffer_save(tflags);
  385. bfin_dump(regs);
  386. panic("PANIC: Blackfin internal error");
  387. }