starfive_seeed_panel.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
  4. * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  5. * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  6. *
  7. * This seeed panel driver is inspired from the Linux Kernel driver
  8. * drivers/gpu/drm/panel/panel-raydium-seeed.c.
  9. */
  10. #include <common.h>
  11. #include <backlight.h>
  12. #include <dm.h>
  13. #include <mipi_dsi.h>
  14. #include <panel.h>
  15. #include <asm/gpio.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/delay.h>
  18. #include <power/regulator.h>
  19. #include <i2c.h>
  20. /* I2C registers of the Atmel microcontroller. */
  21. enum REG_ADDR {
  22. REG_ID = 0x80,
  23. REG_PORTA, /* BIT(2) for horizontal flip, BIT(3) for vertical flip */
  24. REG_PORTB,
  25. REG_PORTC,
  26. REG_PORTD,
  27. REG_POWERON,
  28. REG_PWM,
  29. REG_DDRA,
  30. REG_DDRB,
  31. REG_DDRC,
  32. REG_DDRD,
  33. REG_TEST,
  34. REG_WR_ADDRL,
  35. REG_WR_ADDRH,
  36. REG_READH,
  37. REG_READL,
  38. REG_WRITEH,
  39. REG_WRITEL,
  40. REG_ID2,
  41. };
  42. /* DSI D-PHY Layer Registers */
  43. #define D0W_DPHYCONTTX 0x0004
  44. #define CLW_DPHYCONTRX 0x0020
  45. #define D0W_DPHYCONTRX 0x0024
  46. #define D1W_DPHYCONTRX 0x0028
  47. #define COM_DPHYCONTRX 0x0038
  48. #define CLW_CNTRL 0x0040
  49. #define D0W_CNTRL 0x0044
  50. #define D1W_CNTRL 0x0048
  51. #define DFTMODE_CNTRL 0x0054
  52. /* DSI PPI Layer Registers */
  53. #define PPI_STARTPPI 0x0104
  54. #define PPI_BUSYPPI 0x0108
  55. #define PPI_LINEINITCNT 0x0110
  56. #define PPI_LPTXTIMECNT 0x0114
  57. #define PPI_CLS_ATMR 0x0140
  58. #define PPI_D0S_ATMR 0x0144
  59. #define PPI_D1S_ATMR 0x0148
  60. #define PPI_D0S_CLRSIPOCOUNT 0x0164
  61. #define PPI_D1S_CLRSIPOCOUNT 0x0168
  62. #define CLS_PRE 0x0180
  63. #define D0S_PRE 0x0184
  64. #define D1S_PRE 0x0188
  65. #define CLS_PREP 0x01A0
  66. #define D0S_PREP 0x01A4
  67. #define D1S_PREP 0x01A8
  68. #define CLS_ZERO 0x01C0
  69. #define D0S_ZERO 0x01C4
  70. #define D1S_ZERO 0x01C8
  71. #define PPI_CLRFLG 0x01E0
  72. #define PPI_CLRSIPO 0x01E4
  73. #define HSTIMEOUT 0x01F0
  74. #define HSTIMEOUTENABLE 0x01F4
  75. /* DSI Protocol Layer Registers */
  76. #define DSI_STARTDSI 0x0204
  77. #define DSI_BUSYDSI 0x0208
  78. #define DSI_LANEENABLE 0x0210
  79. #define DSI_LANEENABLE_CLOCK BIT(0)
  80. #define DSI_LANEENABLE_D0 BIT(1)
  81. #define DSI_LANEENABLE_D1 BIT(2)
  82. #define DSI_LANESTATUS0 0x0214
  83. #define DSI_LANESTATUS1 0x0218
  84. #define DSI_INTSTATUS 0x0220
  85. #define DSI_INTMASK 0x0224
  86. #define DSI_INTCLR 0x0228
  87. #define DSI_LPTXTO 0x0230
  88. #define DSI_MODE 0x0260
  89. #define DSI_PAYLOAD0 0x0268
  90. #define DSI_PAYLOAD1 0x026C
  91. #define DSI_SHORTPKTDAT 0x0270
  92. #define DSI_SHORTPKTREQ 0x0274
  93. #define DSI_BTASTA 0x0278
  94. #define DSI_BTACLR 0x027C
  95. /* DSI General Registers */
  96. #define DSIERRCNT 0x0300
  97. #define DSISIGMOD 0x0304
  98. /* DSI Application Layer Registers */
  99. #define APLCTRL 0x0400
  100. #define APLSTAT 0x0404
  101. #define APLERR 0x0408
  102. #define PWRMOD 0x040C
  103. #define RDPKTLN 0x0410
  104. #define PXLFMT 0x0414
  105. #define MEMWRCMD 0x0418
  106. /* LCDC/DPI Host Registers */
  107. #define LCDCTRL 0x0420
  108. #define HSR 0x0424
  109. #define HDISPR 0x0428
  110. #define VSR 0x042C
  111. #define VDISPR 0x0430
  112. #define VFUEN 0x0434
  113. /* DBI-B Host Registers */
  114. #define DBIBCTRL 0x0440
  115. /* SPI Master Registers */
  116. #define SPICMR 0x0450
  117. #define SPITCR 0x0454
  118. /* System Controller Registers */
  119. #define SYSSTAT 0x0460
  120. #define SYSCTRL 0x0464
  121. #define SYSPLL1 0x0468
  122. #define SYSPLL2 0x046C
  123. #define SYSPLL3 0x0470
  124. #define SYSPMCTRL 0x047C
  125. /* GPIO Registers */
  126. #define GPIOC 0x0480
  127. #define GPIOO 0x0484
  128. #define GPIOI 0x0488
  129. /* I2C Registers */
  130. #define I2CCLKCTRL 0x0490
  131. /* Chip/Rev Registers */
  132. #define IDREG 0x04A0
  133. /* printf Registers */
  134. #define WCMDQUEUE 0x0500
  135. #define RCMDQUEUE 0x0504
  136. struct seeed_panel_priv {
  137. struct udevice *reg;
  138. struct udevice *backlight;
  139. struct gpio_desc *sel_gpio; //select
  140. };
  141. static const struct display_timing default_timing = {
  142. .pixelclock.typ = 29700000,
  143. .hactive.typ = 800,
  144. .hfront_porch.typ = 90,
  145. .hback_porch.typ = 5,
  146. .hsync_len.typ = 5,
  147. .vactive.typ = 480,
  148. .vfront_porch.typ = 60,
  149. .vback_porch.typ = 5,
  150. .vsync_len.typ = 5,
  151. };
  152. static int seeed_panel_i2c_write(struct udevice *dev, uint addr, uint mask, uint data)
  153. {
  154. uint8_t valb;
  155. int err = 0;
  156. if (mask != 0xff){
  157. err = dm_i2c_read(dev, addr, &valb, 1);
  158. if (err)
  159. return err;
  160. }
  161. valb &= ~mask;
  162. valb |= data;
  163. err = dm_i2c_write(dev, addr, &valb, 1);
  164. return err;
  165. }
  166. static int seeed_panel_i2c_read(struct udevice *dev, uint8_t addr, uint8_t *data)
  167. {
  168. uint8_t valb;
  169. int err;
  170. err = dm_i2c_read(dev, addr, &valb, 1);
  171. if (err)
  172. return err;
  173. *data = (int)valb;
  174. return 0;
  175. }
  176. static void rpi_touchscreen_write(struct udevice *dev, u16 reg, u32 val)
  177. {
  178. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  179. struct mipi_dsi_device *device = plat->device;
  180. int err;
  181. u8 msg[] = {
  182. reg,
  183. reg >> 8,
  184. val,
  185. val >> 8,
  186. val >> 16,
  187. val >> 24,
  188. };
  189. err = mipi_dsi_dcs_write_buffer(device, msg, sizeof(msg));
  190. if (err < 0)
  191. dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
  192. return;
  193. }
  194. static int rm68200_panel_enable_backlight(struct udevice *dev)
  195. {
  196. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  197. struct mipi_dsi_device *device = plat->device;
  198. int ret;
  199. int i;
  200. u8 reg_value = 0;
  201. ret = mipi_dsi_attach(device);
  202. if (ret < 0)
  203. return ret;
  204. seeed_panel_i2c_write(dev, REG_POWERON, 0xff, 1);
  205. mdelay(100);
  206. /* Wait for nPWRDWN to go low to indicate poweron is done. */
  207. for (i = 0; i < 100; i++) {
  208. seeed_panel_i2c_read(dev, REG_PORTB, &reg_value);
  209. if (reg_value & 1)
  210. break;
  211. }
  212. rpi_touchscreen_write(dev, DSI_LANEENABLE,
  213. DSI_LANEENABLE_CLOCK |
  214. DSI_LANEENABLE_D0);
  215. rpi_touchscreen_write(dev,PPI_D0S_CLRSIPOCOUNT, 0x05);
  216. rpi_touchscreen_write(dev,PPI_D1S_CLRSIPOCOUNT, 0x05);
  217. rpi_touchscreen_write(dev,PPI_D0S_ATMR, 0x00);
  218. rpi_touchscreen_write(dev,PPI_D1S_ATMR, 0x00);
  219. rpi_touchscreen_write(dev,PPI_LPTXTIMECNT, 0x03);
  220. rpi_touchscreen_write(dev,SPICMR, 0x00);
  221. rpi_touchscreen_write(dev,LCDCTRL, 0x00100150);
  222. rpi_touchscreen_write(dev,SYSCTRL, 0x040f);
  223. mdelay(100);
  224. rpi_touchscreen_write(dev,PPI_STARTPPI, 0x01);
  225. rpi_touchscreen_write(dev,DSI_STARTDSI, 0x01);
  226. mdelay(100);
  227. /* Turn on the backlight. */
  228. seeed_panel_i2c_write(dev,REG_PWM, 255, 255);
  229. mdelay(100);
  230. /* Default to the same orientation as the closed source
  231. * firmware used for the panel. Runtime rotation
  232. * configuration will be supported using VC4's plane
  233. * orientation bits.
  234. */
  235. seeed_panel_i2c_write(dev,REG_PORTA,255, BIT(2));
  236. mdelay(100);
  237. return 0;
  238. }
  239. static int rm68200_panel_get_display_timing(struct udevice *dev,
  240. struct display_timing *timings)
  241. {
  242. memcpy(timings, &default_timing, sizeof(*timings));
  243. return 0;
  244. }
  245. static int rm68200_panel_of_to_plat(struct udevice *dev)
  246. {
  247. return 0;
  248. }
  249. static int rm68200_panel_probe(struct udevice *dev)
  250. {
  251. struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
  252. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_DEVKITS)
  253. struct seeed_panel_priv *priv = dev_get_priv(dev);
  254. #endif
  255. u8 reg_value = 0;
  256. /* fill characteristics of DSI data link */
  257. plat->lanes = 1;
  258. plat->format = MIPI_DSI_FMT_RGB888;
  259. plat->mode_flags = MIPI_DSI_MODE_VIDEO |
  260. MIPI_DSI_MODE_VIDEO_BURST |
  261. MIPI_DSI_MODE_LPM;
  262. seeed_panel_i2c_read(dev, 0x80, &reg_value);
  263. debug("%s,reg_value = %d\n", __func__,reg_value);
  264. switch (reg_value) {
  265. case 0xde: /* ver 1 */
  266. case 0xc3: /* ver 2 */
  267. break;
  268. default:
  269. debug("Unknown Atmel firmware revision: 0x%02x\n", reg_value);
  270. return -ENODEV;
  271. }
  272. #if CONFIG_IS_ENABLED(TARGET_STARFIVE_DEVKITS)
  273. priv->sel_gpio = devm_gpiod_get_optional(dev, "sel", GPIOD_IS_OUT);
  274. if (IS_ERR(priv->sel_gpio)) {
  275. pr_err("Failed get reset sel gpio\n");
  276. return PTR_ERR(priv->sel_gpio);
  277. }
  278. dm_gpio_set_value(priv->sel_gpio, 0);
  279. #endif
  280. return 0;
  281. }
  282. static const struct panel_ops rm68200_panel_ops = {
  283. .enable_backlight = rm68200_panel_enable_backlight,
  284. .get_display_timing = rm68200_panel_get_display_timing,
  285. };
  286. static const struct udevice_id rm68200_panel_ids[] = {
  287. { .compatible = "starfive,seeed" },
  288. { }
  289. };
  290. U_BOOT_DRIVER(seeed_panel) = {
  291. .name = "seeed_panel",
  292. .id = UCLASS_PANEL,
  293. .of_match = rm68200_panel_ids,
  294. .ops = &rm68200_panel_ops,
  295. .of_to_plat = rm68200_panel_of_to_plat,
  296. .probe = rm68200_panel_probe,
  297. .plat_auto = sizeof(struct mipi_dsi_panel_plat),
  298. .priv_auto = sizeof(struct seeed_panel_priv),
  299. };