starfive_visionfive2.dts 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /*
  3. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  4. */
  5. /dts-v1/;
  6. #include "jh7110.dtsi"
  7. #include <dt-bindings/gpio/gpio.h>
  8. #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
  9. / {
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. model = "StarFive VisionFive V2";
  13. compatible = "starfive,jh7110";
  14. aliases {
  15. spi0="/soc/spi@13010000";
  16. gpio0="/soc/gpio@13040000";
  17. ethernet0=&gmac0;
  18. ethernet1=&gmac1;
  19. mmc0=&sdio0;
  20. mmc1=&sdio1;
  21. i2c0 = &i2c5;
  22. };
  23. chosen {
  24. stdout-path = "/soc/serial@10000000:115200";
  25. starfive,boot-hart-id = <1>;
  26. };
  27. memory@80000000 {
  28. device_type = "memory";
  29. reg = <0x0 0x40000000 0x1 0x0>;
  30. };
  31. reserved-memory {
  32. #size-cells = <2>;
  33. #address-cells = <2>;
  34. ranges;
  35. opensbi {
  36. reg = <0x00 0x40000000 0x00 0x80000>;
  37. no-map;
  38. };
  39. };
  40. soc {
  41. };
  42. gpio-restart {
  43. compatible = "gpio-restart";
  44. gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
  45. };
  46. };
  47. &cpu0 {
  48. status = "okay";
  49. };
  50. &clkgen {
  51. clocks = <&osc>, <&gmac1_rmii_refin>,
  52. <&stg_apb>, <&gmac0_rmii_refin>;
  53. clock-names = "osc", "gmac1_rmii_refin",
  54. "stg_apb", "gmac0_rmii_refin";
  55. };
  56. &gpio {
  57. status = "okay";
  58. gpio-controller;
  59. uart0_pins: uart0-0 {
  60. tx-pins {
  61. pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
  62. GPOEN_ENABLE, GPI_NONE)>;
  63. bias-disable;
  64. drive-strength = <12>;
  65. input-disable;
  66. input-schmitt-disable;
  67. slew-rate = <0>;
  68. };
  69. rx-pins {
  70. pinmux = <GPIOMUX(6, GPOUT_LOW,
  71. GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
  72. bias-pull-up;
  73. drive-strength = <2>;
  74. input-enable;
  75. input-schmitt-enable;
  76. slew-rate = <0>;
  77. };
  78. };
  79. mmc0_pins: mmc0-pins {
  80. mmc0-pins-rest {
  81. pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
  82. GPOEN_ENABLE, GPI_NONE)>;
  83. bias-pull-up;
  84. drive-strength = <12>;
  85. input-disable;
  86. input-schmitt-disable;
  87. slew-rate = <0>;
  88. };
  89. };
  90. sdcard1_pins: sdcard1-pins {
  91. sdcard1-pins0 {
  92. pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
  93. GPOEN_ENABLE, GPI_NONE)>;
  94. bias-pull-up;
  95. drive-strength = <12>;
  96. input-disable;
  97. input-schmitt-disable;
  98. slew-rate = <0>;
  99. };
  100. sdcard1-pins1 {
  101. pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
  102. GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>;
  103. bias-pull-up;
  104. drive-strength = <12>;
  105. input-enable;
  106. input-schmitt-enable;
  107. slew-rate = <0>;
  108. };
  109. sdcard1-pins2 {
  110. pinmux = <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
  111. GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>;
  112. bias-pull-up;
  113. drive-strength = <12>;
  114. input-enable;
  115. input-schmitt-enable;
  116. slew-rate = <0>;
  117. };
  118. sdcard1-pins3 {
  119. pinmux = <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
  120. GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>;
  121. bias-pull-up;
  122. drive-strength = <12>;
  123. input-enable;
  124. input-schmitt-enable;
  125. slew-rate = <0>;
  126. };
  127. sdcard1-pins4 {
  128. pinmux = <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
  129. GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>;
  130. bias-pull-up;
  131. drive-strength = <12>;
  132. input-enable;
  133. input-schmitt-enable;
  134. slew-rate = <0>;
  135. };
  136. sdcard1-pins5 {
  137. pinmux = <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
  138. GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
  139. bias-pull-up;
  140. drive-strength = <12>;
  141. input-enable;
  142. input-schmitt-enable;
  143. slew-rate = <0>;
  144. };
  145. };
  146. pcie0_perst_default: pcie0_perst_default {
  147. perst-pins {
  148. pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  149. drive-strength = <2>;
  150. input-disable;
  151. input-schmitt-disable;
  152. slew-rate = <0>;
  153. };
  154. };
  155. pcie0_perst_active: pcie0_perst_active {
  156. perst-pins {
  157. pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
  158. drive-strength = <2>;
  159. input-disable;
  160. input-schmitt-disable;
  161. slew-rate = <0>;
  162. };
  163. };
  164. pcie0_wake_default: pcie0_wake_default {
  165. wake-pins {
  166. pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  167. drive-strength = <2>;
  168. input-enable;
  169. input-schmitt-disable;
  170. slew-rate = <0>;
  171. };
  172. };
  173. pcie0_clkreq_default: pcie0_clkreq_default {
  174. clkreq-pins {
  175. pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  176. drive-strength = <2>;
  177. input-enable;
  178. input-schmitt-disable;
  179. slew-rate = <0>;
  180. };
  181. };
  182. pcie1_perst_default: pcie1_perst_default {
  183. perst-pins {
  184. pinmux = <GPIOMUX(28, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  185. drive-strength = <2>;
  186. input-disable;
  187. input-schmitt-disable;
  188. slew-rate = <0>;
  189. };
  190. };
  191. pcie1_perst_active: pcie1_perst_active {
  192. perst-pins {
  193. pinmux = <GPIOMUX(28, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
  194. drive-strength = <2>;
  195. input-disable;
  196. input-schmitt-disable;
  197. slew-rate = <0>;
  198. };
  199. };
  200. pcie1_wake_default: pcie1_wake_default {
  201. wake-pins {
  202. pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  203. drive-strength = <2>;
  204. input-enable;
  205. input-schmitt-disable;
  206. slew-rate = <0>;
  207. };
  208. };
  209. pcie1_clkreq_default: pcie1_clkreq_default {
  210. clkreq-pins {
  211. pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  212. drive-strength = <2>;
  213. input-enable;
  214. input-schmitt-disable;
  215. slew-rate = <0>;
  216. };
  217. };
  218. i2c2_pins: i2c2-0 {
  219. i2c-pins {
  220. pinmux = <GPIOMUX(3, GPOUT_LOW,
  221. GPOEN_SYS_I2C2_CLK,
  222. GPI_SYS_I2C2_CLK)>,
  223. <GPIOMUX(2, GPOUT_LOW,
  224. GPOEN_SYS_I2C2_DATA,
  225. GPI_SYS_I2C2_DATA)>;
  226. bias-disable; /* external pull-up */
  227. input-enable;
  228. input-schmitt-enable;
  229. };
  230. };
  231. i2c5_pins: i2c5-0 {
  232. i2c-pins {
  233. pinmux = <GPIOMUX(19, GPOUT_LOW,
  234. GPOEN_SYS_I2C5_CLK,
  235. GPI_SYS_I2C5_CLK)>,
  236. <GPIOMUX(20, GPOUT_LOW,
  237. GPOEN_SYS_I2C5_DATA,
  238. GPI_SYS_I2C5_DATA)>;
  239. bias-disable; /* external pull-up */
  240. input-enable;
  241. input-schmitt-enable;
  242. };
  243. };
  244. hdmi_pins: hdmi-0 {
  245. cec-pins {
  246. pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
  247. GPOEN_SYS_HDMI_CEC_SDA,
  248. GPI_SYS_HDMI_CEC_SDA)>;
  249. bias-pull-up;
  250. input-enable;
  251. };
  252. hpd-pins {
  253. pinmux = <GPIOMUX(15, GPOUT_LOW,
  254. GPOEN_DISABLE,
  255. GPI_SYS_HDMI_HPD)>;
  256. input-enable;
  257. };
  258. };
  259. };
  260. &sdio0 {
  261. assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>;
  262. assigned-clock-rates = <50000000>;
  263. fifo-depth = <32>;
  264. bus-width = <8>;
  265. pinctrl-names = "default";
  266. pinctrl-0 = <&mmc0_pins>;
  267. status = "okay";
  268. };
  269. &sdio1 {
  270. assigned-clocks = <&clkgen JH7110_SDIO1_CLK_SDCARD>;
  271. assigned-clock-rates = <50000000>;
  272. fifo-depth = <32>;
  273. bus-width = <4>;
  274. pinctrl-names = "default";
  275. pinctrl-0 = <&sdcard1_pins>;
  276. status = "okay";
  277. };
  278. &gmac0 {
  279. status = "okay";
  280. #address-cells = <1>;
  281. #size-cells = <0>;
  282. phy0: ethernet-phy@0 {
  283. rgmii_sw_dr_2 = <0x0>;
  284. rgmii_sw_dr = <0x3>;
  285. rgmii_sw_dr_rxc = <0x6>;
  286. rxc_dly_en = <0>;
  287. rx_delay_sel = <0xa>;
  288. tx_delay_sel_fe = <5>;
  289. tx_delay_sel = <0xa>;
  290. tx_inverted_10 = <0x1>;
  291. tx_inverted_100 = <0x1>;
  292. tx_inverted_1000 = <0x1>;
  293. };
  294. };
  295. &gmac1 {
  296. status = "okay";
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. phy1: ethernet-phy@1 {
  300. rgmii_sw_dr_2 = <0x0>;
  301. rgmii_sw_dr = <0x3>;
  302. rgmii_sw_dr_rxc = <0x6>;
  303. tx_delay_sel_fe = <5>;
  304. tx_delay_sel = <0>;
  305. rxc_dly_en = <0>;
  306. rx_delay_sel = <0x2>;
  307. tx_inverted_10 = <0x1>;
  308. tx_inverted_100 = <0x1>;
  309. tx_inverted_1000 = <0x0>;
  310. };
  311. };
  312. &uart0 {
  313. reg-offset = <0>;
  314. current-speed = <115200>;
  315. pinctrl-names = "default";
  316. pinctrl-0 = <&uart0_pins>;
  317. status = "okay";
  318. };
  319. &i2c5 {
  320. clock-frequency = <100000>;
  321. i2c-sda-hold-time-ns = <300>;
  322. i2c-sda-falling-time-ns = <3000>;
  323. i2c-scl-falling-time-ns = <3000>;
  324. auto_calc_scl_lhcnt;
  325. status = "okay";
  326. eeprom@50 {
  327. compatible = "atmel,24c02";
  328. reg = <0x50>;
  329. pagesize = <8>;
  330. };
  331. pmic: axp15060_reg@36 {
  332. compatible = "stf,axp15060-regulator";
  333. reg = <0x36>;
  334. };
  335. };
  336. &gpioa {
  337. status = "disabled";
  338. };
  339. &usbdrd30 {
  340. starfive,usb2-only = <1>;
  341. status = "okay";
  342. };
  343. &usbdrd_cdns3 {
  344. dr_mode = "peripheral";
  345. };
  346. &pcie0 {
  347. pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
  348. pinctrl-0 = <&pcie0_perst_default>;
  349. pinctrl-1 = <&pcie0_perst_active>;
  350. pinctrl-2 = <&pcie0_wake_default>;
  351. pinctrl-3 = <&pcie0_clkreq_default>;
  352. status = "okay";
  353. };
  354. &pcie1 {
  355. pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
  356. pinctrl-0 = <&pcie1_perst_default>;
  357. pinctrl-1 = <&pcie1_perst_active>;
  358. pinctrl-2 = <&pcie1_wake_default>;
  359. pinctrl-3 = <&pcie1_clkreq_default>;
  360. status = "okay";
  361. };
  362. &timer {
  363. status = "disabled";
  364. };
  365. &wdog {
  366. status = "disabled";
  367. };
  368. &clkvout {
  369. status = "okay";
  370. };
  371. &pdm {
  372. status = "disabled";
  373. };
  374. &mipi_dsi0 {
  375. status = "okay";
  376. rockchip,panel = <&rm68200_panel>;
  377. data-lanes-num = <1>;
  378. display-timings {
  379. timing0 {
  380. bits-per-pixel = <24>;
  381. clock-frequency = <160000000>;
  382. hfront-porch = <120>;
  383. hsync-len = <20>;
  384. hback-porch = <21>;
  385. hactive = <1200>;
  386. vfront-porch = <21>;
  387. vsync-len = <3>;
  388. vback-porch = <18>;
  389. vactive = <1920>;
  390. hsync-active = <0>;
  391. vsync-active = <0>;
  392. de-active = <1>;
  393. pixelclk-active = <0>;
  394. };
  395. };
  396. };
  397. &hdmi{
  398. pinctrl-names = "default";
  399. pinctrl-0 = <&hdmi_pins>;
  400. status = "okay";
  401. };
  402. &i2c2 {
  403. clock-frequency = <100000>;
  404. i2c-sda-hold-time-ns = <300>;
  405. i2c-sda-falling-time-ns = <3000>;
  406. i2c-scl-falling-time-ns = <3000>;
  407. auto_calc_scl_lhcnt;
  408. pinctrl-names = "default";
  409. pinctrl-0 = <&i2c2_pins>;
  410. status = "okay";
  411. rm68200_panel: rm68200_panel@45 {
  412. compatible = "starfive,seeed";
  413. reg = <0x45>;
  414. };
  415. };