pinctrl-jh7110-sys.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Pinctrl / GPIO driver for StarFive JH7110 SoC
  4. *
  5. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  6. * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
  7. * Author: Jianlong Huang <jianlong.huang@starfivetech.com>
  8. */
  9. #include <dm/read.h>
  10. #include <dm/device_compat.h>
  11. #include <linux/io.h>
  12. #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
  13. #include "pinctrl-starfive.h"
  14. #define JH7110_SYS_NGPIO 64
  15. #define JH7110_SYS_GC_BASE 0
  16. /* registers */
  17. #define JH7110_SYS_DOEN 0x000
  18. #define JH7110_SYS_DOUT 0x040
  19. #define JH7110_SYS_GPI 0x080
  20. #define JH7110_SYS_GPIOIN 0x118
  21. #define JH7110_SYS_GPIOEN 0x0dc
  22. #define JH7110_SYS_GPIOIS0 0x0e0
  23. #define JH7110_SYS_GPIOIS1 0x0e4
  24. #define JH7110_SYS_GPIOIC0 0x0e8
  25. #define JH7110_SYS_GPIOIC1 0x0ec
  26. #define JH7110_SYS_GPIOIBE0 0x0f0
  27. #define JH7110_SYS_GPIOIBE1 0x0f4
  28. #define JH7110_SYS_GPIOIEV0 0x0f8
  29. #define JH7110_SYS_GPIOIEV1 0x0fc
  30. #define JH7110_SYS_GPIOIE0 0x100
  31. #define JH7110_SYS_GPIOIE1 0x104
  32. #define JH7110_SYS_GPIORIS0 0x108
  33. #define JH7110_SYS_GPIORIS1 0x10c
  34. #define JH7110_SYS_GPIOMIS0 0x110
  35. #define JH7110_SYS_GPIOMIS1 0x114
  36. #define SYS_GPO_PDA_0_74_CFG 0x120
  37. #define SYS_GPO_PDA_89_94_CFG 0x284
  38. static const struct starfive_pinctrl_pin jh7110_sys_pins[] = {
  39. STARFIVE_PINCTRL(PAD_GPIO0, "GPIO0"),
  40. STARFIVE_PINCTRL(PAD_GPIO1, "GPIO1"),
  41. STARFIVE_PINCTRL(PAD_GPIO2, "GPIO2"),
  42. STARFIVE_PINCTRL(PAD_GPIO3, "GPIO3"),
  43. STARFIVE_PINCTRL(PAD_GPIO4, "GPIO4"),
  44. STARFIVE_PINCTRL(PAD_GPIO5, "GPIO5"),
  45. STARFIVE_PINCTRL(PAD_GPIO6, "GPIO6"),
  46. STARFIVE_PINCTRL(PAD_GPIO7, "GPIO7"),
  47. STARFIVE_PINCTRL(PAD_GPIO8, "GPIO8"),
  48. STARFIVE_PINCTRL(PAD_GPIO9, "GPIO9"),
  49. STARFIVE_PINCTRL(PAD_GPIO10, "GPIO10"),
  50. STARFIVE_PINCTRL(PAD_GPIO11, "GPIO11"),
  51. STARFIVE_PINCTRL(PAD_GPIO12, "GPIO12"),
  52. STARFIVE_PINCTRL(PAD_GPIO13, "GPIO13"),
  53. STARFIVE_PINCTRL(PAD_GPIO14, "GPIO14"),
  54. STARFIVE_PINCTRL(PAD_GPIO15, "GPIO15"),
  55. STARFIVE_PINCTRL(PAD_GPIO16, "GPIO16"),
  56. STARFIVE_PINCTRL(PAD_GPIO17, "GPIO17"),
  57. STARFIVE_PINCTRL(PAD_GPIO18, "GPIO18"),
  58. STARFIVE_PINCTRL(PAD_GPIO19, "GPIO19"),
  59. STARFIVE_PINCTRL(PAD_GPIO20, "GPIO20"),
  60. STARFIVE_PINCTRL(PAD_GPIO21, "GPIO21"),
  61. STARFIVE_PINCTRL(PAD_GPIO22, "GPIO22"),
  62. STARFIVE_PINCTRL(PAD_GPIO23, "GPIO23"),
  63. STARFIVE_PINCTRL(PAD_GPIO24, "GPIO24"),
  64. STARFIVE_PINCTRL(PAD_GPIO25, "GPIO25"),
  65. STARFIVE_PINCTRL(PAD_GPIO26, "GPIO26"),
  66. STARFIVE_PINCTRL(PAD_GPIO27, "GPIO27"),
  67. STARFIVE_PINCTRL(PAD_GPIO28, "GPIO28"),
  68. STARFIVE_PINCTRL(PAD_GPIO29, "GPIO29"),
  69. STARFIVE_PINCTRL(PAD_GPIO30, "GPIO30"),
  70. STARFIVE_PINCTRL(PAD_GPIO31, "GPIO31"),
  71. STARFIVE_PINCTRL(PAD_GPIO32, "GPIO32"),
  72. STARFIVE_PINCTRL(PAD_GPIO33, "GPIO33"),
  73. STARFIVE_PINCTRL(PAD_GPIO34, "GPIO34"),
  74. STARFIVE_PINCTRL(PAD_GPIO35, "GPIO35"),
  75. STARFIVE_PINCTRL(PAD_GPIO36, "GPIO36"),
  76. STARFIVE_PINCTRL(PAD_GPIO37, "GPIO37"),
  77. STARFIVE_PINCTRL(PAD_GPIO38, "GPIO38"),
  78. STARFIVE_PINCTRL(PAD_GPIO39, "GPIO39"),
  79. STARFIVE_PINCTRL(PAD_GPIO40, "GPIO40"),
  80. STARFIVE_PINCTRL(PAD_GPIO41, "GPIO41"),
  81. STARFIVE_PINCTRL(PAD_GPIO42, "GPIO42"),
  82. STARFIVE_PINCTRL(PAD_GPIO43, "GPIO43"),
  83. STARFIVE_PINCTRL(PAD_GPIO44, "GPIO44"),
  84. STARFIVE_PINCTRL(PAD_GPIO45, "GPIO45"),
  85. STARFIVE_PINCTRL(PAD_GPIO46, "GPIO46"),
  86. STARFIVE_PINCTRL(PAD_GPIO47, "GPIO47"),
  87. STARFIVE_PINCTRL(PAD_GPIO48, "GPIO48"),
  88. STARFIVE_PINCTRL(PAD_GPIO49, "GPIO49"),
  89. STARFIVE_PINCTRL(PAD_GPIO50, "GPIO50"),
  90. STARFIVE_PINCTRL(PAD_GPIO51, "GPIO51"),
  91. STARFIVE_PINCTRL(PAD_GPIO52, "GPIO52"),
  92. STARFIVE_PINCTRL(PAD_GPIO53, "GPIO53"),
  93. STARFIVE_PINCTRL(PAD_GPIO54, "GPIO54"),
  94. STARFIVE_PINCTRL(PAD_GPIO55, "GPIO55"),
  95. STARFIVE_PINCTRL(PAD_GPIO56, "GPIO56"),
  96. STARFIVE_PINCTRL(PAD_GPIO57, "GPIO57"),
  97. STARFIVE_PINCTRL(PAD_GPIO58, "GPIO58"),
  98. STARFIVE_PINCTRL(PAD_GPIO59, "GPIO59"),
  99. STARFIVE_PINCTRL(PAD_GPIO60, "GPIO60"),
  100. STARFIVE_PINCTRL(PAD_GPIO61, "GPIO61"),
  101. STARFIVE_PINCTRL(PAD_GPIO62, "GPIO62"),
  102. STARFIVE_PINCTRL(PAD_GPIO63, "GPIO63"),
  103. STARFIVE_PINCTRL(PAD_SD0_CLK, "SD0_CLK"),
  104. STARFIVE_PINCTRL(PAD_SD0_CMD, "SD0_CMD"),
  105. STARFIVE_PINCTRL(PAD_SD0_DATA0, "SD0_DATA0"),
  106. STARFIVE_PINCTRL(PAD_SD0_DATA1, "SD0_DATA1"),
  107. STARFIVE_PINCTRL(PAD_SD0_DATA2, "SD0_DATA2"),
  108. STARFIVE_PINCTRL(PAD_SD0_DATA3, "SD0_DATA3"),
  109. STARFIVE_PINCTRL(PAD_SD0_DATA4, "SD0_DATA4"),
  110. STARFIVE_PINCTRL(PAD_SD0_DATA5, "SD0_DATA5"),
  111. STARFIVE_PINCTRL(PAD_SD0_DATA6, "SD0_DATA6"),
  112. STARFIVE_PINCTRL(PAD_SD0_DATA7, "SD0_DATA7"),
  113. STARFIVE_PINCTRL(PAD_SD0_STRB, "SD0_STRB"),
  114. STARFIVE_PINCTRL(PAD_GMAC1_MDC, "GMAC1_MDC"),
  115. STARFIVE_PINCTRL(PAD_GMAC1_MDIO, "GMAC1_MDIO"),
  116. STARFIVE_PINCTRL(PAD_GMAC1_RXD0, "GMAC1_RXD0"),
  117. STARFIVE_PINCTRL(PAD_GMAC1_RXD1, "GMAC1_RXD1"),
  118. STARFIVE_PINCTRL(PAD_GMAC1_RXD2, "GMAC1_RXD2"),
  119. STARFIVE_PINCTRL(PAD_GMAC1_RXD3, "GMAC1_RXD3"),
  120. STARFIVE_PINCTRL(PAD_GMAC1_RXDV, "GMAC1_RXDV"),
  121. STARFIVE_PINCTRL(PAD_GMAC1_RXC, "GMAC1_RXC"),
  122. STARFIVE_PINCTRL(PAD_GMAC1_TXD0, "GMAC1_TXD0"),
  123. STARFIVE_PINCTRL(PAD_GMAC1_TXD1, "GMAC1_TXD1"),
  124. STARFIVE_PINCTRL(PAD_GMAC1_TXD2, "GMAC1_TXD2"),
  125. STARFIVE_PINCTRL(PAD_GMAC1_TXD3, "GMAC1_TXD3"),
  126. STARFIVE_PINCTRL(PAD_GMAC1_TXEN, "GMAC1_TXEN"),
  127. STARFIVE_PINCTRL(PAD_GMAC1_TXC, "GMAC1_TXC"),
  128. STARFIVE_PINCTRL(PAD_QSPI_SCLK, "QSPI_SCLK"),
  129. STARFIVE_PINCTRL(PAD_QSPI_CS0, "QSPI_CS0"),
  130. STARFIVE_PINCTRL(PAD_QSPI_DATA0, "QSPI_DATA0"),
  131. STARFIVE_PINCTRL(PAD_QSPI_DATA1, "QSPI_DATA1"),
  132. STARFIVE_PINCTRL(PAD_QSPI_DATA2, "QSPI_DATA2"),
  133. STARFIVE_PINCTRL(PAD_QSPI_DATA3, "QSPI_DATA3"),
  134. };
  135. struct jh7110_func_sel {
  136. u16 offset;
  137. u8 shift;
  138. u8 max;
  139. };
  140. static const struct jh7110_func_sel
  141. jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
  142. [PAD_GMAC1_RXC] = { 0x29c, 0, 1 },
  143. [PAD_GPIO10] = { 0x29c, 2, 3 },
  144. [PAD_GPIO11] = { 0x29c, 5, 3 },
  145. [PAD_GPIO12] = { 0x29c, 8, 3 },
  146. [PAD_GPIO13] = { 0x29c, 11, 3 },
  147. [PAD_GPIO14] = { 0x29c, 14, 3 },
  148. [PAD_GPIO15] = { 0x29c, 17, 3 },
  149. [PAD_GPIO16] = { 0x29c, 20, 3 },
  150. [PAD_GPIO17] = { 0x29c, 23, 3 },
  151. [PAD_GPIO18] = { 0x29c, 26, 3 },
  152. [PAD_GPIO19] = { 0x29c, 29, 3 },
  153. [PAD_GPIO20] = { 0x2a0, 0, 3 },
  154. [PAD_GPIO21] = { 0x2a0, 3, 3 },
  155. [PAD_GPIO22] = { 0x2a0, 6, 3 },
  156. [PAD_GPIO23] = { 0x2a0, 9, 3 },
  157. [PAD_GPIO24] = { 0x2a0, 12, 3 },
  158. [PAD_GPIO25] = { 0x2a0, 15, 3 },
  159. [PAD_GPIO26] = { 0x2a0, 18, 3 },
  160. [PAD_GPIO27] = { 0x2a0, 21, 3 },
  161. [PAD_GPIO28] = { 0x2a0, 24, 3 },
  162. [PAD_GPIO29] = { 0x2a0, 27, 3 },
  163. [PAD_GPIO30] = { 0x2a4, 0, 3 },
  164. [PAD_GPIO31] = { 0x2a4, 3, 3 },
  165. [PAD_GPIO32] = { 0x2a4, 6, 3 },
  166. [PAD_GPIO33] = { 0x2a4, 9, 3 },
  167. [PAD_GPIO34] = { 0x2a4, 12, 3 },
  168. [PAD_GPIO35] = { 0x2a4, 15, 3 },
  169. [PAD_GPIO36] = { 0x2a4, 17, 3 },
  170. [PAD_GPIO37] = { 0x2a4, 20, 3 },
  171. [PAD_GPIO38] = { 0x2a4, 23, 3 },
  172. [PAD_GPIO39] = { 0x2a4, 26, 3 },
  173. [PAD_GPIO40] = { 0x2a4, 29, 3 },
  174. [PAD_GPIO41] = { 0x2a8, 0, 3 },
  175. [PAD_GPIO42] = { 0x2a8, 3, 3 },
  176. [PAD_GPIO43] = { 0x2a8, 6, 3 },
  177. [PAD_GPIO44] = { 0x2a8, 9, 3 },
  178. [PAD_GPIO45] = { 0x2a8, 12, 3 },
  179. [PAD_GPIO46] = { 0x2a8, 15, 3 },
  180. [PAD_GPIO47] = { 0x2a8, 18, 3 },
  181. [PAD_GPIO48] = { 0x2a8, 21, 3 },
  182. [PAD_GPIO49] = { 0x2a8, 24, 3 },
  183. [PAD_GPIO50] = { 0x2a8, 27, 3 },
  184. [PAD_GPIO51] = { 0x2a8, 30, 3 },
  185. [PAD_GPIO52] = { 0x2ac, 0, 3 },
  186. [PAD_GPIO53] = { 0x2ac, 2, 3 },
  187. [PAD_GPIO54] = { 0x2ac, 4, 3 },
  188. [PAD_GPIO55] = { 0x2ac, 6, 3 },
  189. [PAD_GPIO56] = { 0x2ac, 9, 3 },
  190. [PAD_GPIO57] = { 0x2ac, 12, 3 },
  191. [PAD_GPIO58] = { 0x2ac, 15, 3 },
  192. [PAD_GPIO59] = { 0x2ac, 18, 3 },
  193. [PAD_GPIO60] = { 0x2ac, 21, 3 },
  194. [PAD_GPIO61] = { 0x2ac, 24, 3 },
  195. [PAD_GPIO62] = { 0x2ac, 27, 3 },
  196. [PAD_GPIO63] = { 0x2ac, 30, 3 },
  197. [PAD_GPIO6] = { 0x2b0, 0, 3 },
  198. [PAD_GPIO7] = { 0x2b0, 2, 3 },
  199. [PAD_GPIO8] = { 0x2b0, 5, 3 },
  200. [PAD_GPIO9] = { 0x2b0, 8, 3 },
  201. };
  202. struct jh7110_vin_group_sel {
  203. u16 offset;
  204. u8 shift;
  205. u8 group;
  206. };
  207. static const struct jh7110_vin_group_sel
  208. jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
  209. [PAD_GPIO6] = { 0x2b4, 21, 0 },
  210. [PAD_GPIO7] = { 0x2b4, 18, 0 },
  211. [PAD_GPIO8] = { 0x2b4, 15, 0 },
  212. [PAD_GPIO9] = { 0x2b0, 11, 0 },
  213. [PAD_GPIO10] = { 0x2b0, 20, 0 },
  214. [PAD_GPIO11] = { 0x2b0, 23, 0 },
  215. [PAD_GPIO12] = { 0x2b0, 26, 0 },
  216. [PAD_GPIO13] = { 0x2b0, 29, 0 },
  217. [PAD_GPIO14] = { 0x2b4, 0, 0 },
  218. [PAD_GPIO15] = { 0x2b4, 3, 0 },
  219. [PAD_GPIO16] = { 0x2b4, 6, 0 },
  220. [PAD_GPIO17] = { 0x2b4, 9, 0 },
  221. [PAD_GPIO18] = { 0x2b4, 12, 0 },
  222. [PAD_GPIO19] = { 0x2b0, 14, 0 },
  223. [PAD_GPIO20] = { 0x2b0, 17, 0 },
  224. [PAD_GPIO21] = { 0x2b4, 21, 1 },
  225. [PAD_GPIO22] = { 0x2b4, 18, 1 },
  226. [PAD_GPIO23] = { 0x2b4, 15, 1 },
  227. [PAD_GPIO24] = { 0x2b0, 11, 1 },
  228. [PAD_GPIO25] = { 0x2b0, 20, 1 },
  229. [PAD_GPIO26] = { 0x2b0, 23, 1 },
  230. [PAD_GPIO27] = { 0x2b0, 26, 1 },
  231. [PAD_GPIO28] = { 0x2b0, 29, 1 },
  232. [PAD_GPIO29] = { 0x2b4, 0, 1 },
  233. [PAD_GPIO30] = { 0x2b4, 3, 1 },
  234. [PAD_GPIO31] = { 0x2b4, 6, 1 },
  235. [PAD_GPIO32] = { 0x2b4, 9, 1 },
  236. [PAD_GPIO33] = { 0x2b4, 12, 1 },
  237. [PAD_GPIO34] = { 0x2b0, 14, 1 },
  238. [PAD_GPIO35] = { 0x2b0, 17, 1 },
  239. [PAD_GPIO36] = { 0x2b4, 21, 2 },
  240. [PAD_GPIO37] = { 0x2b4, 18, 2 },
  241. [PAD_GPIO38] = { 0x2b4, 15, 2 },
  242. [PAD_GPIO39] = { 0x2b0, 11, 2 },
  243. [PAD_GPIO40] = { 0x2b0, 20, 2 },
  244. [PAD_GPIO41] = { 0x2b0, 23, 2 },
  245. [PAD_GPIO42] = { 0x2b0, 26, 2 },
  246. [PAD_GPIO43] = { 0x2b0, 29, 2 },
  247. [PAD_GPIO44] = { 0x2b4, 0, 2 },
  248. [PAD_GPIO45] = { 0x2b4, 3, 2 },
  249. [PAD_GPIO46] = { 0x2b4, 6, 2 },
  250. [PAD_GPIO47] = { 0x2b4, 9, 2 },
  251. [PAD_GPIO48] = { 0x2b4, 12, 2 },
  252. [PAD_GPIO49] = { 0x2b0, 14, 2 },
  253. [PAD_GPIO50] = { 0x2b0, 17, 2 },
  254. };
  255. static void jh7110_set_function(struct udevice *dev,
  256. unsigned int pin, u32 func)
  257. {
  258. const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
  259. struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
  260. void __iomem *reg;
  261. u32 mask;
  262. if (!fs->offset)
  263. return;
  264. if (func > fs->max)
  265. return;
  266. reg = priv->base + fs->offset;
  267. func = func << fs->shift;
  268. mask = 0x3U << fs->shift;
  269. func |= readl(reg) & ~mask;
  270. writel(func, reg);
  271. }
  272. static void jh7110_set_vin_group(struct udevice *dev, unsigned int pin)
  273. {
  274. const struct jh7110_vin_group_sel *gs =
  275. &jh7110_sys_vin_group_sel[pin];
  276. struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
  277. void __iomem *reg;
  278. u32 mask;
  279. u32 grp;
  280. if (!gs->offset)
  281. return;
  282. reg = priv->base + gs->offset;
  283. grp = gs->group << gs->shift;
  284. mask = 0x3U << gs->shift;
  285. grp |= readl(reg) & ~mask;
  286. writel(grp, reg);
  287. }
  288. static int jh7110_sys_set_one_pin_mux(struct udevice *dev, unsigned int pin,
  289. unsigned int din, u32 dout, u32 doen, u32 func)
  290. {
  291. struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
  292. if (pin < priv->info->ngpios && func == 0)
  293. starfive_set_gpiomux(dev, pin, din, dout, doen);
  294. jh7110_set_function(dev, pin, func);
  295. if (pin < priv->info->ngpios && func == 2)
  296. jh7110_set_vin_group(dev, pin);
  297. return 0;
  298. }
  299. static int jh7110_sys_get_padcfg_base(struct udevice *dev,
  300. unsigned int pin)
  301. {
  302. if (pin < PAD_GMAC1_MDC)
  303. return SYS_GPO_PDA_0_74_CFG;
  304. else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
  305. return SYS_GPO_PDA_89_94_CFG;
  306. else
  307. return -1;
  308. }
  309. static void jh7110_sys_init_hw(struct udevice *dev)
  310. {
  311. struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
  312. /* mask all GPIO interrupts */
  313. writel(0U, priv->base + JH7110_SYS_GPIOIE0);
  314. writel(0U, priv->base + JH7110_SYS_GPIOIE1);
  315. /* clear edge interrupt flags */
  316. writel(~0U, priv->base + JH7110_SYS_GPIOIC0);
  317. writel(~0U, priv->base + JH7110_SYS_GPIOIC1);
  318. /* enable GPIO interrupts */
  319. writel(1U, priv->base + JH7110_SYS_GPIOEN);
  320. }
  321. const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = {
  322. /* pin conf */
  323. .set_one_pinmux = jh7110_sys_set_one_pin_mux,
  324. .get_padcfg_base = jh7110_sys_get_padcfg_base,
  325. /* gpio dout/doen/din/gpioinput register */
  326. .dout_reg_base = JH7110_SYS_DOUT,
  327. .dout_mask = GENMASK(6, 0),
  328. .doen_reg_base = JH7110_SYS_DOEN,
  329. .doen_mask = GENMASK(5, 0),
  330. .gpi_reg_base = JH7110_SYS_GPI,
  331. .gpi_mask = GENMASK(6, 0),
  332. .gpioin_reg_base = JH7110_SYS_GPIOIN,
  333. /* gpio */
  334. .gpio_bank_name = "GPIO",
  335. .ngpios = JH7110_SYS_NGPIO,
  336. .gpio_init_hw = jh7110_sys_init_hw,
  337. };
  338. static int jh7110_sys_pinctrl_probe(struct udevice *dev)
  339. {
  340. u32 value;
  341. int ret;
  342. struct starfive_pinctrl_soc_info *info =
  343. (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
  344. struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
  345. ret = starfive_pinctrl_probe(dev, info);
  346. /* Set up the usb controller overcurrent signal. */
  347. if (!ret) {
  348. value = readl(priv->base + JH7110_SYS_GPI);
  349. value &= ~(0x7f << 16);
  350. value |= BIT(16);
  351. writel(value, priv->base + JH7110_SYS_GPI);
  352. }
  353. return ret;
  354. }
  355. static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
  356. /* JH7110 sys pinctrl */
  357. { .compatible = "starfive,jh7110-sys-pinctrl",
  358. .data = (ulong)&jh7110_sys_pinctrl_info, },
  359. { /* sentinel */ }
  360. };
  361. U_BOOT_DRIVER(jh7110_sys_pinctrl) = {
  362. .name = "jh7110-sys-pinctrl",
  363. .id = UCLASS_PINCTRL,
  364. .of_match = jh7110_sys_pinctrl_ids,
  365. .priv_auto = sizeof(struct starfive_pinctrl_priv),
  366. .ops = &starfive_pinctrl_ops,
  367. .probe = jh7110_sys_pinctrl_probe,
  368. };