Kconfig 16 KB

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  1. #
  2. # I2C subsystem configuration
  3. #
  4. menuconfig I2C
  5. bool "I2C support"
  6. default y
  7. help
  8. Note:
  9. This is a stand-in for an option to enable I2C support. In fact this
  10. simply enables building of the I2C directory for U-Boot. The actual
  11. I2C feature is enabled by DM_I2C (for driver model) and
  12. the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
  13. So at present there is no need to ever disable this option.
  14. Eventually it will:
  15. Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
  16. I2C works with a clock and data line which can be driven by a
  17. one or more masters or slaves. It is a fairly complex bus but is
  18. widely used as it only needs two lines for communication. Speeds of
  19. 400kbps are typical but up to 3.4Mbps is supported by some
  20. hardware. Enable this option to build the drivers in drivers/i2c as
  21. part of a U-Boot build.
  22. if I2C
  23. config DM_I2C
  24. bool "Enable Driver Model for I2C drivers"
  25. depends on DM
  26. help
  27. Enable driver model for I2C. The I2C uclass interface: probe, read,
  28. write and speed, is implemented with the bus drivers operations,
  29. which provide methods for bus setting and data transfer. Each chip
  30. device (bus child) info is kept as parent plat. The interface
  31. is defined in include/i2c.h.
  32. config SPL_DM_I2C
  33. bool "Enable Driver Model for I2C drivers in SPL"
  34. depends on SPL_DM && DM_I2C
  35. default y
  36. help
  37. Enable driver model for I2C. The I2C uclass interface: probe, read,
  38. write and speed, is implemented with the bus drivers operations,
  39. which provide methods for bus setting and data transfer. Each chip
  40. device (bus child) info is kept as parent platdata. The interface
  41. is defined in include/i2c.h.
  42. config I2C_CROS_EC_TUNNEL
  43. tristate "Chrome OS EC tunnel I2C bus"
  44. depends on CROS_EC
  45. help
  46. This provides an I2C bus that will tunnel i2c commands through to
  47. the other side of the Chrome OS EC to the I2C bus connected there.
  48. This will work whatever the interface used to talk to the EC (SPI,
  49. I2C or LPC). Some Chromebooks use this when the hardware design
  50. does not allow direct access to the main PMIC from the AP.
  51. config I2C_CROS_EC_LDO
  52. bool "Provide access to LDOs on the Chrome OS EC"
  53. depends on CROS_EC
  54. ---help---
  55. On many Chromebooks the main PMIC is inaccessible to the AP. This is
  56. often dealt with by using an I2C pass-through interface provided by
  57. the EC. On some unfortunate models (e.g. Spring) the pass-through
  58. is not available, and an LDO message is available instead. This
  59. option enables a driver which provides very basic access to those
  60. regulators, via the EC. We implement this as an I2C bus which
  61. emulates just the TPS65090 messages we know about. This is done to
  62. avoid duplicating the logic in the TPS65090 regulator driver for
  63. enabling/disabling an LDO.
  64. config I2C_SET_DEFAULT_BUS_NUM
  65. bool "Set default I2C bus number"
  66. depends on DM_I2C
  67. help
  68. Set default number of I2C bus to be accessed. This option provides
  69. behaviour similar to old (i.e. pre DM) I2C bus driver.
  70. config I2C_DEFAULT_BUS_NUMBER
  71. hex "I2C default bus number"
  72. depends on I2C_SET_DEFAULT_BUS_NUM
  73. default 0x0
  74. help
  75. Number of default I2C bus to use
  76. config DM_I2C_GPIO
  77. bool "Enable Driver Model for software emulated I2C bus driver"
  78. depends on DM_I2C && DM_GPIO
  79. help
  80. Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
  81. configuration is given by the device tree. Kernel-style device tree
  82. bindings are supported.
  83. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
  84. config SPL_DM_I2C_GPIO
  85. bool "Enable Driver Model for software emulated I2C bus driver in SPL"
  86. depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
  87. default y
  88. help
  89. Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
  90. configuration is given by the device tree. Kernel-style device tree
  91. bindings are supported.
  92. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
  93. config SYS_I2C_AT91
  94. bool "Atmel I2C driver"
  95. depends on DM_I2C && ARCH_AT91
  96. help
  97. Add support for the Atmel I2C driver. A serious problem is that there
  98. is no documented way to issue repeated START conditions for more than
  99. two messages, as needed to support combined I2C messages. Use the
  100. i2c-gpio driver unless your system can cope with this limitation.
  101. Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
  102. config SYS_I2C_IPROC
  103. bool "Broadcom I2C driver"
  104. depends on DM_I2C
  105. help
  106. Broadcom I2C driver.
  107. Add support for Broadcom I2C driver.
  108. Say yes here to to enable the Broadco I2C driver.
  109. config SYS_I2C_FSL
  110. bool "Freescale I2C bus driver"
  111. depends on DM_I2C
  112. help
  113. Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
  114. MPC85xx processors.
  115. config SYS_I2C_CADENCE
  116. tristate "Cadence I2C Controller"
  117. depends on DM_I2C
  118. help
  119. Say yes here to select Cadence I2C Host Controller. This controller is
  120. e.g. used by Xilinx Zynq.
  121. config SYS_I2C_CA
  122. tristate "Cortina-Access I2C Controller"
  123. depends on DM_I2C && CORTINA_PLATFORM
  124. default n
  125. help
  126. Add support for the Cortina Access I2C host controller.
  127. Say yes here to select Cortina-Access I2C Host Controller.
  128. config SYS_I2C_DAVINCI
  129. bool "Davinci I2C Controller"
  130. depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
  131. help
  132. Say yes here to add support for Davinci and Keystone I2C controller
  133. config SYS_I2C_DW
  134. bool "Designware I2C Controller"
  135. default n
  136. help
  137. Say yes here to select the Designware I2C Host Controller. This
  138. controller is used in various SoCs, e.g. the ST SPEAr, Altera
  139. SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
  140. config SPL_SYS_I2C_DW
  141. bool "Designware I2C Controller in SPL"
  142. default n
  143. help
  144. Say yes here to select the Designware I2C Host Controller in SPL. This
  145. controller is used in StarFive JH7110 SoC.
  146. config SYS_I2C_ASPEED
  147. bool "Aspeed I2C Controller"
  148. depends on DM_I2C && ARCH_ASPEED
  149. help
  150. Say yes here to select Aspeed I2C Host Controller. The driver
  151. supports AST2500 and AST2400 controllers, but is very limited.
  152. Only single master mode is supported and only byte-by-byte
  153. synchronous reads and writes are supported, no Pool Buffers or DMA.
  154. config SYS_I2C_INTEL
  155. bool "Intel I2C/SMBUS driver"
  156. depends on DM_I2C
  157. help
  158. Add support for the Intel SMBUS driver. So far this driver is just
  159. a stub which perhaps some basic init. There is no implementation of
  160. the I2C API meaning that any I2C operations will immediately fail
  161. for now.
  162. config SYS_I2C_IMX_LPI2C
  163. bool "NXP i.MX LPI2C driver"
  164. help
  165. Add support for the NXP i.MX LPI2C driver.
  166. config SYS_I2C_LPC32XX
  167. bool "LPC32XX I2C driver"
  168. depends on ARCH_LPC32XX
  169. help
  170. Enable support for the LPC32xx I2C driver.
  171. config SYS_I2C_MESON
  172. bool "Amlogic Meson I2C driver"
  173. depends on DM_I2C && ARCH_MESON
  174. help
  175. Add support for the I2C controller available in Amlogic Meson
  176. SoCs. The controller supports programmable bus speed including
  177. standard (100kbits/s) and fast (400kbit/s) speed and allows the
  178. software to define a flexible format of the bit streams. It has an
  179. internal buffer holding up to 8 bytes for transfers and supports
  180. both 7-bit and 10-bit addresses.
  181. config SYS_I2C_MXC
  182. bool "NXP MXC I2C driver"
  183. help
  184. Add support for the NXP I2C driver. This supports up to four bus
  185. channels and operating on standard mode up to 100 kbits/s and fast
  186. mode up to 400 kbits/s.
  187. # These settings are not used with DM_I2C, however SPL doesn't use
  188. # DM_I2C even if DM_I2C is enabled, and so might use these settings even
  189. # when main u-boot does not!
  190. if SYS_I2C_MXC && (!DM_I2C || SPL)
  191. config SYS_I2C_MXC_I2C1
  192. bool "NXP MXC I2C1"
  193. help
  194. Add support for NXP MXC I2C Controller 1.
  195. Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
  196. config SYS_I2C_MXC_I2C2
  197. bool "NXP MXC I2C2"
  198. help
  199. Add support for NXP MXC I2C Controller 2.
  200. Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
  201. config SYS_I2C_MXC_I2C3
  202. bool "NXP MXC I2C3"
  203. help
  204. Add support for NXP MXC I2C Controller 3.
  205. Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
  206. config SYS_I2C_MXC_I2C4
  207. bool "NXP MXC I2C4"
  208. help
  209. Add support for NXP MXC I2C Controller 4.
  210. Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
  211. config SYS_I2C_MXC_I2C5
  212. bool "NXP MXC I2C5"
  213. help
  214. Add support for NXP MXC I2C Controller 5.
  215. Required for SoCs which have I2C MXC controller 5 eg LX2160A
  216. config SYS_I2C_MXC_I2C6
  217. bool "NXP MXC I2C6"
  218. help
  219. Add support for NXP MXC I2C Controller 6.
  220. Required for SoCs which have I2C MXC controller 6 eg LX2160A
  221. config SYS_I2C_MXC_I2C7
  222. bool "NXP MXC I2C7"
  223. help
  224. Add support for NXP MXC I2C Controller 7.
  225. Required for SoCs which have I2C MXC controller 7 eg LX2160A
  226. config SYS_I2C_MXC_I2C8
  227. bool "NXP MXC I2C8"
  228. help
  229. Add support for NXP MXC I2C Controller 8.
  230. Required for SoCs which have I2C MXC controller 8 eg LX2160A
  231. endif
  232. if SYS_I2C_MXC_I2C1
  233. config SYS_MXC_I2C1_SPEED
  234. int "I2C Channel 1 speed"
  235. default 40000000 if TARGET_LS2080A_EMU
  236. default 100000
  237. help
  238. MXC I2C Channel 1 speed
  239. config SYS_MXC_I2C1_SLAVE
  240. int "I2C1 Slave"
  241. default 0
  242. help
  243. MXC I2C1 Slave
  244. endif
  245. if SYS_I2C_MXC_I2C2
  246. config SYS_MXC_I2C2_SPEED
  247. int "I2C Channel 2 speed"
  248. default 40000000 if TARGET_LS2080A_EMU
  249. default 100000
  250. help
  251. MXC I2C Channel 2 speed
  252. config SYS_MXC_I2C2_SLAVE
  253. int "I2C2 Slave"
  254. default 0
  255. help
  256. MXC I2C2 Slave
  257. endif
  258. if SYS_I2C_MXC_I2C3
  259. config SYS_MXC_I2C3_SPEED
  260. int "I2C Channel 3 speed"
  261. default 100000
  262. help
  263. MXC I2C Channel 3 speed
  264. config SYS_MXC_I2C3_SLAVE
  265. int "I2C3 Slave"
  266. default 0
  267. help
  268. MXC I2C3 Slave
  269. endif
  270. if SYS_I2C_MXC_I2C4
  271. config SYS_MXC_I2C4_SPEED
  272. int "I2C Channel 4 speed"
  273. default 100000
  274. help
  275. MXC I2C Channel 4 speed
  276. config SYS_MXC_I2C4_SLAVE
  277. int "I2C4 Slave"
  278. default 0
  279. help
  280. MXC I2C4 Slave
  281. endif
  282. if SYS_I2C_MXC_I2C5
  283. config SYS_MXC_I2C5_SPEED
  284. int "I2C Channel 5 speed"
  285. default 100000
  286. help
  287. MXC I2C Channel 5 speed
  288. config SYS_MXC_I2C5_SLAVE
  289. int "I2C5 Slave"
  290. default 0
  291. help
  292. MXC I2C5 Slave
  293. endif
  294. if SYS_I2C_MXC_I2C6
  295. config SYS_MXC_I2C6_SPEED
  296. int "I2C Channel 6 speed"
  297. default 100000
  298. help
  299. MXC I2C Channel 6 speed
  300. config SYS_MXC_I2C6_SLAVE
  301. int "I2C6 Slave"
  302. default 0
  303. help
  304. MXC I2C6 Slave
  305. endif
  306. if SYS_I2C_MXC_I2C7
  307. config SYS_MXC_I2C7_SPEED
  308. int "I2C Channel 7 speed"
  309. default 100000
  310. help
  311. MXC I2C Channel 7 speed
  312. config SYS_MXC_I2C7_SLAVE
  313. int "I2C7 Slave"
  314. default 0
  315. help
  316. MXC I2C7 Slave
  317. endif
  318. if SYS_I2C_MXC_I2C8
  319. config SYS_MXC_I2C8_SPEED
  320. int "I2C Channel 8 speed"
  321. default 100000
  322. help
  323. MXC I2C Channel 8 speed
  324. config SYS_MXC_I2C8_SLAVE
  325. int "I2C8 Slave"
  326. default 0
  327. help
  328. MXC I2C8 Slave
  329. endif
  330. config SYS_I2C_NEXELL
  331. bool "Nexell I2C driver"
  332. depends on DM_I2C
  333. help
  334. Add support for the Nexell I2C driver. This is used with various
  335. Nexell parts such as S5Pxx18 series SoCs. All chips
  336. have several I2C ports and all are provided, controlled by the
  337. device tree.
  338. config SYS_I2C_OCORES
  339. bool "ocores I2C driver"
  340. depends on DM_I2C
  341. help
  342. Add support for ocores I2C controller. For details see
  343. https://opencores.org/projects/i2c
  344. config SYS_I2C_OMAP24XX
  345. bool "TI OMAP2+ I2C driver"
  346. depends on ARCH_OMAP2PLUS || ARCH_K3
  347. help
  348. Add support for the OMAP2+ I2C driver.
  349. if SYS_I2C_OMAP24XX
  350. config SYS_OMAP24_I2C_SLAVE
  351. int "I2C Slave addr channel 0"
  352. default 1
  353. help
  354. OMAP24xx I2C Slave address channel 0
  355. config SYS_OMAP24_I2C_SPEED
  356. int "I2C Slave channel 0 speed"
  357. default 100000
  358. help
  359. OMAP24xx Slave speed channel 0
  360. endif
  361. config SYS_I2C_RCAR_I2C
  362. bool "Renesas RCar I2C driver"
  363. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  364. help
  365. Support for Renesas RCar I2C controller.
  366. config SYS_I2C_RCAR_IIC
  367. bool "Renesas RCar Gen3 IIC driver"
  368. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  369. help
  370. Support for Renesas RCar Gen3 IIC controller.
  371. config SYS_I2C_ROCKCHIP
  372. bool "Rockchip I2C driver"
  373. depends on DM_I2C
  374. help
  375. Add support for the Rockchip I2C driver. This is used with various
  376. Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
  377. have several I2C ports and all are provided, controlled by the
  378. device tree.
  379. config SYS_I2C_SANDBOX
  380. bool "Sandbox I2C driver"
  381. depends on SANDBOX && DM_I2C
  382. help
  383. Enable I2C support for sandbox. This is an emulation of a real I2C
  384. bus. Devices can be attached to the bus using the device tree
  385. which specifies the driver to use. See sandbox.dts as an example.
  386. config SYS_I2C_OCTEON
  387. bool "Octeon II/III/TX/TX2 I2C driver"
  388. depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
  389. default y
  390. help
  391. Add support for the Marvell Octeon I2C driver. This is used with
  392. various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
  393. chips have several I2C ports and all are provided, controlled by
  394. the device tree.
  395. config SYS_I2C_S3C24X0
  396. bool "Samsung I2C driver"
  397. depends on ARCH_EXYNOS4 && DM_I2C
  398. help
  399. Support for Samsung I2C controller as Samsung SoCs.
  400. config SYS_I2C_STM32F7
  401. bool "STMicroelectronics STM32F7 I2C support"
  402. depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
  403. help
  404. Enable this option to add support for STM32 I2C controller
  405. introduced with STM32F7/H7 SoCs. This I2C controller supports :
  406. _ Slave and master modes
  407. _ Multimaster capability
  408. _ Standard-mode (up to 100 kHz)
  409. _ Fast-mode (up to 400 kHz)
  410. _ Fast-mode Plus (up to 1 MHz)
  411. _ 7-bit and 10-bit addressing mode
  412. _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
  413. _ All 7-bit addresses acknowledge mode
  414. _ General call
  415. _ Programmable setup and hold times
  416. _ Easy to use event management
  417. _ Optional clock stretching
  418. _ Software reset
  419. config SYS_I2C_SYNQUACER
  420. bool "Socionext SynQuacer I2C controller"
  421. depends on ARCH_SYNQUACER && DM_I2C
  422. help
  423. Support for Socionext Synquacer I2C controller. This I2C controller
  424. will be used for RTC and LS-connector on DeveloperBox.
  425. config SYS_I2C_TEGRA
  426. bool "NVIDIA Tegra internal I2C controller"
  427. depends on ARCH_TEGRA
  428. help
  429. Support for NVIDIA I2C controller available in Tegra SoCs.
  430. config SYS_I2C_UNIPHIER
  431. bool "UniPhier I2C driver"
  432. depends on ARCH_UNIPHIER && DM_I2C
  433. default y
  434. help
  435. Support for UniPhier I2C controller driver. This I2C controller
  436. is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
  437. config SYS_I2C_UNIPHIER_F
  438. bool "UniPhier FIFO-builtin I2C driver"
  439. depends on ARCH_UNIPHIER && DM_I2C
  440. default y
  441. help
  442. Support for UniPhier FIFO-builtin I2C controller driver.
  443. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
  444. config SYS_I2C_VERSATILE
  445. bool "Arm Ltd Versatile I2C bus driver"
  446. depends on DM_I2C && TARGET_VEXPRESS64_JUNO
  447. help
  448. Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
  449. controller is present in the development boards manufactured by Arm Ltd.
  450. config SYS_I2C_MVTWSI
  451. bool "Marvell I2C driver"
  452. depends on DM_I2C
  453. help
  454. Support for Marvell I2C controllers as used on the orion5x and
  455. kirkwood SoC families.
  456. config TEGRA186_BPMP_I2C
  457. bool "Enable Tegra186 BPMP-based I2C driver"
  458. depends on TEGRA186_BPMP
  459. help
  460. Support for Tegra I2C controllers managed by the BPMP (Boot and
  461. Power Management Processor). On Tegra186, some I2C controllers are
  462. directly controlled by the main CPU, whereas others are controlled
  463. by the BPMP, and can only be accessed by the main CPU via IPC
  464. requests to the BPMP. This driver covers the latter case.
  465. config SYS_I2C_BUS_MAX
  466. int "Max I2C busses"
  467. depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
  468. default 2 if TI816X
  469. default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
  470. default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
  471. default 5 if OMAP54XX
  472. help
  473. Define the maximum number of available I2C buses.
  474. config SYS_I2C_XILINX_XIIC
  475. bool "Xilinx AXI I2C driver"
  476. depends on DM_I2C
  477. help
  478. Support for Xilinx AXI I2C controller.
  479. config SYS_I2C_IHS
  480. bool "gdsys IHS I2C driver"
  481. depends on DM_I2C
  482. help
  483. Support for gdsys IHS I2C driver on FPGA bus.
  484. source "drivers/i2c/muxes/Kconfig"
  485. endif