clk-jh7110.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clk.h>
  9. #include <clk-uclass.h>
  10. #include <clk.h>
  11. #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  12. #include <dm/device.h>
  13. #include <dm/devres.h>
  14. #include <dm.h>
  15. #include <malloc.h>
  16. #include <log.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/io.h>
  19. #define STARFIVE_CLK_ENABLE_SHIFT 31 /*[31]*/
  20. #define STARFIVE_CLK_INVERT_SHIFT 30 /*[30]*/
  21. #define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/
  22. #define STARFIVE_CLK_DIV_SHIFT 0 /*[23:0]*/
  23. #define SYS_OFFSET(id) ((id) * 4)
  24. #define STG_OFFSET(id) (((id) - JH7110_CLK_SYS_REG_END) * 4)
  25. #define AON_OFFSET(id) (((id) - JH7110_CLK_STG_REG_END) * 4)
  26. #define VOUT_OFFSET(id) (((id) - JH7110_CLK_VOUT_START) * 4)
  27. struct jh7110_clk_priv {
  28. void __iomem *sys;
  29. void __iomem *stg;
  30. void __iomem *aon;
  31. void __iomem *vout;
  32. };
  33. static const char *cpu_root_sels[2] = {
  34. [0] = "osc",
  35. [1] = "pll0_out",
  36. };
  37. static const char *perh_root_sels[2] = {
  38. [0] = "pll0_out",
  39. [1] = "pll2_out",
  40. };
  41. static const char *bus_root_sels[2] = {
  42. [0] = "osc",
  43. [1] = "pll2_out",
  44. };
  45. static const char *qspi_ref_sels[2] = {
  46. [0] = "osc",
  47. [1] = "u0_cdns_qspi_ref_src",
  48. };
  49. static const char *gmac5_tx_sels[2] = {
  50. [0] = "gmac1_gtxclk",
  51. [1] = "gmac1_rmii_rtx",
  52. };
  53. static const char *u0_dw_gmac5_axi64_clk_tx_sels[2] = {
  54. [0] = "gmac0_gtxclk",
  55. [1] = "gmac0_rmii_rtx",
  56. };
  57. static const char *mclk_sels[2] = {
  58. [0] = "mclk_inner",
  59. [1] = "mclk_ext",
  60. };
  61. static const char *u0_i2stx_4ch_bclk_sels[2] = {
  62. [0] = "i2stx_4ch0_bclk_mst",
  63. [1] = "i2stx_bclk_ext",
  64. };
  65. static const char *u0_dc8200_clk_pix_sels[2] = {
  66. [0] = "dc8200_pix0",
  67. [1] = "hdmitx0_pixelclk",
  68. };
  69. static const char *dom_vout_top_lcd_clk_sels[2] = {
  70. [0] = "u0_dc8200_clk_pix0_out",
  71. [1] = "u0_dc8200_clk_pix1_out",
  72. };
  73. static const char *u0_cdns_dsitx_clk_sels[2] = {
  74. [0] = "dc8200_pix0",
  75. [1] = "hdmitx0_pixelclk",
  76. };
  77. static ulong starfive_clk_get_rate(struct clk *clk)
  78. {
  79. struct clk *c;
  80. int ret;
  81. debug("%s(#%lu)\n", __func__, clk->id);
  82. ret = clk_get_by_id(clk->id, &c);
  83. if (ret)
  84. return ret;
  85. return clk_get_rate(c);
  86. }
  87. static ulong starfive_clk_set_rate(struct clk *clk, unsigned long rate)
  88. {
  89. struct clk *c;
  90. int ret;
  91. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  92. ret = clk_get_by_id(clk->id, &c);
  93. if (ret)
  94. return ret;
  95. return clk_set_rate(c, rate);
  96. }
  97. static int __starfive_clk_enable(struct clk *clk, bool enable)
  98. {
  99. struct clk *c;
  100. int ret;
  101. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  102. ret = clk_get_by_id(clk->id, &c);
  103. if (ret)
  104. return ret;
  105. if (enable)
  106. ret = clk_enable(c);
  107. else
  108. ret = clk_disable(c);
  109. return ret;
  110. }
  111. static int starfive_clk_disable(struct clk *clk)
  112. {
  113. return __starfive_clk_enable(clk, 0);
  114. }
  115. static int starfive_clk_enable(struct clk *clk)
  116. {
  117. return __starfive_clk_enable(clk, 1);
  118. }
  119. static int starfive_clk_set_parent(struct clk *clk, struct clk *parent)
  120. {
  121. struct clk *c, *cp;
  122. int ret;
  123. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  124. ret = clk_get_by_id(clk->id, &c);
  125. if (ret)
  126. return ret;
  127. ret = clk_get_by_id(parent->id, &cp);
  128. if (ret)
  129. return ret;
  130. ret = clk_set_parent(c, cp);
  131. c->dev->parent = cp->dev;
  132. return ret;
  133. }
  134. static const struct clk_ops starfive_clk_ops = {
  135. .set_rate = starfive_clk_set_rate,
  136. .get_rate = starfive_clk_get_rate,
  137. .enable = starfive_clk_enable,
  138. .disable = starfive_clk_disable,
  139. .set_parent = starfive_clk_set_parent,
  140. };
  141. static struct clk *starfive_clk_mux(void __iomem *reg,
  142. const char *name,
  143. unsigned int offset,
  144. u8 width,
  145. const char * const *parent_names,
  146. u8 num_parents)
  147. {
  148. return clk_register_mux(NULL, name, parent_names, num_parents, 0,
  149. reg + offset, STARFIVE_CLK_MUX_SHIFT, width, 0);
  150. }
  151. static struct clk *starfive_clk_gate(void __iomem *reg,
  152. const char *name,
  153. const char *parent_name,
  154. unsigned int offset)
  155. {
  156. return clk_register_gate(NULL, name, parent_name, 0, reg+offset,
  157. STARFIVE_CLK_ENABLE_SHIFT, 0, NULL);
  158. }
  159. static struct clk *starfive_clk_fix_factor(void __iomem *reg,
  160. const char *name,
  161. const char *parent_name,
  162. unsigned int mult,
  163. unsigned int div)
  164. {
  165. return clk_register_fixed_factor(NULL, name, parent_name,
  166. 0, mult, div);
  167. }
  168. static struct clk *starfive_clk_divider(void __iomem *reg,
  169. const char *name,
  170. const char *parent_name,
  171. unsigned int offset,
  172. u8 width)
  173. {
  174. return clk_register_divider(NULL, name, parent_name, 0, reg+offset, 0,
  175. width, CLK_DIVIDER_ONE_BASED);
  176. }
  177. static struct clk *starfive_clk_composite(void __iomem *reg,
  178. const char *name,
  179. const char * const *parent_names,
  180. unsigned int num_parents,
  181. unsigned int offset,
  182. unsigned int mux_width,
  183. unsigned int gate_width,
  184. unsigned int div_width)
  185. {
  186. struct clk *clk = ERR_PTR(-ENOMEM);
  187. struct clk_divider *div = NULL;
  188. struct clk_gate *gate = NULL;
  189. struct clk_mux *mux = NULL;
  190. int mask_arry[4] = {0x1, 0x3, 0x7, 0xF};
  191. int mask;
  192. if (mux_width) {
  193. if (mux_width > 4)
  194. goto fail;
  195. else
  196. mask = mask_arry[mux_width-1];
  197. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  198. if (!mux)
  199. goto fail;
  200. mux->reg = reg + offset;
  201. mux->mask = mask;
  202. mux->shift = STARFIVE_CLK_MUX_SHIFT;
  203. mux->num_parents = num_parents;
  204. mux->flags = 0;
  205. mux->parent_names = parent_names;
  206. }
  207. if (gate_width) {
  208. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  209. if (!gate)
  210. goto fail;
  211. gate->reg = reg + offset;
  212. gate->bit_idx = STARFIVE_CLK_ENABLE_SHIFT;
  213. gate->flags = 0;
  214. }
  215. if (div_width) {
  216. div = kzalloc(sizeof(*div), GFP_KERNEL);
  217. if (!div)
  218. goto fail;
  219. div->reg = reg + offset;
  220. if ((offset == SYS_OFFSET(JH7110_UART3_CLK_CORE)) ||
  221. (offset == SYS_OFFSET(JH7110_UART4_CLK_CORE)) ||
  222. (offset == SYS_OFFSET(JH7110_UART5_CLK_CORE))) {
  223. div->shift = 8;
  224. div->width = 8;
  225. } else {
  226. div->shift = STARFIVE_CLK_DIV_SHIFT;
  227. div->width = div_width;
  228. }
  229. div->flags = CLK_DIVIDER_ONE_BASED;
  230. div->table = NULL;
  231. }
  232. clk = clk_register_composite(NULL, name,
  233. parent_names, num_parents,
  234. &mux->clk, &clk_mux_ops,
  235. &div->clk, &clk_divider_ops,
  236. &gate->clk, &clk_gate_ops, 0);
  237. if (IS_ERR(clk))
  238. goto fail;
  239. return clk;
  240. fail:
  241. kfree(gate);
  242. kfree(div);
  243. kfree(mux);
  244. return ERR_CAST(clk);
  245. }
  246. static struct clk *starfive_clk_fix_parent_composite(void __iomem *reg,
  247. const char *name,
  248. const char *parent_names,
  249. unsigned int offset,
  250. unsigned int mux_width,
  251. unsigned int gate_width,
  252. unsigned int div_width)
  253. {
  254. const char * const *parents;
  255. parents = &parent_names;
  256. return starfive_clk_composite(reg, name, parents, 1, offset,
  257. mux_width, gate_width, div_width);
  258. }
  259. static struct clk *starfive_clk_gate_divider(void __iomem *reg,
  260. const char *name,
  261. const char *parent,
  262. unsigned int offset,
  263. unsigned int width)
  264. {
  265. const char * const *parent_names;
  266. parent_names = &parent;
  267. return starfive_clk_composite(reg, name, parent_names, 1,
  268. offset, 0, 1, width);
  269. }
  270. static int jh7110_clk_init(struct udevice *dev)
  271. {
  272. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  273. struct starfive_pll_freq conf;
  274. u64 pll;
  275. pll = starfive_jh7110_pll_get_rate(PLL0, &conf);
  276. clk_dm(JH7110_PLL0_OUT,
  277. starfive_clk_fix_factor(priv->sys,
  278. "pll0_out", "osc", conf.fbdiv,
  279. conf.prediv * conf.postdiv1));
  280. pll = starfive_jh7110_pll_get_rate(PLL1, &conf);
  281. clk_dm(JH7110_PLL1_OUT,
  282. starfive_clk_fix_factor(priv->sys,
  283. "pll1_out", "osc", conf.fbdiv,
  284. conf.prediv * conf.postdiv1));
  285. pll = starfive_jh7110_pll_get_rate(PLL2, &conf);
  286. clk_dm(JH7110_PLL2_OUT,
  287. starfive_clk_fix_factor(priv->sys,
  288. "pll2_out", "osc", conf.fbdiv,
  289. conf.prediv * conf.postdiv1));
  290. /*root*/
  291. clk_dm(JH7110_CPU_ROOT,
  292. starfive_clk_mux(priv->sys, "cpu_root",
  293. SYS_OFFSET(JH7110_CPU_ROOT), 1,
  294. cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
  295. clk_dm(JH7110_CPU_CORE,
  296. starfive_clk_divider(priv->sys,
  297. "cpu_core", "cpu_root",
  298. SYS_OFFSET(JH7110_CPU_CORE), 3));
  299. clk_dm(JH7110_CPU_BUS,
  300. starfive_clk_divider(priv->sys,
  301. "cpu_bus", "cpu_core",
  302. SYS_OFFSET(JH7110_CPU_BUS), 2));
  303. clk_dm(JH7110_DDR_ROOT,
  304. starfive_clk_fix_factor(priv->sys,
  305. "ddr_root", "pll1_out", 1, 1));
  306. clk_dm(JH7110_GMACUSB_ROOT,
  307. starfive_clk_fix_factor(priv->sys,
  308. "gmacusb_root", "pll0_out", 1, 1));
  309. clk_dm(JH7110_PERH_ROOT,
  310. starfive_clk_composite(priv->sys,
  311. "perh_root",
  312. perh_root_sels, ARRAY_SIZE(perh_root_sels),
  313. SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2));
  314. clk_dm(JH7110_BUS_ROOT,
  315. starfive_clk_mux(priv->sys, "bus_root",
  316. SYS_OFFSET(JH7110_BUS_ROOT), 1,
  317. bus_root_sels, ARRAY_SIZE(bus_root_sels)));
  318. clk_dm(JH7110_AXI_CFG0,
  319. starfive_clk_divider(priv->sys,
  320. "axi_cfg0", "bus_root",
  321. SYS_OFFSET(JH7110_AXI_CFG0), 2));
  322. clk_dm(JH7110_STG_AXIAHB,
  323. starfive_clk_divider(priv->sys,
  324. "stg_axiahb", "axi_cfg0",
  325. SYS_OFFSET(JH7110_STG_AXIAHB), 2));
  326. clk_dm(JH7110_AHB0,
  327. starfive_clk_gate(priv->sys,
  328. "ahb0", "stg_axiahb",
  329. SYS_OFFSET(JH7110_AHB0)));
  330. clk_dm(JH7110_AHB1,
  331. starfive_clk_gate(priv->sys,
  332. "ahb1", "stg_axiahb",
  333. SYS_OFFSET(JH7110_AHB1)));
  334. clk_dm(JH7110_APB_BUS_FUNC,
  335. starfive_clk_divider(priv->sys,
  336. "apb_bus_func", "stg_axiahb",
  337. SYS_OFFSET(JH7110_APB_BUS_FUNC), 4));
  338. clk_dm(JH7110_PCLK2_MUX_FUNC_PCLK,
  339. starfive_clk_fix_factor(priv->sys,
  340. "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1));
  341. clk_dm(JH7110_U2_PCLK_MUX_PCLK,
  342. starfive_clk_fix_factor(priv->sys,
  343. "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1));
  344. clk_dm(JH7110_APB_BUS,
  345. starfive_clk_fix_factor(priv->sys,
  346. "apb_bus", "u2_pclk_mux_pclk", 1, 1));
  347. clk_dm(JH7110_APB0,
  348. starfive_clk_gate(priv->sys,
  349. "apb0", "apb_bus",
  350. SYS_OFFSET(JH7110_APB0)));
  351. clk_dm(JH7110_APB12,
  352. starfive_clk_fix_factor(priv->sys,
  353. "apb12", "apb_bus", 1, 1));
  354. clk_dm(JH7110_AON_APB,
  355. starfive_clk_fix_factor(priv->sys,
  356. "aon_apb", "apb_bus_func", 1, 1));
  357. clk_dm(JH7110_NOCSTG_BUS,
  358. starfive_clk_divider(priv->sys,
  359. "nocstg_bus", "bus_root",
  360. SYS_OFFSET(JH7110_NOCSTG_BUS), 3));
  361. /*I2C*/
  362. clk_dm(JH7110_I2C0_CLK_APB,
  363. starfive_clk_gate(priv->sys,
  364. "u0_dw_i2c_clk_apb", "apb0",
  365. SYS_OFFSET(JH7110_I2C0_CLK_APB)));
  366. clk_dm(JH7110_I2C0_CLK_CORE,
  367. starfive_clk_fix_factor(priv->sys,
  368. "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 1, 1));
  369. clk_dm(JH7110_I2C1_CLK_APB,
  370. starfive_clk_gate(priv->sys,
  371. "u1_dw_i2c_clk_apb", "apb0",
  372. SYS_OFFSET(JH7110_I2C1_CLK_APB)));
  373. clk_dm(JH7110_I2C1_CLK_CORE,
  374. starfive_clk_fix_factor(priv->sys,
  375. "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 1, 1));
  376. clk_dm(JH7110_I2C2_CLK_APB,
  377. starfive_clk_gate(priv->sys,
  378. "u2_dw_i2c_clk_apb", "apb0",
  379. SYS_OFFSET(JH7110_I2C2_CLK_APB)));
  380. clk_dm(JH7110_I2C2_CLK_CORE,
  381. starfive_clk_fix_factor(priv->sys,
  382. "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1));
  383. clk_dm(JH7110_I2C3_CLK_APB,
  384. starfive_clk_gate(priv->sys,
  385. "u3_dw_i2c_clk_apb", "apb12",
  386. SYS_OFFSET(JH7110_I2C3_CLK_APB)));
  387. clk_dm(JH7110_I2C3_CLK_CORE,
  388. starfive_clk_fix_factor(priv->sys,
  389. "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 1, 1));
  390. clk_dm(JH7110_I2C4_CLK_APB,
  391. starfive_clk_gate(priv->sys,
  392. "u4_dw_i2c_clk_apb", "apb12",
  393. SYS_OFFSET(JH7110_I2C4_CLK_APB)));
  394. clk_dm(JH7110_I2C4_CLK_CORE,
  395. starfive_clk_fix_factor(priv->sys,
  396. "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 1, 1));
  397. clk_dm(JH7110_I2C5_CLK_APB,
  398. starfive_clk_gate(priv->sys,
  399. "u5_dw_i2c_clk_apb", "apb12",
  400. SYS_OFFSET(JH7110_I2C5_CLK_APB)));
  401. clk_dm(JH7110_I2C5_CLK_CORE,
  402. starfive_clk_fix_factor(priv->sys,
  403. "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1));
  404. clk_dm(JH7110_I2C6_CLK_APB,
  405. starfive_clk_gate(priv->sys,
  406. "u6_dw_i2c_clk_apb", "apb12",
  407. SYS_OFFSET(JH7110_I2C6_CLK_APB)));
  408. clk_dm(JH7110_I2C6_CLK_CORE,
  409. starfive_clk_fix_factor(priv->sys,
  410. "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 1, 1));
  411. /*QSPI*/
  412. clk_dm(JH7110_QSPI_CLK_AHB,
  413. starfive_clk_gate(priv->sys,
  414. "u0_cdns_qspi_clk_ahb", "ahb1",
  415. SYS_OFFSET(JH7110_QSPI_CLK_AHB)));
  416. clk_dm(JH7110_QSPI_CLK_APB,
  417. starfive_clk_gate(priv->sys,
  418. "u0_cdns_qspi_clk_apb", "apb12",
  419. SYS_OFFSET(JH7110_QSPI_CLK_APB)));
  420. clk_dm(JH7110_QSPI_REF_SRC,
  421. starfive_clk_divider(priv->sys,
  422. "u0_cdns_qspi_ref_src", "gmacusb_root",
  423. SYS_OFFSET(JH7110_QSPI_REF_SRC), 5));
  424. clk_dm(JH7110_QSPI_CLK_REF,
  425. starfive_clk_composite(priv->sys,
  426. "u0_cdns_qspi_clk_ref",
  427. qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
  428. SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0));
  429. /*SDIO*/
  430. clk_dm(JH7110_SDIO0_CLK_AHB,
  431. starfive_clk_gate(priv->sys,
  432. "u0_dw_sdio_clk_ahb", "ahb0",
  433. SYS_OFFSET(JH7110_SDIO0_CLK_AHB)));
  434. clk_dm(JH7110_SDIO1_CLK_AHB,
  435. starfive_clk_gate(priv->sys,
  436. "u1_dw_sdio_clk_ahb", "ahb0",
  437. SYS_OFFSET(JH7110_SDIO1_CLK_AHB)));
  438. clk_dm(JH7110_SDIO0_CLK_SDCARD,
  439. starfive_clk_fix_parent_composite(priv->sys,
  440. "u0_dw_sdio_clk_sdcard", "axi_cfg0",
  441. SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4));
  442. clk_dm(JH7110_SDIO1_CLK_SDCARD,
  443. starfive_clk_fix_parent_composite(priv->sys,
  444. "u1_dw_sdio_clk_sdcard", "axi_cfg0",
  445. SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4));
  446. /*STG*/
  447. clk_dm(JH7110_USB_125M,
  448. starfive_clk_divider(priv->sys,
  449. "usb_125m", "gmacusb_root",
  450. SYS_OFFSET(JH7110_USB_125M), 4));
  451. clk_dm(JH7110_NOC_BUS_CLK_STG_AXI,
  452. starfive_clk_gate(priv->sys,
  453. "u0_sft7110_noc_bus_clk_stg_axi",
  454. "nocstg_bus",
  455. SYS_OFFSET(JH7110_NOC_BUS_CLK_STG_AXI)));
  456. /*GMAC1*/
  457. clk_dm(JH7110_GMAC5_CLK_AHB,
  458. starfive_clk_gate(priv->sys,
  459. "u1_dw_gmac5_axi64_clk_ahb", "ahb0",
  460. SYS_OFFSET(JH7110_GMAC5_CLK_AHB)));
  461. clk_dm(JH7110_GMAC5_CLK_AXI,
  462. starfive_clk_gate(priv->sys,
  463. "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb",
  464. SYS_OFFSET(JH7110_GMAC5_CLK_AXI)));
  465. clk_dm(JH7110_GMAC_SRC,
  466. starfive_clk_divider(priv->sys,
  467. "gmac_src", "gmacusb_root",
  468. SYS_OFFSET(JH7110_GMAC_SRC), 3));
  469. clk_dm(JH7110_GMAC1_GTXCLK,
  470. starfive_clk_divider(priv->sys,
  471. "gmac1_gtxclk", "gmacusb_root",
  472. SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4));
  473. clk_dm(JH7110_GMAC1_GTXC,
  474. starfive_clk_gate(priv->sys,
  475. "gmac1_gtxc", "gmac1_gtxclk",
  476. SYS_OFFSET(JH7110_GMAC1_GTXC)));
  477. clk_dm(JH7110_GMAC1_RMII_RTX,
  478. starfive_clk_divider(priv->sys,
  479. "gmac1_rmii_rtx", "gmac1_rmii_refin",
  480. SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5));
  481. clk_dm(JH7110_GMAC5_CLK_PTP,
  482. starfive_clk_gate_divider(priv->sys,
  483. "u1_dw_gmac5_axi64_clk_ptp", "gmac_src",
  484. SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5));
  485. clk_dm(JH7110_GMAC5_CLK_TX,
  486. starfive_clk_composite(priv->sys,
  487. "u1_dw_gmac5_axi64_clk_tx",
  488. gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels),
  489. SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0));
  490. /*GMAC0*/
  491. clk_dm(JH7110_AON_AHB,
  492. starfive_clk_fix_factor(priv->sys, "aon_ahb",
  493. "stg_axiahb", 1, 1));
  494. clk_dm(JH7110_GMAC0_GTXCLK,
  495. starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk",
  496. "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4));
  497. clk_dm(JH7110_GMAC0_PTP,
  498. starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
  499. "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
  500. clk_dm(JH7110_GMAC0_GTXC,
  501. starfive_clk_gate(priv->sys,
  502. "gmac0_gtxc", "gmac0_gtxclk",
  503. SYS_OFFSET(JH7110_GMAC0_GTXC)));
  504. /*UART0*/
  505. clk_dm(JH7110_UART0_CLK_APB,
  506. starfive_clk_gate(priv->sys,
  507. "u0_dw_uart_clk_apb", "apb0",
  508. SYS_OFFSET(JH7110_UART0_CLK_APB)));
  509. clk_dm(JH7110_UART0_CLK_CORE,
  510. starfive_clk_gate(priv->sys,
  511. "u0_dw_uart_clk_core", "osc",
  512. SYS_OFFSET(JH7110_UART0_CLK_CORE)));
  513. /*UART1*/
  514. clk_dm(JH7110_UART1_CLK_APB,
  515. starfive_clk_gate(priv->sys,
  516. "u1_dw_uart_clk_apb", "apb0",
  517. SYS_OFFSET(JH7110_UART1_CLK_APB)));
  518. clk_dm(JH7110_UART1_CLK_CORE,
  519. starfive_clk_gate(priv->sys,
  520. "u1_dw_uart_clk_core", "osc",
  521. SYS_OFFSET(JH7110_UART1_CLK_CORE)));
  522. /*UART2*/
  523. clk_dm(JH7110_UART2_CLK_APB,
  524. starfive_clk_gate(priv->sys,
  525. "u2_dw_uart_clk_apb", "apb0",
  526. SYS_OFFSET(JH7110_UART2_CLK_APB)));
  527. clk_dm(JH7110_UART2_CLK_CORE,
  528. starfive_clk_gate(priv->sys,
  529. "u2_dw_uart_clk_core", "osc",
  530. SYS_OFFSET(JH7110_UART2_CLK_CORE)));
  531. /*UART3*/
  532. clk_dm(JH7110_UART3_CLK_APB,
  533. starfive_clk_gate(priv->sys,
  534. "u3_dw_uart_clk_apb", "apb0",
  535. SYS_OFFSET(JH7110_UART3_CLK_APB)));
  536. clk_dm(JH7110_UART3_CLK_CORE,
  537. starfive_clk_gate_divider(priv->sys,
  538. "u3_dw_uart_clk_core", "perh_root",
  539. SYS_OFFSET(JH7110_UART3_CLK_CORE), 8));
  540. /*UART4*/
  541. clk_dm(JH7110_UART4_CLK_APB,
  542. starfive_clk_gate(priv->sys,
  543. "u4_dw_uart_clk_apb", "apb0",
  544. SYS_OFFSET(JH7110_UART4_CLK_APB)));
  545. clk_dm(JH7110_UART4_CLK_CORE,
  546. starfive_clk_gate_divider(priv->sys,
  547. "u4_dw_uart_clk_core", "perh_root",
  548. SYS_OFFSET(JH7110_UART4_CLK_CORE), 8));
  549. /*UART5*/
  550. clk_dm(JH7110_UART5_CLK_APB,
  551. starfive_clk_gate(priv->sys,
  552. "u5_dw_uart_clk_apb", "apb0",
  553. SYS_OFFSET(JH7110_UART5_CLK_APB)));
  554. clk_dm(JH7110_UART5_CLK_CORE,
  555. starfive_clk_gate_divider(priv->sys,
  556. "u5_dw_uart_clk_core", "perh_root",
  557. SYS_OFFSET(JH7110_UART5_CLK_CORE), 8));
  558. clk_dm(JH7110_STG_APB,
  559. starfive_clk_fix_factor(priv->stg,
  560. "stg_apb", "apb_bus", 1, 1));
  561. /*USB*/
  562. clk_dm(JH7110_USB0_CLK_USB_APB,
  563. starfive_clk_gate(priv->stg,
  564. "u0_cdn_usb_clk_usb_apb", "stg_apb",
  565. STG_OFFSET(JH7110_USB0_CLK_USB_APB)));
  566. clk_dm(JH7110_USB0_CLK_UTMI_APB,
  567. starfive_clk_gate(priv->stg,
  568. "u0_cdn_usb_clk_utmi_apb", "stg_apb",
  569. STG_OFFSET(JH7110_USB0_CLK_UTMI_APB)));
  570. clk_dm(JH7110_USB0_CLK_AXI,
  571. starfive_clk_gate(priv->stg,
  572. "u0_cdn_usb_clk_axi", "stg_axiahb",
  573. STG_OFFSET(JH7110_USB0_CLK_AXI)));
  574. clk_dm(JH7110_USB0_CLK_LPM,
  575. starfive_clk_gate_divider(priv->stg,
  576. "u0_cdn_usb_clk_lpm", "osc",
  577. STG_OFFSET(JH7110_USB0_CLK_LPM), 2));
  578. clk_dm(JH7110_USB0_CLK_STB,
  579. starfive_clk_gate_divider(priv->stg,
  580. "u0_cdn_usb_clk_stb", "osc",
  581. STG_OFFSET(JH7110_USB0_CLK_STB), 3));
  582. clk_dm(JH7110_USB0_CLK_APP_125,
  583. starfive_clk_gate(priv->stg,
  584. "u0_cdn_usb_clk_app_125", "usb_125m",
  585. STG_OFFSET(JH7110_USB0_CLK_APP_125)));
  586. clk_dm(JH7110_USB0_REFCLK,
  587. starfive_clk_divider(priv->stg,
  588. "u0_cdn_usb_refclk", "osc",
  589. STG_OFFSET(JH7110_USB0_REFCLK), 2));
  590. /*GMAC1*/
  591. clk_dm(JH7110_U0_GMAC5_CLK_AHB,
  592. starfive_clk_gate(priv->aon,
  593. "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb",
  594. AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB)));
  595. clk_dm(JH7110_U0_GMAC5_CLK_AXI,
  596. starfive_clk_gate(priv->aon,
  597. "u0_dw_gmac5_axi64_clk_axi", "aon_ahb",
  598. AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI)));
  599. clk_dm(JH7110_GMAC0_RMII_RTX,
  600. starfive_clk_divider(priv->aon,
  601. "gmac0_rmii_rtx", "gmac0_rmii_refin",
  602. AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5));
  603. clk_dm(JH7110_U0_GMAC5_CLK_PTP,
  604. starfive_clk_fix_factor(priv->aon,
  605. "u0_dw_gmac5_axi64_clk_ptp",
  606. "gmac0_ptp", 1, 1));
  607. clk_dm(JH7110_U0_GMAC5_CLK_TX,
  608. starfive_clk_composite(priv->aon,
  609. "u0_dw_gmac5_axi64_clk_tx",
  610. u0_dw_gmac5_axi64_clk_tx_sels,
  611. ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels),
  612. AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0));
  613. /*otp*/
  614. clk_dm(JH7110_OTPC_CLK_APB,
  615. starfive_clk_gate(priv->aon,
  616. "u0_otpc_clk_apb", "aon_apb",
  617. AON_OFFSET(JH7110_OTPC_CLK_APB)));
  618. /*vout*/
  619. clk_dm(JH7110_VOUT_ROOT,
  620. starfive_clk_fix_factor(priv->sys,
  621. "vout_root", "pll2_out", 1, 1));
  622. clk_dm(JH7110_AUDIO_ROOT,
  623. starfive_clk_divider(priv->sys,
  624. "audio_root", "pll2_out",
  625. SYS_OFFSET(JH7110_AUDIO_ROOT), 5));
  626. clk_dm(JH7110_VOUT_SRC,
  627. starfive_clk_gate(priv->sys,
  628. "u0_dom_vout_top_clk_vout_src", "vout_root",
  629. SYS_OFFSET(JH7110_VOUT_SRC)));
  630. clk_dm(JH7110_VOUT_AXI,
  631. starfive_clk_divider(priv->sys,
  632. "vout_axi", "vout_root",
  633. SYS_OFFSET(JH7110_VOUT_AXI), 3));
  634. clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AXI,
  635. starfive_clk_gate(priv->sys,
  636. "u0_dom_vout_top_vout_axi", "vout_axi",
  637. SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AXI)));
  638. clk_dm(JH7110_NOC_BUS_CLK_DISP_AXI,
  639. starfive_clk_gate(priv->sys,
  640. "u0_sft7110_noc_bus_clk_disp_axi", "vout_axi",
  641. SYS_OFFSET(JH7110_NOC_BUS_CLK_DISP_AXI)));
  642. clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AHB,
  643. starfive_clk_gate(priv->sys,
  644. "u0_dom_vout_top_clk_vout_ahb", "ahb1",
  645. SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AHB)));
  646. clk_dm(JH7110_MCLK_INNER,
  647. starfive_clk_divider(priv->sys,
  648. "mclk_inner", "audio_root",
  649. SYS_OFFSET(JH7110_MCLK_INNER), 5));
  650. clk_dm(JH7110_MCLK,
  651. starfive_clk_mux(priv->sys, "mclk",
  652. SYS_OFFSET(JH7110_MCLK), 1,
  653. mclk_sels, ARRAY_SIZE(mclk_sels)));
  654. clk_dm(JH7110_I2STX_4CH0_BCLK_MST,
  655. starfive_clk_gate_divider(priv->sys,
  656. "i2stx_4ch0_bclk_mst", "mclk",
  657. SYS_OFFSET(JH7110_I2STX_4CH0_BCLK_MST), 5));
  658. clk_dm(JH7110_I2STX0_4CHBCLK,
  659. starfive_clk_mux(priv->sys, "u0_i2stx_4ch_bclk",
  660. SYS_OFFSET(JH7110_I2STX0_4CHBCLK), 1,
  661. u0_i2stx_4ch_bclk_sels, ARRAY_SIZE(u0_i2stx_4ch_bclk_sels)));
  662. clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK,
  663. starfive_clk_fix_factor(priv->sys,
  664. "u0_dom_vout_top_clk_hdmitx0_bclk",
  665. "u0_i2stx_4ch_bclk", 1, 1));
  666. clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
  667. starfive_clk_gate(priv->sys,
  668. "u0_dom_vout_top_clk_hdmitx0_mclk", "mclk",
  669. SYS_OFFSET(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK)));
  670. clk_dm(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
  671. starfive_clk_divider(priv->sys,
  672. "u0_dom_vout_top_clk_mipiphy_ref", "osc",
  673. SYS_OFFSET(JH7110_MCLK_INNER), 2));
  674. /*pcie0*/
  675. clk_dm(JH7110_PCIE0_CLK_TL,
  676. starfive_clk_gate(priv->stg,
  677. "u0_plda_pcie_clk_tl",
  678. "stg_axiahb",
  679. STG_OFFSET(JH7110_PCIE0_CLK_TL)));
  680. clk_dm(JH7110_PCIE0_CLK_AXI_MST0,
  681. starfive_clk_gate(priv->stg,
  682. "u0_plda_pcie_clk_axi_mst0",
  683. "stg_axiahb",
  684. STG_OFFSET(JH7110_PCIE0_CLK_AXI_MST0)));
  685. clk_dm(JH7110_PCIE0_CLK_APB,
  686. starfive_clk_gate(priv->stg,
  687. "u0_plda_pcie_clk_apb",
  688. "stg_apb",
  689. STG_OFFSET(JH7110_PCIE0_CLK_APB)));
  690. /*pcie1*/
  691. clk_dm(JH7110_PCIE1_CLK_TL,
  692. starfive_clk_gate(priv->stg,
  693. "u1_plda_pcie_clk_tl",
  694. "stg_axiahb",
  695. STG_OFFSET(JH7110_PCIE1_CLK_TL)));
  696. clk_dm(JH7110_PCIE1_CLK_AXI_MST0,
  697. starfive_clk_gate(priv->stg,
  698. "u1_plda_pcie_clk_axi_mst0",
  699. "stg_axiahb",
  700. STG_OFFSET(JH7110_PCIE1_CLK_AXI_MST0)));
  701. clk_dm(JH7110_PCIE1_CLK_APB,
  702. starfive_clk_gate(priv->stg,
  703. "u1_plda_pcie_clk_apb",
  704. "stg_apb",
  705. STG_OFFSET(JH7110_PCIE1_CLK_APB)));
  706. return 0;
  707. }
  708. static int jh7110_clk_vout_init(struct udevice *dev)
  709. {
  710. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  711. clk_dm(JH7110_DISP_ROOT,
  712. starfive_clk_fix_factor(priv->vout,
  713. "disp_root", "u0_dom_vout_top_clk_vout_src",
  714. 1, 1));
  715. clk_dm(JH7110_DISP_AXI,
  716. starfive_clk_fix_factor(priv->vout,
  717. "disp_axi", "u0_dom_vout_top_vout_axi",
  718. 1, 1));
  719. clk_dm(JH7110_DISP_AHB,
  720. starfive_clk_fix_factor(priv->vout,
  721. "disp_ahb", "u0_dom_vout_top_clk_vout_ahb",
  722. 1, 1));
  723. clk_dm(JH7110_HDMITX0_MCLK,
  724. starfive_clk_fix_factor(priv->vout,
  725. "hdmitx0_mclk", "u0_dom_vout_top_clk_hdmitx0_mclk",
  726. 1, 1));
  727. clk_dm(JH7110_HDMITX0_SCK,
  728. starfive_clk_fix_factor(priv->vout,
  729. "hdmitx0_sck", "u0_dom_vout_top_clk_hdmitx0_bclk",
  730. 1, 1));
  731. clk_dm(JH7110_APB,
  732. starfive_clk_divider(priv->vout,
  733. "apb", "disp_ahb",
  734. VOUT_OFFSET(JH7110_APB), 5));
  735. clk_dm(JH7110_U0_PCLK_MUX_FUNC_PCLK,
  736. starfive_clk_fix_factor(priv->vout,
  737. "u0_pclk_mux_func_pclk", "apb",
  738. 1, 1));
  739. clk_dm(JH7110_DISP_APB,
  740. starfive_clk_fix_factor(priv->vout,
  741. "disp_apb", "u0_pclk_mux_func_pclk",
  742. 1, 1));
  743. clk_dm(JH7110_TX_ESC,
  744. starfive_clk_divider(priv->vout,
  745. "tx_esc", "disp_ahb",
  746. VOUT_OFFSET(JH7110_TX_ESC), 5));
  747. clk_dm(JH7110_DC8200_PIX0,
  748. starfive_clk_divider(priv->vout,
  749. "dc8200_pix0", "disp_root",
  750. VOUT_OFFSET(JH7110_DC8200_PIX0), 6));
  751. clk_dm(JH7110_DSI_SYS,
  752. starfive_clk_divider(priv->vout,
  753. "dsi_sys", "disp_root",
  754. VOUT_OFFSET(JH7110_DSI_SYS), 5));
  755. clk_dm(JH7110_U0_DC8200_CLK_PIX0,
  756. starfive_clk_composite(priv->vout,
  757. "u0_dc8200_clk_pix0",
  758. u0_dc8200_clk_pix_sels,
  759. ARRAY_SIZE(u0_dc8200_clk_pix_sels),
  760. VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX0), 1, 1, 0));
  761. clk_dm(JH7110_U0_DC8200_CLK_PIX1,
  762. starfive_clk_composite(priv->vout,
  763. "u0_dc8200_clk_pix1",
  764. u0_dc8200_clk_pix_sels,
  765. ARRAY_SIZE(u0_dc8200_clk_pix_sels),
  766. VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX1), 1, 1, 0));
  767. clk_dm(JH7110_U0_DC8200_CLK_AXI,
  768. starfive_clk_gate(priv->vout,
  769. "u0_dc8200_clk_axi", "disp_axi",
  770. VOUT_OFFSET(JH7110_U0_DC8200_CLK_AXI)));
  771. clk_dm(JH7110_U0_DC8200_CLK_CORE,
  772. starfive_clk_gate(priv->vout,
  773. "u0_dc8200_clk_core", "disp_axi",
  774. VOUT_OFFSET(JH7110_U0_DC8200_CLK_CORE)));
  775. clk_dm(JH7110_U0_DC8200_CLK_AHB,
  776. starfive_clk_gate(priv->vout,
  777. "u0_dc8200_clk_ahb", "disp_ahb",
  778. VOUT_OFFSET(JH7110_U0_DC8200_CLK_AHB)));
  779. clk_dm(JH7110_U0_DC8200_CLK_PIX0_OUT,
  780. starfive_clk_fix_factor(priv->vout,
  781. "u0_dc8200_clk_pix0_out", "u0_dc8200_clk_pix0",
  782. 1, 1));
  783. clk_dm(JH7110_U0_DC8200_CLK_PIX1_OUT,
  784. starfive_clk_fix_factor(priv->sys,
  785. "u0_dc8200_clk_pix1_out", "u0_dc8200_clk_pix1",
  786. 1, 1));
  787. clk_dm(JH7110_DOM_VOUT_TOP_LCD_CLK,
  788. starfive_clk_composite(priv->vout,
  789. "dom_vout_top_lcd_clk",
  790. dom_vout_top_lcd_clk_sels,
  791. ARRAY_SIZE(dom_vout_top_lcd_clk_sels),
  792. VOUT_OFFSET(JH7110_DOM_VOUT_TOP_LCD_CLK), 1, 1, 0));
  793. clk_dm(JH7110_U0_MIPITX_DPHY_CLK_TXESC,
  794. starfive_clk_gate(priv->vout,
  795. "u0_mipitx_dphy_clk_txesc", "tx_esc",
  796. VOUT_OFFSET(JH7110_U0_MIPITX_DPHY_CLK_TXESC)));
  797. clk_dm(JH7110_U0_CDNS_DSITX_CLK_SYS,
  798. starfive_clk_gate(priv->vout,
  799. "u0_cdns_dsiTx_clk_sys", "dsi_sys",
  800. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_SYS)));
  801. clk_dm(JH7110_U0_CDNS_DSITX_CLK_APB,
  802. starfive_clk_gate(priv->vout,
  803. "u0_cdns_dsiTx_clk_apb", "dsi_sys",
  804. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_APB)));
  805. clk_dm(JH7110_U0_CDNS_DSITX_CLK_TXESC,
  806. starfive_clk_gate(priv->vout,
  807. "u0_cdns_dsiTx_clk_txesc", "tx_esc",
  808. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_TXESC)));
  809. clk_dm(JH7110_U0_CDNS_DSITX_CLK_DPI,
  810. starfive_clk_composite(priv->vout,
  811. "u0_cdns_dsitx_clk_api",
  812. u0_cdns_dsitx_clk_sels,
  813. ARRAY_SIZE(u0_cdns_dsitx_clk_sels),
  814. VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_DPI), 1, 1, 0));
  815. clk_dm(JH7110_U0_HDMI_TX_CLK_SYS,
  816. starfive_clk_gate(priv->vout,
  817. "u0_hdmi_tx_clk_sys", "disp_apb",
  818. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_SYS)));
  819. clk_dm(JH7110_U0_HDMI_TX_CLK_MCLK,
  820. starfive_clk_gate(priv->vout,
  821. "u0_hdmi_tx_clk_mclk", "hdmitx0_mclk",
  822. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_MCLK)));
  823. clk_dm(JH7110_U0_HDMI_TX_CLK_BCLK,
  824. starfive_clk_gate(priv->vout,
  825. "u0_hdmi_tx_clk_bclk", "hdmitx0_sck",
  826. VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_BCLK)));
  827. return 0;
  828. }
  829. static int jh7110_clk_vout_probe(struct udevice *dev)
  830. {
  831. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  832. priv->vout = (void __iomem *)dev_read_addr(dev);
  833. if (!priv->vout)
  834. return -EINVAL;
  835. return jh7110_clk_vout_init(dev);
  836. }
  837. static int jh7110_clk_probe(struct udevice *dev)
  838. {
  839. struct jh7110_clk_priv *priv = dev_get_priv(dev);
  840. priv->aon = dev_remap_addr_name(dev, "aon");
  841. if (!priv->aon)
  842. return -EINVAL;
  843. priv->sys = dev_remap_addr_name(dev, "sys");
  844. if (!priv->sys)
  845. return -EINVAL;
  846. priv->stg = dev_remap_addr_name(dev, "stg");
  847. if (!priv->stg)
  848. return -EINVAL;
  849. return jh7110_clk_init(dev);
  850. }
  851. static const struct udevice_id jh7110_clk_of_match[] = {
  852. { .compatible = "starfive,jh7110-clkgen" },
  853. { }
  854. };
  855. U_BOOT_DRIVER(jh7110_clk) = {
  856. .name = "jh7110_clk",
  857. .id = UCLASS_CLK,
  858. .of_match = jh7110_clk_of_match,
  859. .probe = jh7110_clk_probe,
  860. .ops = &starfive_clk_ops,
  861. .priv_auto = sizeof(struct jh7110_clk_priv),
  862. };
  863. static const struct udevice_id jh7110_clk_vout_of_match[] = {
  864. { .compatible = "starfive,jh7110-clk-vout" },
  865. { }
  866. };
  867. U_BOOT_DRIVER(jh7110_clk_vout) = {
  868. .name = "jh7110_clk_vout",
  869. .id = UCLASS_CLK,
  870. .of_match = jh7110_clk_vout_of_match,
  871. .probe = jh7110_clk_vout_probe,
  872. .ops = &starfive_clk_ops,
  873. .priv_auto = sizeof(struct jh7110_clk_priv),
  874. };