starfive_visionfive2.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022 Starfive, Inc.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/eeprom.h>
  10. #include <asm/arch/jh7110-regs.h>
  11. #include <cpu_func.h>
  12. #include <dm/uclass.h>
  13. #include <dm/device.h>
  14. #include <env.h>
  15. #include <inttypes.h>
  16. #include <misc.h>
  17. #include <linux/bitops.h>
  18. #include <asm/arch/gpio.h>
  19. #include <bmp_logo.h>
  20. #include <video.h>
  21. #include <splash.h>
  22. #define SYS_CLOCK_ENABLE(clk) \
  23. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  24. #define PCB_REVISION_MASK 0xF0
  25. #define PCB_REVISION_SHIFT 4
  26. #define PCB_REVISION_A 0x0A
  27. #define PCB_REVISION_B 0x0B
  28. #define CHIP_REVISION_SHIFT 80
  29. #define CPU_VOL_BINNING_OFFSET 0x7fc
  30. enum {
  31. BOOT_FLASH = 0,
  32. BOOT_SD,
  33. BOOT_EMMC,
  34. BOOT_UART,
  35. };
  36. enum chip_type_t {
  37. CHIP_A = 0,
  38. CHIP_B,
  39. CHIP_MAX,
  40. };
  41. enum board_type_t {
  42. BOARD_1000M_1000M = 0,
  43. BOARD_1000M_100M,
  44. BOARD_TYPE_MAX,
  45. };
  46. enum cpu_voltage_type_t {
  47. CPU_VOL_1020 = 0xef0,
  48. CPU_VOL_1040 = 0xfff,
  49. CPU_VOL_1060 = 0xff0,
  50. CPU_VOL_1000 = 0x8f0,
  51. };
  52. #define CPU_VOL_MASK 0xfff
  53. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  54. {
  55. u32 value;
  56. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  57. do {
  58. value = in_le32(SYS_CRG_BASE + status);
  59. } while ((value & BIT(rst)) != BIT(rst));
  60. }
  61. static void jh7110_timer_init(void)
  62. {
  63. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  64. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  65. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  66. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  67. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  68. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  69. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  70. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  71. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  72. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  73. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  74. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  75. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  76. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  77. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  78. }
  79. static void jh7110_gmac_init_1000M(int id)
  80. {
  81. switch (id) {
  82. case 0:
  83. clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12,
  84. GMAC5_0_SEL_I_MASK,
  85. BIT(GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK);
  86. break;
  87. case 1:
  88. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144,
  89. GMAC5_1_SEL_I_MASK,
  90. BIT(GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK);
  91. break;
  92. default:
  93. break;
  94. }
  95. }
  96. static void jh7110_gmac_init_100M(int id)
  97. {
  98. switch (id) {
  99. case 0:
  100. clrsetbits_le32(AON_SYSCON_BASE + AON_SYSCFG_12,
  101. GMAC5_0_SEL_I_MASK,
  102. (4 << GMAC5_0_SEL_I_SHIFT) & GMAC5_0_SEL_I_MASK);
  103. setbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT, 0x1000000);
  104. setbits_le32(AON_CRG_BASE + GMAC5_0_CLK_RX_SHIFT, 0x1000000);
  105. break;
  106. case 1:
  107. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_144,
  108. GMAC5_1_SEL_I_MASK,
  109. (4 << GMAC5_1_SEL_I_SHIFT) & GMAC5_1_SEL_I_MASK);
  110. setbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT, 0x1000000);
  111. setbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_RX_SHIFT, 0x1000000);
  112. break;
  113. default:
  114. break;
  115. }
  116. }
  117. static void jh7110_gmac_sel_tx_to_rgmii(int id)
  118. {
  119. switch (id) {
  120. case 0:
  121. clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
  122. GMAC5_0_CLK_TX_MASK,
  123. BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
  124. break;
  125. case 1:
  126. clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
  127. GMAC5_1_CLK_TX_MASK,
  128. BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
  129. break;
  130. default:
  131. break;
  132. }
  133. }
  134. static void set_uboot_fdt_addr_env(void)
  135. {
  136. char str[17];
  137. ulong fdt_addr = (ulong)gd->fdt_blob;
  138. sprintf(str, "0x%lx", fdt_addr);
  139. env_set("uboot_fdt_addr", str);
  140. }
  141. static int get_chip_type(void)
  142. {
  143. int type;
  144. int len = -1;
  145. u8 data;
  146. len = get_data_from_eeprom(CHIP_REVISION_SHIFT, 1, &data);
  147. if (len <= 0) {
  148. env_set("chip_vision", "UNKOWN");
  149. return -EINVAL;
  150. }
  151. switch (data) {
  152. case 'a':
  153. case 'A':
  154. type = CHIP_A;
  155. env_set("chip_vision", "A");
  156. break;
  157. case 'b':
  158. case 'B':
  159. type = CHIP_B;
  160. env_set("chip_vision", "B");
  161. break;
  162. default:
  163. type = CHIP_MAX;
  164. env_set("chip_vision", "UNKOWN");
  165. break;
  166. }
  167. return type;
  168. }
  169. static int get_board_type(void)
  170. {
  171. u8 pv;
  172. int type;
  173. pv = get_pcb_revision_from_eeprom();
  174. pv = (pv & PCB_REVISION_MASK) >> PCB_REVISION_SHIFT;
  175. if (pv == PCB_REVISION_A) {
  176. type = BOARD_1000M_100M;
  177. } else if (pv == PCB_REVISION_B) {
  178. type = BOARD_1000M_1000M;
  179. } else {
  180. type = BOARD_TYPE_MAX;
  181. }
  182. return type;
  183. }
  184. static void jh7110_gmac_init(int chip_type, int pcb_type)
  185. {
  186. switch (chip_type) {
  187. case CHIP_A:
  188. break;
  189. case CHIP_B:
  190. default:
  191. jh7110_gmac_sel_tx_to_rgmii(0);
  192. jh7110_gmac_sel_tx_to_rgmii(1);
  193. break;
  194. }
  195. switch (pcb_type) {
  196. case BOARD_1000M_100M:
  197. jh7110_gmac_init_1000M(0);
  198. jh7110_gmac_init_100M(1);
  199. break;
  200. case BOARD_1000M_1000M:
  201. default:
  202. jh7110_gmac_init_1000M(0);
  203. jh7110_gmac_init_1000M(1);
  204. break;
  205. }
  206. }
  207. static void jh7110_usb_init(bool usb2_enable)
  208. {
  209. if (usb2_enable) {
  210. /*usb 2.0 utmi phy init*/
  211. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  212. USB_MODE_STRAP_MASK,
  213. (2<<USB_MODE_STRAP_SHIFT) &
  214. USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
  215. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  216. USB_OTG_SUSPENDM_BYPS_MASK,
  217. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  218. & USB_OTG_SUSPENDM_BYPS_MASK);
  219. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  220. USB_OTG_SUSPENDM_MASK,
  221. BIT(USB_OTG_SUSPENDM_SHIFT) &
  222. USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
  223. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  224. USB_PLL_EN_MASK,
  225. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  226. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  227. USB_REFCLK_MODE_MASK,
  228. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  229. /* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  230. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  231. PDRSTN_SPLIT_MASK,
  232. BIT(PDRSTN_SPLIT_SHIFT) &
  233. PDRSTN_SPLIT_MASK);
  234. } else {
  235. /*usb 3.0 pipe phy config*/
  236. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  237. PCIE_CKREF_SRC_MASK,
  238. (0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
  239. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  240. PCIE_CLK_SEL_MASK,
  241. (0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
  242. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_328,
  243. PCIE_PHY_MODE_MASK,
  244. BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
  245. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  246. PCIE_USB3_BUS_WIDTH_MASK,
  247. (0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
  248. PCIE_USB3_BUS_WIDTH_MASK);
  249. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  250. PCIE_USB3_RATE_MASK,
  251. (0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
  252. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  253. PCIE_USB3_RX_STANDBY_MASK,
  254. (0 << PCIE_USB3_RX_STANDBY_SHIFT)
  255. & PCIE_USB3_RX_STANDBY_MASK);
  256. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  257. PCIE_USB3_PHY_ENABLE_MASK,
  258. BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
  259. & PCIE_USB3_PHY_ENABLE_MASK);
  260. /* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  261. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  262. PDRSTN_SPLIT_MASK,
  263. (0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  264. }
  265. SYS_IOMUX_DOEN(25, LOW);
  266. SYS_IOMUX_DOUT(25, 7);
  267. }
  268. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  269. static void get_cpu_voltage_type(struct udevice *dev)
  270. {
  271. int ret;
  272. u32 buf = CPU_VOL_1040;
  273. ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf));
  274. if (ret != sizeof(buf))
  275. printf("%s: error reading CPU vol from OTP\n", __func__);
  276. else {
  277. switch ((buf & CPU_VOL_MASK)) {
  278. case CPU_VOL_1000:
  279. env_set("cpu_max_vol", "1000000");
  280. break;
  281. case CPU_VOL_1060:
  282. env_set("cpu_max_vol", "1060000");
  283. break;
  284. case CPU_VOL_1020:
  285. env_set("cpu_max_vol", "1020000");
  286. break;
  287. default:
  288. env_set("cpu_max_vol", "1040000");
  289. break;
  290. }
  291. }
  292. }
  293. #endif
  294. static void jh7110_jtag_init(void)
  295. {
  296. /*jtag*/
  297. SYS_IOMUX_DOEN(36, HIGH);
  298. SYS_IOMUX_DIN(36, 4);
  299. SYS_IOMUX_DOEN(61, HIGH);
  300. SYS_IOMUX_DIN(61, 19);
  301. SYS_IOMUX_DOEN(63, HIGH);
  302. SYS_IOMUX_DIN(63, 20);
  303. SYS_IOMUX_DOEN(60, HIGH);
  304. SYS_IOMUX_DIN(60, 29);
  305. SYS_IOMUX_DOEN(44, 8);
  306. SYS_IOMUX_DOUT(44, 22);
  307. }
  308. static void jh7110_i2c_init(int id)
  309. {
  310. switch (id) {
  311. case 5:
  312. //scl
  313. SYS_IOMUX_COMPLEX(19, 79, 0, 42);
  314. //sda
  315. SYS_IOMUX_COMPLEX(20, 80, 0, 43);
  316. break;
  317. default:
  318. break;
  319. }
  320. }
  321. static void get_boot_mode(void)
  322. {
  323. u32 value;
  324. value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG);
  325. switch (value & 0x03) {
  326. case BOOT_FLASH:
  327. env_set("bootmode", "flash");
  328. env_set("devnum", "1");
  329. break;
  330. case BOOT_SD:
  331. env_set("bootmode", "sd");
  332. env_set("devnum", "1");
  333. break;
  334. case BOOT_EMMC:
  335. env_set("bootmode", "emmc");
  336. env_set("devnum", "0");
  337. break;
  338. default:
  339. env_set("bootmode", "uart");
  340. env_set("devnum", "1");
  341. break;
  342. }
  343. }
  344. static void jh7110_gpio_init(void)
  345. {
  346. /* This is for fixing don't detect wm8960 occasionally.
  347. * Set scl/sda gpio output enable
  348. * Set drive strength to 12mA
  349. * Set gpio pull up
  350. */
  351. SYS_IOMUX_COMPLEX(57, 9, 0, 1);
  352. SYS_IOMUX_SET_DS(57, 3);
  353. SYS_IOMUX_SET_PULL(57, GPIO_PULL_UP);
  354. SYS_IOMUX_COMPLEX(58, 10, 0, 1);
  355. SYS_IOMUX_SET_DS(58, 3);
  356. SYS_IOMUX_SET_PULL(58, GPIO_PULL_UP);
  357. }
  358. int board_init(void)
  359. {
  360. enable_caches();
  361. jh7110_jtag_init();
  362. jh7110_timer_init();
  363. jh7110_usb_init(true);
  364. jh7110_i2c_init(5);
  365. jh7110_gpio_init();
  366. return 0;
  367. }
  368. #ifdef CONFIG_BOARD_LATE_INIT
  369. int board_late_init(void)
  370. {
  371. struct udevice *dev;
  372. int ret;
  373. get_boot_mode();
  374. jh7110_gmac_init(get_chip_type(), get_board_type());
  375. /*
  376. * save the memory info by environment variable in u-boot,
  377. * It will used to update the memory configuration in dts,
  378. * which passed to kernel lately.
  379. */
  380. env_set_hex("memory_addr", gd->ram_base);
  381. env_set_hex("memory_size", gd->ram_size);
  382. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  383. if (ret)
  384. return ret;
  385. ret = video_bmp_display(dev, (ulong)&bmp_logo_bitmap[0], BMP_ALIGN_CENTER, BMP_ALIGN_CENTER, true);
  386. if (ret)
  387. goto err;
  388. err:
  389. return 0;
  390. }
  391. #endif
  392. #ifdef CONFIG_MISC_INIT_R
  393. int misc_init_r(void)
  394. {
  395. char mac0[6] = {0x6c, 0xcf, 0x39, 0x6c, 0xde, 0xad};
  396. char mac1[6] = {0x6c, 0xcf, 0x39, 0x7c, 0xae, 0x5d};
  397. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  398. struct udevice *dev;
  399. char buf[16];
  400. int ret;
  401. #define MACADDR_OFFSET 0x8
  402. ret = uclass_get_device_by_driver(UCLASS_MISC,
  403. DM_DRIVER_GET(starfive_otp), &dev);
  404. if (ret) {
  405. debug("%s: could not find otp device\n", __func__);
  406. goto err;
  407. }
  408. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  409. if (ret != sizeof(buf))
  410. printf("%s: error reading mac from OTP\n", __func__);
  411. else
  412. if (buf[0] != 0xff) {
  413. memcpy(mac0, buf, 6);
  414. memcpy(mac1, &buf[8], 6);
  415. }
  416. err:
  417. #endif
  418. eth_env_set_enetaddr("eth0addr", mac0);
  419. eth_env_set_enetaddr("eth1addr", mac1);
  420. get_chip_type();
  421. set_uboot_fdt_addr_env();
  422. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  423. get_cpu_voltage_type(dev);
  424. #endif
  425. return 0;
  426. }
  427. #endif
  428. #ifdef CONFIG_ID_EEPROM
  429. #include <asm/arch/eeprom.h>
  430. #define STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET 91
  431. static bool check_eeprom_dram_info(ulong size)
  432. {
  433. switch (size) {
  434. case 1:
  435. case 2:
  436. case 4:
  437. case 8:
  438. case 16:
  439. return true;
  440. default:
  441. return false;
  442. }
  443. }
  444. static int resize_ddr_from_eeprom(void)
  445. {
  446. struct udevice *dev;
  447. ulong size;
  448. u32 len = 1;
  449. u8 data = 0;
  450. int ret;
  451. /* I2C init */
  452. ret = uclass_get_device(UCLASS_I2C, 0, &dev);
  453. if (ret) {
  454. debug("I2C init failed: %d\n", ret);
  455. return 0;
  456. }
  457. /* read memory size info */
  458. ret = get_data_from_eeprom(STARFIVE_JH7110_EEPROM_DDRINFO_OFFSET, len, &data);
  459. if (ret == len) {
  460. size = hextoul(&data, NULL);
  461. if (check_eeprom_dram_info(size))
  462. return size;
  463. }
  464. return 0;
  465. }
  466. #else
  467. static int resize_ddr_from_eeprom(void)
  468. {
  469. return 0;
  470. }
  471. #endif /* CONFIG_ID_EEPROM */
  472. int board_ddr_size(void)
  473. {
  474. return resize_ddr_from_eeprom();
  475. }