starfive_devkits.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/jh7110-regs.h>
  10. #include <asm/gpio.h>
  11. #include <cpu_func.h>
  12. #include <dm/uclass.h>
  13. #include <dm/device.h>
  14. #include <env.h>
  15. #include <i2c.h>
  16. #include <inttypes.h>
  17. #include <misc.h>
  18. #include <linux/bitops.h>
  19. #include <asm/arch/gpio.h>
  20. #include <bmp_logo.h>
  21. #include <video.h>
  22. #include <splash.h>
  23. #include <asm/gpio.h>
  24. #include <linux/err.h>
  25. #define SYS_CLOCK_ENABLE(clk) \
  26. setbits_le32(SYS_CRG_BASE + clk, CLK_ENABLE_MASK)
  27. #define CPU_VOL_BINNING_OFFSET 0x7fc
  28. enum {
  29. BOOT_FLASH = 0,
  30. BOOT_SD,
  31. BOOT_EMMC,
  32. BOOT_UART,
  33. };
  34. enum cpu_voltage_type_t {
  35. CPU_VOL_1020 = 0xef0,
  36. CPU_VOL_1040 = 0xfff,
  37. CPU_VOL_1060 = 0xff0,
  38. CPU_VOL_1000 = 0x8f0,
  39. };
  40. #define CPU_VOL_MASK 0xfff
  41. static void sys_reset_clear(ulong assert, ulong status, u32 rst)
  42. {
  43. u32 value;
  44. clrbits_le32(SYS_CRG_BASE + assert, BIT(rst));
  45. do {
  46. value = in_le32(SYS_CRG_BASE + status);
  47. } while ((value & BIT(rst)) != BIT(rst));
  48. }
  49. static void jh7110_timer_init(void)
  50. {
  51. SYS_CLOCK_ENABLE(TIMER_CLK_APB_SHIFT);
  52. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER0_SHIFT);
  53. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER1_SHIFT);
  54. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER2_SHIFT);
  55. SYS_CLOCK_ENABLE(TIMER_CLK_TIMER3_SHIFT);
  56. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  57. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_APB_SHIFT);
  58. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  59. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER0_SHIFT);
  60. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  61. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER1_SHIFT);
  62. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  63. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER2_SHIFT);
  64. sys_reset_clear(SYS_CRG_RESET_ASSERT3_SHIFT,
  65. SYS_CRG_RESET_STATUS3_SHIFT, TIMER_RSTN_TIMER3_SHIFT);
  66. }
  67. static void jh7110_i2c_init (int id)
  68. {
  69. switch (id) {
  70. case 5:
  71. //scl
  72. SYS_IOMUX_COMPLEX(19, 79, 0, 42);
  73. //sda
  74. SYS_IOMUX_COMPLEX(20, 80, 0, 43);
  75. break;
  76. default:
  77. break;
  78. }
  79. }
  80. static void jh7110_gmac_sel_tx_to_rgmii(int id)
  81. {
  82. switch (id) {
  83. case 0:
  84. clrsetbits_le32(AON_CRG_BASE + GMAC5_0_CLK_TX_SHIFT,
  85. GMAC5_0_CLK_TX_MASK,
  86. BIT(GMAC5_0_CLK_TX_BIT) & GMAC5_0_CLK_TX_MASK);
  87. break;
  88. case 1:
  89. clrsetbits_le32(SYS_CRG_BASE + GMAC5_1_CLK_TX_SHIFT,
  90. GMAC5_1_CLK_TX_MASK,
  91. BIT(GMAC5_1_CLK_TX_BIT) & GMAC5_1_CLK_TX_MASK);
  92. break;
  93. default:
  94. break;
  95. }
  96. }
  97. static void jh7110_gmac_io_pad(int id)
  98. {
  99. u32 cap = BIT(0); /* 2.5V */
  100. switch (id) {
  101. case 0:
  102. /* Improved GMAC0 TX I/O PAD capability */
  103. clrsetbits_le32(AON_IOMUX_BASE + 0x78, 0x3, cap & 0x3);
  104. clrsetbits_le32(AON_IOMUX_BASE + 0x7c, 0x3, cap & 0x3);
  105. clrsetbits_le32(AON_IOMUX_BASE + 0x80, 0x3, cap & 0x3);
  106. clrsetbits_le32(AON_IOMUX_BASE + 0x84, 0x3, cap & 0x3);
  107. clrsetbits_le32(AON_IOMUX_BASE + 0x88, 0x3, cap & 0x3);
  108. break;
  109. case 1:
  110. /* Improved GMAC1 TX I/O PAD capability */
  111. clrsetbits_le32(SYS_IOMUX_BASE + 0x26c, 0x3, cap & 0x3);
  112. clrsetbits_le32(SYS_IOMUX_BASE + 0x270, 0x3, cap & 0x3);
  113. clrsetbits_le32(SYS_IOMUX_BASE + 0x274, 0x3, cap & 0x3);
  114. clrsetbits_le32(SYS_IOMUX_BASE + 0x278, 0x3, cap & 0x3);
  115. clrsetbits_le32(SYS_IOMUX_BASE + 0x27c, 0x3, cap & 0x3);
  116. break;
  117. }
  118. }
  119. static void jh7110_gmac_init(int id)
  120. {
  121. jh7110_gmac_sel_tx_to_rgmii(id);
  122. jh7110_gmac_io_pad(id);
  123. }
  124. static void jh7110_usb_init(bool usb2_enable)
  125. {
  126. if (usb2_enable) {
  127. /*usb 2.0 utmi phy init*/
  128. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  129. USB_MODE_STRAP_MASK,
  130. (2<<USB_MODE_STRAP_SHIFT) &
  131. USB_MODE_STRAP_MASK);/*2:host mode, 4:device mode*/
  132. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  133. USB_OTG_SUSPENDM_BYPS_MASK,
  134. BIT(USB_OTG_SUSPENDM_BYPS_SHIFT)
  135. & USB_OTG_SUSPENDM_BYPS_MASK);
  136. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  137. USB_OTG_SUSPENDM_MASK,
  138. BIT(USB_OTG_SUSPENDM_SHIFT) &
  139. USB_OTG_SUSPENDM_MASK);/*HOST = 1. DEVICE = 0;*/
  140. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  141. USB_PLL_EN_MASK,
  142. BIT(USB_PLL_EN_SHIFT) & USB_PLL_EN_MASK);
  143. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_4,
  144. USB_REFCLK_MODE_MASK,
  145. BIT(USB_REFCLK_MODE_SHIFT) & USB_REFCLK_MODE_MASK);
  146. /* usb 2.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  147. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  148. PDRSTN_SPLIT_MASK,
  149. BIT(PDRSTN_SPLIT_SHIFT) &
  150. PDRSTN_SPLIT_MASK);
  151. } else {
  152. /*usb 3.0 pipe phy config*/
  153. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  154. PCIE_CKREF_SRC_MASK,
  155. (0<<PCIE_CKREF_SRC_SHIFT) & PCIE_CKREF_SRC_MASK);
  156. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_196,
  157. PCIE_CLK_SEL_MASK,
  158. (0<<PCIE_CLK_SEL_SHIFT) & PCIE_CLK_SEL_MASK);
  159. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_328,
  160. PCIE_PHY_MODE_MASK,
  161. BIT(PCIE_PHY_MODE_SHIFT) & PCIE_PHY_MODE_MASK);
  162. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  163. PCIE_USB3_BUS_WIDTH_MASK,
  164. (0 << PCIE_USB3_BUS_WIDTH_SHIFT) &
  165. PCIE_USB3_BUS_WIDTH_MASK);
  166. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  167. PCIE_USB3_RATE_MASK,
  168. (0 << PCIE_USB3_RATE_SHIFT) & PCIE_USB3_RATE_MASK);
  169. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  170. PCIE_USB3_RX_STANDBY_MASK,
  171. (0 << PCIE_USB3_RX_STANDBY_SHIFT)
  172. & PCIE_USB3_RX_STANDBY_MASK);
  173. clrsetbits_le32(STG_SYSCON_BASE + STG_SYSCON_500,
  174. PCIE_USB3_PHY_ENABLE_MASK,
  175. BIT(PCIE_USB3_PHY_ENABLE_SHIFT)
  176. & PCIE_USB3_PHY_ENABLE_MASK);
  177. /* usb 3.0 phy mode,REPLACE USB3.0 PHY module = 1;else = 0*/
  178. clrsetbits_le32(SYS_SYSCON_BASE + SYS_SYSCON_24,
  179. PDRSTN_SPLIT_MASK,
  180. (0 << PDRSTN_SPLIT_SHIFT) & PDRSTN_SPLIT_MASK);
  181. }
  182. }
  183. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  184. static void get_cpu_voltage_type(struct udevice *dev)
  185. {
  186. int ret;
  187. u32 buf = CPU_VOL_1040;
  188. ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf));
  189. if (ret != sizeof(buf))
  190. printf("%s: error reading CPU vol from OTP\n", __func__);
  191. else {
  192. switch ((buf & CPU_VOL_MASK)) {
  193. case CPU_VOL_1000:
  194. env_set("cpu_max_vol", "1000000");
  195. break;
  196. case CPU_VOL_1060:
  197. env_set("cpu_max_vol", "1060000");
  198. break;
  199. case CPU_VOL_1020:
  200. env_set("cpu_max_vol", "1020000");
  201. break;
  202. default:
  203. env_set("cpu_max_vol", "1040000");
  204. break;
  205. }
  206. }
  207. }
  208. #endif
  209. static void get_boot_mode(void)
  210. {
  211. u32 value;
  212. value = in_le32(AON_IOMUX_BASE + AON_GPIO_DIN_REG);
  213. switch (value & 0x03) {
  214. case BOOT_FLASH:
  215. env_set("bootmode", "flash");
  216. env_set("devnum", "1");
  217. break;
  218. case BOOT_SD:
  219. env_set("bootmode", "sd");
  220. env_set("devnum", "1");
  221. break;
  222. case BOOT_EMMC:
  223. env_set("bootmode", "emmc");
  224. env_set("devnum", "0");
  225. break;
  226. default:
  227. env_set("bootmode", "uart");
  228. env_set("devnum", "1");
  229. break;
  230. }
  231. }
  232. #define CONFIG_SYS_PMIC_BUS_NUM 5
  233. #define CONFIG_SYS_I2C_PMIC_ADDR 0x36
  234. #define CONFIG_SYS_I2C_PMIC_ADDR_LEN 1
  235. #define AXP15060_DCDC_MODE_CTRL_2 0x1b
  236. #define AXP15060_DCDC5_MODE_BIT BIT(4)
  237. #define AXP15060_PWR_SEQUENCE_CTRL 0X32
  238. #define AXP15060_RST_PMIC_BY_PWROK_BIT BIT(4)
  239. int set_pmic(void)
  240. {
  241. int ret;
  242. struct udevice *dev;
  243. u8 temp_buf;
  244. ret = i2c_get_chip_for_busnum(CONFIG_SYS_PMIC_BUS_NUM,
  245. CONFIG_SYS_I2C_PMIC_ADDR,
  246. CONFIG_SYS_I2C_PMIC_ADDR_LEN,
  247. &dev);
  248. if (!ret) {
  249. /* Set Pmic DCDC5 Mode as PWM */
  250. ret = dm_i2c_read(dev,
  251. AXP15060_DCDC_MODE_CTRL_2,
  252. &temp_buf,
  253. sizeof(temp_buf));
  254. if (ret)
  255. printf("%s: can't read pmic dcdc5 mode register\n",
  256. __func__);
  257. temp_buf = temp_buf | AXP15060_DCDC5_MODE_BIT;
  258. ret = dm_i2c_write(dev,
  259. AXP15060_DCDC_MODE_CTRL_2,
  260. &temp_buf,
  261. sizeof(temp_buf));
  262. if (ret)
  263. printf("%s: can't write pmic dcdc5 mode register\n",
  264. __func__);
  265. /* Enable PWROK in PMIC */
  266. ret = dm_i2c_read(dev,
  267. AXP15060_PWR_SEQUENCE_CTRL,
  268. &temp_buf,
  269. sizeof(temp_buf));
  270. if (ret)
  271. printf("%s: can't read pmic power disbale & down sequence register\n",
  272. __func__);
  273. temp_buf = temp_buf | AXP15060_RST_PMIC_BY_PWROK_BIT;
  274. ret = dm_i2c_write(dev,
  275. AXP15060_PWR_SEQUENCE_CTRL,
  276. &temp_buf,
  277. sizeof(temp_buf));
  278. if (ret)
  279. printf("%s: can't write pmic power disbale & down sequence register\n",
  280. __func__);
  281. }
  282. return 0;
  283. }
  284. int board_init(void)
  285. {
  286. enable_caches();
  287. jh7110_timer_init();
  288. jh7110_usb_init(true);
  289. jh7110_gmac_init(0);
  290. jh7110_gmac_init(1);
  291. jh7110_i2c_init(5);
  292. return 0;
  293. }
  294. #ifdef CONFIG_MISC_INIT_R
  295. int misc_init_r(void)
  296. {
  297. char mac0[6] = {0x6c, 0xcf, 0x39, 0x6c, 0xde, 0xad};
  298. char mac1[6] = {0x6c, 0xcf, 0x39, 0x7c, 0xae, 0x5d};
  299. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  300. struct udevice *dev;
  301. char buf[16];
  302. int ret;
  303. #define MACADDR_OFFSET 0x8
  304. ret = uclass_get_device_by_driver(UCLASS_MISC,
  305. DM_DRIVER_GET(starfive_otp), &dev);
  306. if (ret) {
  307. debug("%s: could not find otp device\n", __func__);
  308. goto err;
  309. }
  310. ret = misc_read(dev, MACADDR_OFFSET, buf, sizeof(buf));
  311. if (ret != sizeof(buf))
  312. printf("%s: error reading mac from OTP\n", __func__);
  313. else
  314. if (buf[0] != 0xff) {
  315. memcpy(mac0, buf, 6);
  316. memcpy(mac1, &buf[8], 6);
  317. }
  318. err:
  319. #endif
  320. eth_env_set_enetaddr("eth0addr", mac0);
  321. eth_env_set_enetaddr("eth1addr", mac1);
  322. #if CONFIG_IS_ENABLED(STARFIVE_OTP)
  323. get_cpu_voltage_type(dev);
  324. #endif
  325. return 0;
  326. }
  327. #endif
  328. int board_late_init(void)
  329. {
  330. struct udevice *dev;
  331. int ret;
  332. get_boot_mode();
  333. env_set("chip_vision", "B");
  334. /*
  335. * save the memory info by environment variable in u-boot,
  336. * It will used to update the memory configuration in dts,
  337. * which passed to kernel lately.
  338. */
  339. env_set_hex("memory_addr", gd->ram_base);
  340. env_set_hex("memory_size", gd->ram_size);
  341. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  342. if (ret)
  343. return ret;
  344. ret = video_bmp_display(dev, (ulong)&bmp_logo_bitmap[0], BMP_ALIGN_CENTER, BMP_ALIGN_CENTER, true);
  345. if (ret)
  346. goto err;
  347. err:
  348. return 0;
  349. }
  350. static int jh7110_get_gpio_val(u32 gpio)
  351. {
  352. int ret;
  353. ret = gpio_request(gpio, "ddr_gpio");
  354. if (!ret) {
  355. ret = gpio_direction_input(gpio);
  356. if (!ret)
  357. ret = gpio_get_value(gpio);
  358. gpio_free(gpio);
  359. }
  360. return ret;
  361. }
  362. int board_ddr_size(void)
  363. {
  364. int val, ret;
  365. val = jh7110_get_gpio_val(21);
  366. if (IS_ERR_VALUE(val))
  367. return val;
  368. ret = jh7110_get_gpio_val(22);
  369. if (IS_ERR_VALUE(ret))
  370. return ret;
  371. val |= (ret << 1);
  372. switch (val) {
  373. case 0x0:
  374. ret = 8; //8GB
  375. break;
  376. case 0x1:
  377. ret = 4; //4GB
  378. break;
  379. case 0x2:
  380. ret = 2; //2GB
  381. break;
  382. case 0x3:
  383. ret = 1; //1GB
  384. break;
  385. default:
  386. ret = -EINVAL;
  387. break;
  388. };
  389. return ret;
  390. }
  391. static int starfive_get_gpio_val(u32 gpio)
  392. {
  393. int ret;
  394. ret = gpio_request(gpio, "ddr_gpio");
  395. if (!ret) {
  396. ret = gpio_direction_input(gpio);
  397. if (!ret)
  398. ret = gpio_get_value(gpio);
  399. gpio_free(gpio);
  400. }
  401. return ret;
  402. }
  403. /* get ddr type from GPIO23,GPIO24 DDR4 or LPDDR4 */
  404. int starfive_get_ddr_type(void)
  405. {
  406. int val, ret;
  407. val = starfive_get_gpio_val(23);
  408. if (IS_ERR_VALUE(val))
  409. return val;
  410. ret = starfive_get_gpio_val(24);
  411. if (IS_ERR_VALUE(ret))
  412. return ret;
  413. return val | (ret << 1);
  414. }