jh7110-u-boot.dtsi 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /*
  3. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  4. */
  5. #include <dt-bindings/reset/starfive-jh7110.h>
  6. #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  7. / {
  8. cpus: cpus {
  9. u-boot,dm-spl;
  10. timebase-frequency = <4000000>;
  11. cpu0: cpu@0 {
  12. u-boot,dm-spl;
  13. status = "okay";
  14. cpu0intctrl: interrupt-controller {
  15. u-boot,dm-spl;
  16. };
  17. };
  18. cpu1: cpu@1 {
  19. u-boot,dm-spl;
  20. status = "okay";
  21. cpu1intctrl: interrupt-controller {
  22. u-boot,dm-spl;
  23. };
  24. };
  25. cpu2: cpu@2 {
  26. u-boot,dm-spl;
  27. status = "okay";
  28. cpu2intctrl: interrupt-controller {
  29. u-boot,dm-spl;
  30. };
  31. };
  32. cpu3: cpu@3 {
  33. u-boot,dm-spl;
  34. status = "okay";
  35. cpu3intctrl: interrupt-controller {
  36. u-boot,dm-spl;
  37. };
  38. };
  39. cpu4: cpu@4 {
  40. u-boot,dm-spl;
  41. status = "okay";
  42. cpu4intctrl: interrupt-controller {
  43. u-boot,dm-spl;
  44. };
  45. };
  46. };
  47. soc {
  48. u-boot,dm-spl;
  49. clint: clint@2000000 {
  50. u-boot,dm-spl;
  51. };
  52. dmc: dmc@100b0000 {
  53. compatible = "starfive,jh7110-dmc";
  54. reg = <0x0 0x15700000 0x0 0x10000 0x0 0x13000000 0x0 0x10000>;
  55. resets = <&rstgen RSTN_U0_DDR_AXI>,
  56. <&rstgen RSTN_U0_DDR_OSC>,
  57. <&rstgen RSTN_U0_DDR_APB>;
  58. reset-names = "axi", "osc", "apb";
  59. clock-frequency = <2133>;
  60. u-boot,dm-spl;
  61. };
  62. };
  63. };
  64. &cachectrl {
  65. reg = <0x0 0x2010000 0x0 0x4000>,
  66. <0x0 0x2030000 0x0 0x80000>,
  67. <0x0 0x8000000 0x0 0x2000000>;
  68. reg-names = "control", "prefetcher", "sideband";
  69. prefetch-dist-size = <0x4>;
  70. prefetch-hart-mask = <0x1e>;
  71. prefetch-enable;
  72. };
  73. &uart0 {
  74. clock-frequency = <24000000>;
  75. current-speed = <115200>;
  76. status = "okay";
  77. u-boot,dm-spl;
  78. };
  79. &sdio0 {
  80. u-boot,dm-spl;
  81. };
  82. &sdio1 {
  83. u-boot,dm-spl;
  84. };
  85. &qspi {
  86. status = "okay";
  87. u-boot,dm-spl;
  88. };
  89. &rstgen {
  90. status = "okay";
  91. u-boot,dm-spl;
  92. };
  93. &nor_flash {
  94. u-boot,dm-spl;
  95. };
  96. &clkgen {
  97. u-boot,dm-spl;
  98. };
  99. &osc {
  100. u-boot,dm-spl;
  101. };
  102. &gmac1_rmii_refin{
  103. u-boot,dm-spl;
  104. };
  105. &stg_apb {
  106. u-boot,dm-spl;
  107. };
  108. &gmac0_rmii_refin {
  109. u-boot,dm-spl;
  110. };
  111. &gpio {
  112. u-boot,dm-spl;
  113. };
  114. &gpioa {
  115. u-boot,dm-spl;
  116. };