clocks.cfg 696 B

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  1. /* set the default clock gate to save power */
  2. DATA 4, CCM_CCGR0, 0x00C03F3F
  3. DATA 4, CCM_CCGR1, 0x0030FC03
  4. DATA 4, CCM_CCGR2, 0x0FFFC000
  5. DATA 4, CCM_CCGR3, 0x3FF00000
  6. DATA 4, CCM_CCGR4, 0x00FFF300
  7. DATA 4, CCM_CCGR5, 0x0F0000C3
  8. DATA 4, CCM_CCGR6, 0x000003FF
  9. /* enable AXI cache for VDOA/VPU/IPU */
  10. DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
  11. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  12. DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
  13. DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
  14. /*
  15. * Setup CCM_CCOSR register as follows:
  16. *
  17. * cko1_en 1 --> CKO1 enabled
  18. * cko1_div 111 --> divide by 8
  19. * cko1_sel 1011 --> ahb_clk_root
  20. *
  21. * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
  22. */
  23. DATA 4, CCM_CCOSR, 0x000000fb