cpu_init.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2003 Motorola Inc.
  6. * Modified by Xianghua Xiao, X.Xiao@motorola.com
  7. *
  8. * (C) Copyright 2000
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <env.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <watchdog.h>
  16. #include <asm/processor.h>
  17. #include <ioports.h>
  18. #include <sata.h>
  19. #include <fm_eth.h>
  20. #include <asm/io.h>
  21. #include <asm/cache.h>
  22. #include <asm/mmu.h>
  23. #include <fsl_errata.h>
  24. #include <asm/fsl_law.h>
  25. #include <asm/fsl_serdes.h>
  26. #include <asm/fsl_srio.h>
  27. #ifdef CONFIG_FSL_CORENET
  28. #include <asm/fsl_portals.h>
  29. #include <asm/fsl_liodn.h>
  30. #include <fsl_qbman.h>
  31. #endif
  32. #include <fsl_usb.h>
  33. #include <hwconfig.h>
  34. #include <linux/compiler.h>
  35. #include "mp.h"
  36. #ifdef CONFIG_CHAIN_OF_TRUST
  37. #include <fsl_validate.h>
  38. #endif
  39. #ifdef CONFIG_FSL_CAAM
  40. #include <fsl_sec.h>
  41. #endif
  42. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
  43. #include <asm/fsl_pamu.h>
  44. #include <fsl_secboot_err.h>
  45. #endif
  46. #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
  47. #include <nand.h>
  48. #include <errno.h>
  49. #endif
  50. #ifndef CONFIG_ARCH_QEMU_E500
  51. #include <fsl_ddr.h>
  52. #endif
  53. #include "../../../../drivers/ata/fsl_sata.h"
  54. #ifdef CONFIG_U_QE
  55. #include <fsl_qe.h>
  56. #endif
  57. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  58. /*
  59. * For deriving usb clock from 100MHz sysclk, reference divisor is set
  60. * to a value of 5, which gives an intermediate value 20(100/5). The
  61. * multiplication factor integer is set to 24, which when multiplied to
  62. * above intermediate value provides clock for usb ip.
  63. */
  64. void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
  65. {
  66. sys_info_t sysinfo;
  67. get_sys_info(&sysinfo);
  68. if (sysinfo.diff_sysclk == 1) {
  69. clrbits_be32(&usb_phy->pllprg[1],
  70. CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
  71. setbits_be32(&usb_phy->pllprg[1],
  72. CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
  73. CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
  74. CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
  75. }
  76. }
  77. #endif
  78. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  79. void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  80. {
  81. #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  82. u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  83. /* Increase Disconnect Threshold by 50mV */
  84. xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  85. INC_DCNT_THRESHOLD_50MV;
  86. /* Enable programming of USB High speed Disconnect threshold */
  87. xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  88. out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  89. xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  90. /* Increase Disconnect Threshold by 50mV */
  91. xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  92. INC_DCNT_THRESHOLD_50MV;
  93. /* Enable programming of USB High speed Disconnect threshold */
  94. xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  95. out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
  96. #else
  97. u32 temp = 0;
  98. u32 status = in_be32(&usb_phy->status1);
  99. u32 squelch_prog_rd_0_2 =
  100. (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
  101. & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  102. u32 squelch_prog_rd_3_5 =
  103. (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
  104. & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  105. setbits_be32(&usb_phy->config1,
  106. CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
  107. setbits_be32(&usb_phy->config2,
  108. CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
  109. temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
  110. out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  111. temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
  112. out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  113. #endif
  114. }
  115. #endif
  116. #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
  117. extern qe_iop_conf_t qe_iop_conf_tab[];
  118. extern void qe_config_iopin(u8 port, u8 pin, int dir,
  119. int open_drain, int assign);
  120. extern void qe_init(uint qe_base);
  121. extern void qe_reset(void);
  122. static void config_qe_ioports(void)
  123. {
  124. u8 port, pin;
  125. int dir, open_drain, assign;
  126. int i;
  127. for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  128. port = qe_iop_conf_tab[i].port;
  129. pin = qe_iop_conf_tab[i].pin;
  130. dir = qe_iop_conf_tab[i].dir;
  131. open_drain = qe_iop_conf_tab[i].open_drain;
  132. assign = qe_iop_conf_tab[i].assign;
  133. qe_config_iopin(port, pin, dir, open_drain, assign);
  134. }
  135. }
  136. #endif
  137. #ifdef CONFIG_CPM2
  138. void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  139. {
  140. int portnum;
  141. for (portnum = 0; portnum < 4; portnum++) {
  142. uint pmsk = 0,
  143. ppar = 0,
  144. psor = 0,
  145. pdir = 0,
  146. podr = 0,
  147. pdat = 0;
  148. iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  149. iop_conf_t *eiopc = iopc + 32;
  150. uint msk = 1;
  151. /*
  152. * NOTE:
  153. * index 0 refers to pin 31,
  154. * index 31 refers to pin 0
  155. */
  156. while (iopc < eiopc) {
  157. if (iopc->conf) {
  158. pmsk |= msk;
  159. if (iopc->ppar)
  160. ppar |= msk;
  161. if (iopc->psor)
  162. psor |= msk;
  163. if (iopc->pdir)
  164. pdir |= msk;
  165. if (iopc->podr)
  166. podr |= msk;
  167. if (iopc->pdat)
  168. pdat |= msk;
  169. }
  170. msk <<= 1;
  171. iopc++;
  172. }
  173. if (pmsk != 0) {
  174. volatile ioport_t *iop = ioport_addr (cpm, portnum);
  175. uint tpmsk = ~pmsk;
  176. /*
  177. * the (somewhat confused) paragraph at the
  178. * bottom of page 35-5 warns that there might
  179. * be "unknown behaviour" when programming
  180. * PSORx and PDIRx, if PPARx = 1, so I
  181. * decided this meant I had to disable the
  182. * dedicated function first, and enable it
  183. * last.
  184. */
  185. iop->ppar &= tpmsk;
  186. iop->psor = (iop->psor & tpmsk) | psor;
  187. iop->podr = (iop->podr & tpmsk) | podr;
  188. iop->pdat = (iop->pdat & tpmsk) | pdat;
  189. iop->pdir = (iop->pdir & tpmsk) | pdir;
  190. iop->ppar |= ppar;
  191. }
  192. }
  193. }
  194. #endif
  195. #ifdef CONFIG_SYS_FSL_CPC
  196. #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
  197. void disable_cpc_sram(void)
  198. {
  199. int i;
  200. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  201. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  202. if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
  203. /* find and disable LAW of SRAM */
  204. struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
  205. if (law.index == -1) {
  206. printf("\nFatal error happened\n");
  207. return;
  208. }
  209. disable_law(law.index);
  210. clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
  211. out_be32(&cpc->cpccsr0, 0);
  212. out_be32(&cpc->cpcsrcr0, 0);
  213. }
  214. }
  215. }
  216. #endif
  217. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  218. #ifdef CONFIG_POST
  219. #error POST memory test cannot be enabled with TDM
  220. #endif
  221. static void enable_tdm_law(void)
  222. {
  223. int ret;
  224. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  225. int tdm_hwconfig_enabled = 0;
  226. /*
  227. * Extract hwconfig from environment since environment
  228. * is not setup properly yet. Search for tdm entry in
  229. * hwconfig.
  230. */
  231. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  232. if (ret > 0) {
  233. tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  234. /* If tdm is defined in hwconfig, set law for tdm workaround */
  235. if (tdm_hwconfig_enabled)
  236. set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
  237. LAW_TRGT_IF_CCSR);
  238. }
  239. }
  240. #endif
  241. void enable_cpc(void)
  242. {
  243. int i;
  244. int ret;
  245. u32 size = 0;
  246. u32 cpccfg0;
  247. char buffer[HWCONFIG_BUFFER_SIZE];
  248. char cpc_subarg[16];
  249. bool have_hwconfig = false;
  250. int cpc_args = 0;
  251. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  252. /* Extract hwconfig from environment */
  253. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  254. if (ret > 0) {
  255. /*
  256. * If "en_cpc" is not defined in hwconfig then by default all
  257. * cpcs are enable. If this config is defined then individual
  258. * cpcs which have to be enabled should also be defined.
  259. * e.g en_cpc:cpc1,cpc2;
  260. */
  261. if (hwconfig_f("en_cpc", buffer))
  262. have_hwconfig = true;
  263. }
  264. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  265. if (have_hwconfig) {
  266. sprintf(cpc_subarg, "cpc%u", i + 1);
  267. cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
  268. if (cpc_args == 0)
  269. continue;
  270. }
  271. cpccfg0 = in_be32(&cpc->cpccfg0);
  272. size += CPC_CFG0_SZ_K(cpccfg0);
  273. #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
  274. setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
  275. #endif
  276. #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
  277. setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
  278. #endif
  279. #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
  280. setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
  281. #endif
  282. #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
  283. if (has_erratum_a006379()) {
  284. setbits_be32(&cpc->cpchdbcr0,
  285. CPC_HDBCR0_SPLRU_LEVEL_EN);
  286. }
  287. #endif
  288. out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
  289. /* Read back to sync write */
  290. in_be32(&cpc->cpccsr0);
  291. }
  292. puts("Corenet Platform Cache: ");
  293. print_size(size * 1024, " enabled\n");
  294. }
  295. static void invalidate_cpc(void)
  296. {
  297. int i;
  298. cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
  299. for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
  300. /* skip CPC when it used as all SRAM */
  301. if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
  302. continue;
  303. /* Flash invalidate the CPC and clear all the locks */
  304. out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
  305. while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
  306. ;
  307. }
  308. }
  309. #else
  310. #define enable_cpc()
  311. #define invalidate_cpc()
  312. #define disable_cpc_sram()
  313. #endif /* CONFIG_SYS_FSL_CPC */
  314. /*
  315. * Breathe some life into the CPU...
  316. *
  317. * Set up the memory map
  318. * initialize a bunch of registers
  319. */
  320. #ifdef CONFIG_FSL_CORENET
  321. static void corenet_tb_init(void)
  322. {
  323. volatile ccsr_rcpm_t *rcpm =
  324. (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  325. volatile ccsr_pic_t *pic =
  326. (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  327. u32 whoami = in_be32(&pic->whoami);
  328. /* Enable the timebase register for this core */
  329. out_be32(&rcpm->ctbenrl, (1 << whoami));
  330. }
  331. #endif
  332. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  333. void fsl_erratum_a007212_workaround(void)
  334. {
  335. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  336. u32 ddr_pll_ratio;
  337. u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
  338. u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
  339. u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
  340. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  341. u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
  342. u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
  343. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  344. u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
  345. u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
  346. #endif
  347. #endif
  348. /*
  349. * Even this workaround applies to selected version of SoCs, it is
  350. * safe to apply to all versions, with the limitation of odd ratios.
  351. * If RCW has disabled DDR PLL, we have to apply this workaround,
  352. * otherwise DDR will not work.
  353. */
  354. ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
  355. FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
  356. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  357. /* check if RCW sets ratio to 0, required by this workaround */
  358. if (ddr_pll_ratio != 0)
  359. return;
  360. ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
  361. FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
  362. FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
  363. /* check if reserved bits have the desired ratio */
  364. if (ddr_pll_ratio == 0) {
  365. printf("Error: Unknown DDR PLL ratio!\n");
  366. return;
  367. }
  368. ddr_pll_ratio >>= 1;
  369. setbits_be32(plldadcr1, 0x02000001);
  370. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  371. setbits_be32(plldadcr2, 0x02000001);
  372. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  373. setbits_be32(plldadcr3, 0x02000001);
  374. #endif
  375. #endif
  376. setbits_be32(dpdovrcr4, 0xe0000000);
  377. out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
  378. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  379. out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
  380. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  381. out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
  382. #endif
  383. #endif
  384. udelay(100);
  385. clrbits_be32(plldadcr1, 0x02000001);
  386. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
  387. clrbits_be32(plldadcr2, 0x02000001);
  388. #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
  389. clrbits_be32(plldadcr3, 0x02000001);
  390. #endif
  391. #endif
  392. clrbits_be32(dpdovrcr4, 0xe0000000);
  393. }
  394. #endif
  395. ulong cpu_init_f(void)
  396. {
  397. extern void m8560_cpm_reset (void);
  398. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  399. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  400. #endif
  401. #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
  402. struct law_entry law;
  403. #endif
  404. #ifdef CONFIG_ARCH_MPC8548
  405. ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  406. uint svr = get_svr();
  407. /*
  408. * CPU2 errata workaround: A core hang possible while executing
  409. * a msync instruction and a snoopable transaction from an I/O
  410. * master tagged to make quick forward progress is present.
  411. * Fixed in silicon rev 2.1.
  412. */
  413. if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
  414. out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
  415. #endif
  416. disable_tlb(14);
  417. disable_tlb(15);
  418. #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
  419. /* Disable the LAW created for NOR flash by the PBI commands */
  420. law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
  421. if (law.index != -1)
  422. disable_law(law.index);
  423. #if defined(CONFIG_SYS_CPC_REINIT_F)
  424. disable_cpc_sram();
  425. #endif
  426. #endif
  427. #ifdef CONFIG_CPM2
  428. config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
  429. #endif
  430. init_early_memctl_regs();
  431. #if defined(CONFIG_CPM2)
  432. m8560_cpm_reset();
  433. #endif
  434. #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
  435. /* Config QE ioports */
  436. config_qe_ioports();
  437. #endif
  438. #if defined(CONFIG_FSL_DMA)
  439. dma_init();
  440. #endif
  441. #ifdef CONFIG_FSL_CORENET
  442. corenet_tb_init();
  443. #endif
  444. init_used_tlb_cams();
  445. /* Invalidate the CPC before DDR gets enabled */
  446. invalidate_cpc();
  447. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  448. /* set DCSRCR so that DCSR space is 1G */
  449. setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
  450. in_be32(&gur->dcsrcr);
  451. #endif
  452. #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
  453. fsl_erratum_a007212_workaround();
  454. #endif
  455. return 0;
  456. }
  457. /* Implement a dummy function for those platforms w/o SERDES */
  458. static void __fsl_serdes__init(void)
  459. {
  460. return ;
  461. }
  462. __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
  463. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  464. int enable_cluster_l2(void)
  465. {
  466. int i = 0;
  467. u32 cluster, svr = get_svr();
  468. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  469. struct ccsr_cluster_l2 __iomem *l2cache;
  470. /* only the L2 of first cluster should be enabled as expected on T4080,
  471. * but there is no EOC in the first cluster as HW sake, so return here
  472. * to skip enabling L2 cache of the 2nd cluster.
  473. */
  474. if (SVR_SOC_VER(svr) == SVR_T4080)
  475. return 0;
  476. cluster = in_be32(&gur->tp_cluster[i].lower);
  477. if (cluster & TP_CLUSTER_EOC)
  478. return 0;
  479. /* The first cache has already been set up, so skip it */
  480. i++;
  481. /* Look through the remaining clusters, and set up their caches */
  482. do {
  483. int j, cluster_valid = 0;
  484. l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
  485. cluster = in_be32(&gur->tp_cluster[i].lower);
  486. /* check that at least one core/accel is enabled in cluster */
  487. for (j = 0; j < 4; j++) {
  488. u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
  489. u32 type = in_be32(&gur->tp_ityp[idx]);
  490. if ((type & TP_ITYP_AV) &&
  491. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
  492. cluster_valid = 1;
  493. }
  494. if (cluster_valid) {
  495. /* set stash ID to (cluster) * 2 + 32 + 1 */
  496. clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
  497. printf("enable l2 for cluster %d %p\n", i, l2cache);
  498. out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
  499. while ((in_be32(&l2cache->l2csr0)
  500. & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
  501. ;
  502. out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
  503. }
  504. i++;
  505. } while (!(cluster & TP_CLUSTER_EOC));
  506. return 0;
  507. }
  508. #endif
  509. /*
  510. * Initialize L2 as cache.
  511. */
  512. int l2cache_init(void)
  513. {
  514. __maybe_unused u32 svr = get_svr();
  515. #ifdef CONFIG_L2_CACHE
  516. ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
  517. #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  518. struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
  519. #endif
  520. puts ("L2: ");
  521. #if defined(CONFIG_L2_CACHE)
  522. volatile uint cache_ctl;
  523. uint ver;
  524. u32 l2siz_field;
  525. ver = SVR_SOC_VER(svr);
  526. asm("msync;isync");
  527. cache_ctl = l2cache->l2ctl;
  528. #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  529. if (cache_ctl & MPC85xx_L2CTL_L2E) {
  530. /* Clear L2 SRAM memory-mapped base address */
  531. out_be32(&l2cache->l2srbar0, 0x0);
  532. out_be32(&l2cache->l2srbar1, 0x0);
  533. /* set MBECCDIS=0, SBECCDIS=0 */
  534. clrbits_be32(&l2cache->l2errdis,
  535. (MPC85xx_L2ERRDIS_MBECC |
  536. MPC85xx_L2ERRDIS_SBECC));
  537. /* set L2E=0, L2SRAM=0 */
  538. clrbits_be32(&l2cache->l2ctl,
  539. (MPC85xx_L2CTL_L2E |
  540. MPC85xx_L2CTL_L2SRAM_ENTIRE));
  541. }
  542. #endif
  543. l2siz_field = (cache_ctl >> 28) & 0x3;
  544. switch (l2siz_field) {
  545. case 0x0:
  546. printf(" unknown size (0x%08x)\n", cache_ctl);
  547. return -1;
  548. break;
  549. case 0x1:
  550. if (ver == SVR_8540 || ver == SVR_8560 ||
  551. ver == SVR_8541 || ver == SVR_8555) {
  552. puts("128 KiB ");
  553. /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
  554. cache_ctl = 0xc4000000;
  555. } else {
  556. puts("256 KiB ");
  557. cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
  558. }
  559. break;
  560. case 0x2:
  561. if (ver == SVR_8540 || ver == SVR_8560 ||
  562. ver == SVR_8541 || ver == SVR_8555) {
  563. puts("256 KiB ");
  564. /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
  565. cache_ctl = 0xc8000000;
  566. } else {
  567. puts("512 KiB ");
  568. /* set L2E=1, L2I=1, & L2SRAM=0 */
  569. cache_ctl = 0xc0000000;
  570. }
  571. break;
  572. case 0x3:
  573. puts("1024 KiB ");
  574. /* set L2E=1, L2I=1, & L2SRAM=0 */
  575. cache_ctl = 0xc0000000;
  576. break;
  577. }
  578. if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
  579. puts("already enabled");
  580. #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
  581. u32 l2srbar = l2cache->l2srbar0;
  582. if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
  583. && l2srbar >= CONFIG_SYS_FLASH_BASE) {
  584. l2srbar = CONFIG_SYS_INIT_L2_ADDR;
  585. l2cache->l2srbar0 = l2srbar;
  586. printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
  587. }
  588. #endif /* CONFIG_SYS_INIT_L2_ADDR */
  589. puts("\n");
  590. } else {
  591. asm("msync;isync");
  592. l2cache->l2ctl = cache_ctl; /* invalidate & enable */
  593. asm("msync;isync");
  594. puts("enabled\n");
  595. }
  596. #elif defined(CONFIG_BACKSIDE_L2_CACHE)
  597. if (SVR_SOC_VER(svr) == SVR_P2040) {
  598. puts("N/A\n");
  599. goto skip_l2;
  600. }
  601. u32 l2cfg0 = mfspr(SPRN_L2CFG0);
  602. /* invalidate the L2 cache */
  603. mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
  604. while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
  605. ;
  606. #ifdef CONFIG_SYS_CACHE_STASHING
  607. /* set stash id to (coreID) * 2 + 32 + L2 (1) */
  608. mtspr(SPRN_L2CSR1, (32 + 1));
  609. #endif
  610. /* enable the cache */
  611. mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
  612. if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
  613. while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
  614. ;
  615. print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
  616. }
  617. skip_l2:
  618. #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  619. if (l2cache->l2csr0 & L2CSR0_L2E)
  620. print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
  621. " enabled\n");
  622. enable_cluster_l2();
  623. #else
  624. puts("disabled\n");
  625. #endif
  626. return 0;
  627. }
  628. /*
  629. *
  630. * The newer 8548, etc, parts have twice as much cache, but
  631. * use the same bit-encoding as the older 8555, etc, parts.
  632. *
  633. */
  634. int cpu_init_r(void)
  635. {
  636. __maybe_unused u32 svr = get_svr();
  637. #ifdef CONFIG_SYS_LBC_LCRR
  638. fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
  639. #endif
  640. #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  641. extern int spin_table_compat;
  642. const char *spin;
  643. #endif
  644. #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  645. ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
  646. #endif
  647. #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
  648. defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
  649. /*
  650. * CPU22 and NMG_CPU_A011 share the same workaround.
  651. * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  652. * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
  653. * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
  654. * fixed in 2.0. NMG_CPU_A011 is activated by default and can
  655. * be disabled by hwconfig with syntax:
  656. *
  657. * fsl_cpu_a011:disable
  658. */
  659. extern int enable_cpu_a011_workaround;
  660. #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
  661. enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
  662. #else
  663. char buffer[HWCONFIG_BUFFER_SIZE];
  664. char *buf = NULL;
  665. int n, res;
  666. n = env_get_f("hwconfig", buffer, sizeof(buffer));
  667. if (n > 0)
  668. buf = buffer;
  669. res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
  670. if (res > 0) {
  671. enable_cpu_a011_workaround = 0;
  672. } else {
  673. if (n >= HWCONFIG_BUFFER_SIZE) {
  674. printf("fsl_cpu_a011 was not found. hwconfig variable "
  675. "may be too long\n");
  676. }
  677. enable_cpu_a011_workaround =
  678. (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
  679. (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
  680. }
  681. #endif
  682. if (enable_cpu_a011_workaround) {
  683. flush_dcache();
  684. mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
  685. sync();
  686. }
  687. #endif
  688. #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
  689. flush_dcache();
  690. mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
  691. sync();
  692. #endif
  693. #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
  694. /*
  695. * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
  696. * in write shadow mode. Checking DCWS before setting SPR 976.
  697. */
  698. if (mfspr(L1CSR2) & L1CSR2_DCWS)
  699. mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
  700. #endif
  701. #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
  702. spin = env_get("spin_table_compat");
  703. if (spin && (*spin == 'n'))
  704. spin_table_compat = 0;
  705. else
  706. spin_table_compat = 1;
  707. #endif
  708. #ifdef CONFIG_FSL_CORENET
  709. set_liodns();
  710. #ifdef CONFIG_SYS_DPAA_QBMAN
  711. setup_qbman_portals();
  712. #endif
  713. #endif
  714. l2cache_init();
  715. #if defined(CONFIG_RAMBOOT_PBL)
  716. disable_cpc_sram();
  717. #endif
  718. enable_cpc();
  719. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  720. enable_tdm_law();
  721. #endif
  722. #ifndef CONFIG_SYS_FSL_NO_SERDES
  723. /* needs to be in ram since code uses global static vars */
  724. fsl_serdes_init();
  725. #endif
  726. #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  727. #define MCFGR_AXIPIPE 0x000000f0
  728. if (IS_SVR_REV(svr, 1, 0))
  729. sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
  730. #endif
  731. #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
  732. if (IS_SVR_REV(svr, 1, 0)) {
  733. int i;
  734. __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
  735. for (i = 0; i < 12; i++) {
  736. p += i + (i > 5 ? 11 : 0);
  737. out_be32(p, 0x2);
  738. }
  739. p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
  740. out_be32(p, 0x34);
  741. }
  742. #endif
  743. #ifdef CONFIG_SYS_SRIO
  744. srio_init();
  745. #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
  746. char *s = env_get("bootmaster");
  747. if (s) {
  748. if (!strcmp(s, "SRIO1")) {
  749. srio_boot_master(1);
  750. srio_boot_master_release_slave(1);
  751. }
  752. if (!strcmp(s, "SRIO2")) {
  753. srio_boot_master(2);
  754. srio_boot_master_release_slave(2);
  755. }
  756. }
  757. #endif
  758. #endif
  759. #if defined(CONFIG_MP)
  760. setup_mp();
  761. #endif
  762. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
  763. {
  764. if (SVR_MAJ(svr) < 3) {
  765. void *p;
  766. p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
  767. setbits_be32(p, 1 << (31 - 14));
  768. }
  769. }
  770. #endif
  771. #ifdef CONFIG_SYS_LBC_LCRR
  772. /*
  773. * Modify the CLKDIV field of LCRR register to improve the writing
  774. * speed for NOR flash.
  775. */
  776. clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
  777. __raw_readl(&lbc->lcrr);
  778. isync();
  779. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
  780. udelay(100);
  781. #endif
  782. #endif
  783. #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
  784. {
  785. struct ccsr_usb_phy __iomem *usb_phy1 =
  786. (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  787. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  788. if (has_erratum_a006261())
  789. fsl_erratum_a006261_workaround(usb_phy1);
  790. #endif
  791. out_be32(&usb_phy1->usb_enable_override,
  792. CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
  793. }
  794. #endif
  795. #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
  796. {
  797. struct ccsr_usb_phy __iomem *usb_phy2 =
  798. (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
  799. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  800. if (has_erratum_a006261())
  801. fsl_erratum_a006261_workaround(usb_phy2);
  802. #endif
  803. out_be32(&usb_phy2->usb_enable_override,
  804. CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
  805. }
  806. #endif
  807. #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
  808. /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
  809. * multi-bit ECC errors which has impact on performance, so software
  810. * should disable all ECC reporting from USB1 and USB2.
  811. */
  812. if (IS_SVR_REV(get_svr(), 1, 0)) {
  813. struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
  814. (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
  815. setbits_be32(&dcfg->ecccr1,
  816. (DCSR_DCFG_ECC_DISABLE_USB1 |
  817. DCSR_DCFG_ECC_DISABLE_USB2));
  818. }
  819. #endif
  820. #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
  821. struct ccsr_usb_phy __iomem *usb_phy =
  822. (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  823. setbits_be32(&usb_phy->pllprg[1],
  824. CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
  825. CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
  826. CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
  827. CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
  828. #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  829. usb_single_source_clk_configure(usb_phy);
  830. #endif
  831. setbits_be32(&usb_phy->port1.ctrl,
  832. CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
  833. setbits_be32(&usb_phy->port1.drvvbuscfg,
  834. CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
  835. setbits_be32(&usb_phy->port1.pwrfltcfg,
  836. CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
  837. setbits_be32(&usb_phy->port2.ctrl,
  838. CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
  839. setbits_be32(&usb_phy->port2.drvvbuscfg,
  840. CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
  841. setbits_be32(&usb_phy->port2.pwrfltcfg,
  842. CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
  843. #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  844. if (has_erratum_a006261())
  845. fsl_erratum_a006261_workaround(usb_phy);
  846. #endif
  847. #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
  848. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  849. erratum_a009942_check_cpo();
  850. #endif
  851. #ifdef CONFIG_FMAN_ENET
  852. fman_enet_init();
  853. #endif
  854. #if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
  855. if (pamu_init() < 0)
  856. fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
  857. #endif
  858. #ifdef CONFIG_FSL_CAAM
  859. sec_init();
  860. #if defined(CONFIG_ARCH_C29X)
  861. if ((SVR_SOC_VER(svr) == SVR_C292) ||
  862. (SVR_SOC_VER(svr) == SVR_C293))
  863. sec_init_idx(1);
  864. if (SVR_SOC_VER(svr) == SVR_C293)
  865. sec_init_idx(2);
  866. #endif
  867. #endif
  868. #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
  869. /*
  870. * For P1022/1013 Rev1.0 silicon, after power on SATA host
  871. * controller is configured in legacy mode instead of the
  872. * expected enterprise mode. Software needs to clear bit[28]
  873. * of HControl register to change to enterprise mode from
  874. * legacy mode. We assume that the controller is offline.
  875. */
  876. if (IS_SVR_REV(svr, 1, 0) &&
  877. ((SVR_SOC_VER(svr) == SVR_P1022) ||
  878. (SVR_SOC_VER(svr) == SVR_P1013))) {
  879. fsl_sata_reg_t *reg;
  880. /* first SATA controller */
  881. reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
  882. clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
  883. /* second SATA controller */
  884. reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
  885. clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
  886. }
  887. #endif
  888. init_used_tlb_cams();
  889. return 0;
  890. }
  891. void arch_preboot_os(void)
  892. {
  893. u32 msr;
  894. /*
  895. * We are changing interrupt offsets and are about to boot the OS so
  896. * we need to make sure we disable all async interrupts. EE is already
  897. * disabled by the time we get called.
  898. */
  899. msr = mfmsr();
  900. msr &= ~(MSR_ME|MSR_CE);
  901. mtmsr(msr);
  902. }
  903. void cpu_secondary_init_r(void)
  904. {
  905. #ifdef CONFIG_U_QE
  906. uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
  907. #elif defined CONFIG_QE
  908. uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
  909. #endif
  910. #ifdef CONFIG_QE
  911. qe_init(qe_base);
  912. qe_reset();
  913. #endif
  914. }
  915. #ifdef CONFIG_BOARD_LATE_INIT
  916. int board_late_init(void)
  917. {
  918. #ifdef CONFIG_CHAIN_OF_TRUST
  919. fsl_setenv_chain_of_trust();
  920. #endif
  921. return 0;
  922. }
  923. #endif