cpu.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <time.h>
  8. #include <asm/arch/hardware.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/armv8/mmu.h>
  11. #include <asm/cache.h>
  12. #include <asm/io.h>
  13. #include <zynqmp_firmware.h>
  14. #include <asm/cache.h>
  15. #define ZYNQ_SILICON_VER_MASK 0xF000
  16. #define ZYNQ_SILICON_VER_SHIFT 12
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /*
  19. * Number of filled static entries and also the first empty
  20. * slot in zynqmp_mem_map.
  21. */
  22. #define ZYNQMP_MEM_MAP_USED 4
  23. #if !defined(CONFIG_ZYNQMP_NO_DDR)
  24. #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  25. #else
  26. #define DRAM_BANKS 0
  27. #endif
  28. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  29. #define TCM_MAP 1
  30. #else
  31. #define TCM_MAP 0
  32. #endif
  33. /* +1 is end of list which needs to be empty */
  34. #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  35. static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
  36. {
  37. .virt = 0x80000000UL,
  38. .phys = 0x80000000UL,
  39. .size = 0x70000000UL,
  40. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  41. PTE_BLOCK_NON_SHARE |
  42. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  43. }, {
  44. .virt = 0xf8000000UL,
  45. .phys = 0xf8000000UL,
  46. .size = 0x07e00000UL,
  47. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  48. PTE_BLOCK_NON_SHARE |
  49. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  50. }, {
  51. .virt = 0x400000000UL,
  52. .phys = 0x400000000UL,
  53. .size = 0x400000000UL,
  54. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  55. PTE_BLOCK_NON_SHARE |
  56. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  57. }, {
  58. .virt = 0x1000000000UL,
  59. .phys = 0x1000000000UL,
  60. .size = 0xf000000000UL,
  61. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  62. PTE_BLOCK_NON_SHARE |
  63. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  64. }
  65. };
  66. void mem_map_fill(void)
  67. {
  68. int banks = ZYNQMP_MEM_MAP_USED;
  69. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  70. zynqmp_mem_map[banks].virt = 0xffe00000UL;
  71. zynqmp_mem_map[banks].phys = 0xffe00000UL;
  72. zynqmp_mem_map[banks].size = 0x00200000UL;
  73. zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  74. PTE_BLOCK_INNER_SHARE;
  75. banks = banks + 1;
  76. #endif
  77. #if !defined(CONFIG_ZYNQMP_NO_DDR)
  78. for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  79. /* Zero size means no more DDR that's this is end */
  80. if (!gd->bd->bi_dram[i].size)
  81. break;
  82. zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  83. zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  84. zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  85. zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  86. PTE_BLOCK_INNER_SHARE;
  87. banks = banks + 1;
  88. }
  89. #endif
  90. }
  91. struct mm_region *mem_map = zynqmp_mem_map;
  92. u64 get_page_table_size(void)
  93. {
  94. return 0x14000;
  95. }
  96. #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  97. void tcm_init(u8 mode)
  98. {
  99. puts("WARNING: Initializing TCM overwrites TCM content\n");
  100. initialize_tcm(mode);
  101. memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
  102. }
  103. #endif
  104. #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
  105. int arm_reserve_mmu(void)
  106. {
  107. tcm_init(TCM_LOCK);
  108. gd->arch.tlb_size = PGTABLE_SIZE;
  109. gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
  110. return 0;
  111. }
  112. #endif
  113. static unsigned int zynqmp_get_silicon_version_secure(void)
  114. {
  115. u32 ver;
  116. ver = readl(&csu_base->version);
  117. ver &= ZYNQMP_SILICON_VER_MASK;
  118. ver >>= ZYNQMP_SILICON_VER_SHIFT;
  119. return ver;
  120. }
  121. unsigned int zynqmp_get_silicon_version(void)
  122. {
  123. if (current_el() == 3)
  124. return zynqmp_get_silicon_version_secure();
  125. gd->cpu_clk = get_tbclk();
  126. switch (gd->cpu_clk) {
  127. case 50000000:
  128. return ZYNQMP_CSU_VERSION_QEMU;
  129. }
  130. return ZYNQMP_CSU_VERSION_SILICON;
  131. }
  132. static int zynqmp_mmio_rawwrite(const u32 address,
  133. const u32 mask,
  134. const u32 value)
  135. {
  136. u32 data;
  137. u32 value_local = value;
  138. int ret;
  139. ret = zynqmp_mmio_read(address, &data);
  140. if (ret)
  141. return ret;
  142. data &= ~mask;
  143. value_local &= mask;
  144. value_local |= data;
  145. writel(value_local, (ulong)address);
  146. return 0;
  147. }
  148. static int zynqmp_mmio_rawread(const u32 address, u32 *value)
  149. {
  150. *value = readl((ulong)address);
  151. return 0;
  152. }
  153. int zynqmp_mmio_write(const u32 address,
  154. const u32 mask,
  155. const u32 value)
  156. {
  157. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
  158. return zynqmp_mmio_rawwrite(address, mask, value);
  159. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  160. else
  161. return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
  162. value, 0, NULL);
  163. #endif
  164. return -EINVAL;
  165. }
  166. int zynqmp_mmio_read(const u32 address, u32 *value)
  167. {
  168. u32 ret = -EINVAL;
  169. if (!value)
  170. return ret;
  171. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
  172. ret = zynqmp_mmio_rawread(address, value);
  173. }
  174. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  175. else {
  176. u32 ret_payload[PAYLOAD_ARG_CNT];
  177. ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
  178. 0, ret_payload);
  179. *value = ret_payload[1];
  180. }
  181. #endif
  182. return ret;
  183. }