spl.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <dm.h>
  8. #include <hang.h>
  9. #include <spl.h>
  10. #include <asm/cache.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <linux/libfdt.h>
  14. u32 spl_boot_device(void)
  15. {
  16. u32 boot_mode;
  17. boot_mode = get_bootmode();
  18. switch (boot_mode) {
  19. case BOOT_FLASH_SD_1:
  20. case BOOT_FLASH_EMMC_1:
  21. return BOOT_DEVICE_MMC1;
  22. case BOOT_FLASH_SD_2:
  23. case BOOT_FLASH_EMMC_2:
  24. return BOOT_DEVICE_MMC2;
  25. case BOOT_SERIAL_UART_1:
  26. case BOOT_SERIAL_UART_2:
  27. case BOOT_SERIAL_UART_3:
  28. case BOOT_SERIAL_UART_4:
  29. case BOOT_SERIAL_UART_5:
  30. case BOOT_SERIAL_UART_6:
  31. case BOOT_SERIAL_UART_7:
  32. case BOOT_SERIAL_UART_8:
  33. return BOOT_DEVICE_UART;
  34. case BOOT_SERIAL_USB_OTG:
  35. return BOOT_DEVICE_USB;
  36. case BOOT_FLASH_NAND_FMC:
  37. return BOOT_DEVICE_NAND;
  38. case BOOT_FLASH_NOR_QSPI:
  39. return BOOT_DEVICE_SPI;
  40. case BOOT_FLASH_SPINAND_1:
  41. return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */
  42. }
  43. return BOOT_DEVICE_MMC1;
  44. }
  45. u32 spl_mmc_boot_mode(const u32 boot_device)
  46. {
  47. return MMCSD_MODE_RAW;
  48. }
  49. int spl_mmc_boot_partition(const u32 boot_device)
  50. {
  51. switch (boot_device) {
  52. case BOOT_DEVICE_MMC1:
  53. return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION;
  54. case BOOT_DEVICE_MMC2:
  55. return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2;
  56. default:
  57. return -EINVAL;
  58. }
  59. }
  60. #ifdef CONFIG_SPL_DISPLAY_PRINT
  61. void spl_display_print(void)
  62. {
  63. DECLARE_GLOBAL_DATA_PTR;
  64. const char *model;
  65. /* same code than show_board_info() but not compiled for SPL
  66. * see CONFIG_DISPLAY_BOARDINFO & common/board_info.c
  67. */
  68. model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
  69. if (model)
  70. printf("Model: %s\n", model);
  71. }
  72. #endif
  73. __weak int board_early_init_f(void)
  74. {
  75. return 0;
  76. }
  77. void board_init_f(ulong dummy)
  78. {
  79. struct udevice *dev;
  80. int ret;
  81. arch_cpu_init();
  82. ret = spl_early_init();
  83. if (ret) {
  84. debug("spl_early_init() failed: %d\n", ret);
  85. hang();
  86. }
  87. ret = uclass_get_device(UCLASS_CLK, 0, &dev);
  88. if (ret) {
  89. debug("Clock init failed: %d\n", ret);
  90. hang();
  91. }
  92. ret = uclass_get_device(UCLASS_RESET, 0, &dev);
  93. if (ret) {
  94. debug("Reset init failed: %d\n", ret);
  95. hang();
  96. }
  97. ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev);
  98. if (ret) {
  99. debug("%s: Cannot find pinctrl device\n", __func__);
  100. hang();
  101. }
  102. /* enable console uart printing */
  103. preloader_console_init();
  104. ret = board_early_init_f();
  105. if (ret) {
  106. debug("board_early_init_f() failed: %d\n", ret);
  107. hang();
  108. }
  109. ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  110. if (ret) {
  111. printf("DRAM init failed: %d\n", ret);
  112. hang();
  113. }
  114. /*
  115. * activate cache on DDR only when DDR is fully initialized
  116. * to avoid speculative access and issue in get_ram_size()
  117. */
  118. if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  119. mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
  120. DCACHE_DEFAULT_OPTION);
  121. }
  122. void spl_board_prepare_for_boot(void)
  123. {
  124. dcache_disable();
  125. }
  126. void spl_board_prepare_for_boot_linux(void)
  127. {
  128. dcache_disable();
  129. }