psci.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <config.h>
  6. #include <common.h>
  7. #include <asm/armv7.h>
  8. #include <asm/cache.h>
  9. #include <asm/gic.h>
  10. #include <asm/io.h>
  11. #include <asm/psci.h>
  12. #include <asm/secure.h>
  13. #define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0
  14. #define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1
  15. #define MPIDR_AFF0 GENMASK(7, 0)
  16. #define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
  17. #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
  18. #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
  19. #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
  20. #define STM32MP1_PSCI_NR_CPUS 2
  21. #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
  22. #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
  23. #endif
  24. u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
  25. PSCI_AFFINITY_LEVEL_ON,
  26. PSCI_AFFINITY_LEVEL_OFF};
  27. static u32 __secure_data cntfrq;
  28. static u32 __secure cp15_read_cntfrq(void)
  29. {
  30. u32 frq;
  31. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
  32. return frq;
  33. }
  34. static void __secure cp15_write_cntfrq(u32 frq)
  35. {
  36. asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
  37. }
  38. static inline void psci_set_state(int cpu, u8 state)
  39. {
  40. psci_state[cpu] = state;
  41. dsb();
  42. isb();
  43. }
  44. static u32 __secure stm32mp_get_gicd_base_address(void)
  45. {
  46. u32 periphbase;
  47. /* get the GIC base address from the CBAR register */
  48. asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
  49. return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
  50. }
  51. static void __secure stm32mp_raise_sgi0(int cpu)
  52. {
  53. u32 gic_dist_addr;
  54. gic_dist_addr = stm32mp_get_gicd_base_address();
  55. /* ask cpu with SGI0 */
  56. writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
  57. }
  58. void __secure psci_arch_cpu_entry(void)
  59. {
  60. u32 cpu = psci_get_cpu_id();
  61. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
  62. /* write the saved cntfrq */
  63. cp15_write_cntfrq(cntfrq);
  64. /* reset magic in TAMP register */
  65. writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
  66. }
  67. s32 __secure psci_features(u32 function_id, u32 psci_fid)
  68. {
  69. switch (psci_fid) {
  70. case ARM_PSCI_0_2_FN_PSCI_VERSION:
  71. case ARM_PSCI_0_2_FN_CPU_OFF:
  72. case ARM_PSCI_0_2_FN_CPU_ON:
  73. case ARM_PSCI_0_2_FN_AFFINITY_INFO:
  74. case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
  75. case ARM_PSCI_0_2_FN_SYSTEM_OFF:
  76. case ARM_PSCI_0_2_FN_SYSTEM_RESET:
  77. return 0x0;
  78. }
  79. return ARM_PSCI_RET_NI;
  80. }
  81. u32 __secure psci_version(void)
  82. {
  83. return ARM_PSCI_VER_1_0;
  84. }
  85. s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity,
  86. u32 lowest_affinity_level)
  87. {
  88. u32 cpu = target_affinity & MPIDR_AFF0;
  89. if (lowest_affinity_level > 0)
  90. return ARM_PSCI_RET_INVAL;
  91. if (target_affinity & ~MPIDR_AFF0)
  92. return ARM_PSCI_RET_INVAL;
  93. if (cpu >= STM32MP1_PSCI_NR_CPUS)
  94. return ARM_PSCI_RET_INVAL;
  95. return psci_state[cpu];
  96. }
  97. u32 __secure psci_migrate_info_type(void)
  98. {
  99. /*
  100. * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
  101. * return 2 = Trusted OS is either not present or does not require
  102. * migration, system of this type does not require the caller
  103. * to use the MIGRATE function.
  104. * MIGRATE function calls return NOT_SUPPORTED.
  105. */
  106. return 2;
  107. }
  108. s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
  109. u32 context_id)
  110. {
  111. u32 cpu = target_cpu & MPIDR_AFF0;
  112. if (target_cpu & ~MPIDR_AFF0)
  113. return ARM_PSCI_RET_INVAL;
  114. if (cpu >= STM32MP1_PSCI_NR_CPUS)
  115. return ARM_PSCI_RET_INVAL;
  116. if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
  117. return ARM_PSCI_RET_ALREADY_ON;
  118. /* read and save cntfrq of current cpu to write on target cpu */
  119. cntfrq = cp15_read_cntfrq();
  120. /* reset magic in TAMP register */
  121. if (readl(TAMP_BACKUP_MAGIC_NUMBER))
  122. writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
  123. /*
  124. * ROM code need a first SGI0 after core reset
  125. * core is ready when magic is set to 0 in ROM code
  126. */
  127. while (readl(TAMP_BACKUP_MAGIC_NUMBER))
  128. stm32mp_raise_sgi0(cpu);
  129. /* store target PC and context id*/
  130. psci_save(cpu, pc, context_id);
  131. /* write entrypoint in backup RAM register */
  132. writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
  133. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
  134. /* write magic number in backup register */
  135. if (cpu == 0x01)
  136. writel(BOOT_API_A7_CORE1_MAGIC_NUMBER,
  137. TAMP_BACKUP_MAGIC_NUMBER);
  138. else
  139. writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
  140. TAMP_BACKUP_MAGIC_NUMBER);
  141. /* Generate an IT to start the core */
  142. stm32mp_raise_sgi0(cpu);
  143. return ARM_PSCI_RET_SUCCESS;
  144. }
  145. s32 __secure psci_cpu_off(void)
  146. {
  147. u32 cpu;
  148. cpu = psci_get_cpu_id();
  149. psci_cpu_off_common();
  150. psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
  151. /* reset core: wfi is managed by BootRom */
  152. if (cpu == 0x01)
  153. writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
  154. else
  155. writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
  156. /* just waiting reset */
  157. while (1)
  158. wfi();
  159. }
  160. void __secure psci_system_reset(void)
  161. {
  162. /* System reset */
  163. writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
  164. /* just waiting reset */
  165. while (1)
  166. wfi();
  167. }
  168. void __secure psci_system_off(void)
  169. {
  170. /* System Off is not managed, waiting user power off
  171. * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF
  172. */
  173. while (1)
  174. wfi();
  175. }