cpu.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <debug_uart.h>
  9. #include <env.h>
  10. #include <misc.h>
  11. #include <net.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/stm32.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <dm/device.h>
  16. #include <dm/uclass.h>
  17. /* RCC register */
  18. #define RCC_TZCR (STM32_RCC_BASE + 0x00)
  19. #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
  20. #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
  21. #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
  22. #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
  23. #define RCC_BDCR_VSWRST BIT(31)
  24. #define RCC_BDCR_RTCSRC GENMASK(17, 16)
  25. #define RCC_DBGCFGR_DBGCKEN BIT(8)
  26. /* Security register */
  27. #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
  28. #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
  29. #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
  30. #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
  31. #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
  32. #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
  33. #define PWR_CR1 (STM32_PWR_BASE + 0x00)
  34. #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
  35. #define PWR_CR1_DBP BIT(8)
  36. #define PWR_MCUCR_SBF BIT(6)
  37. /* DBGMCU register */
  38. #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
  39. #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
  40. #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
  41. #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
  42. #define DBGMCU_IDC_DEV_ID_SHIFT 0
  43. #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
  44. #define DBGMCU_IDC_REV_ID_SHIFT 16
  45. /* GPIOZ registers */
  46. #define GPIOZ_SECCFGR 0x54004030
  47. /* boot interface from Bootrom
  48. * - boot instance = bit 31:16
  49. * - boot device = bit 15:0
  50. */
  51. #define BOOTROM_PARAM_ADDR 0x2FFC0078
  52. #define BOOTROM_MODE_MASK GENMASK(15, 0)
  53. #define BOOTROM_MODE_SHIFT 0
  54. #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
  55. #define BOOTROM_INSTANCE_SHIFT 16
  56. /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
  57. #define RPN_SHIFT 0
  58. #define RPN_MASK GENMASK(7, 0)
  59. /* Package = bit 27:29 of OTP16
  60. * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
  61. * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
  62. * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
  63. * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
  64. * - others: Reserved
  65. */
  66. #define PKG_SHIFT 27
  67. #define PKG_MASK GENMASK(2, 0)
  68. /*
  69. * early TLB into the .data section so that it not get cleared
  70. * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
  71. */
  72. u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
  73. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  74. #ifndef CONFIG_TFABOOT
  75. static void security_init(void)
  76. {
  77. /* Disable the backup domain write protection */
  78. /* the protection is enable at each reset by hardware */
  79. /* And must be disable by software */
  80. setbits_le32(PWR_CR1, PWR_CR1_DBP);
  81. while (!(readl(PWR_CR1) & PWR_CR1_DBP))
  82. ;
  83. /* If RTC clock isn't enable so this is a cold boot then we need
  84. * to reset the backup domain
  85. */
  86. if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
  87. setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  88. while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
  89. ;
  90. clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  91. }
  92. /* allow non secure access in Write/Read for all peripheral */
  93. writel(GENMASK(25, 0), ETZPC_DECPROT0);
  94. /* Open SYSRAM for no secure access */
  95. writel(0x0, ETZPC_TZMA1_SIZE);
  96. /* enable TZC1 TZC2 clock */
  97. writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
  98. /* Region 0 set to no access by default */
  99. /* bit 0 / 16 => nsaid0 read/write Enable
  100. * bit 1 / 17 => nsaid1 read/write Enable
  101. * ...
  102. * bit 15 / 31 => nsaid15 read/write Enable
  103. */
  104. writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
  105. /* bit 30 / 31 => Secure Global Enable : write/read */
  106. /* bit 0 / 1 => Region Enable for filter 0/1 */
  107. writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
  108. /* Enable Filter 0 and 1 */
  109. setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
  110. /* RCC trust zone deactivated */
  111. writel(0x0, RCC_TZCR);
  112. /* TAMP: deactivate the internal tamper
  113. * Bit 23 ITAMP8E: monotonic counter overflow
  114. * Bit 20 ITAMP5E: RTC calendar overflow
  115. * Bit 19 ITAMP4E: HSE monitoring
  116. * Bit 18 ITAMP3E: LSE monitoring
  117. * Bit 16 ITAMP1E: RTC power domain supply monitoring
  118. */
  119. writel(0x0, TAMP_CR1);
  120. /* GPIOZ: deactivate the security */
  121. writel(BIT(0), RCC_MP_AHB5ENSETR);
  122. writel(0x0, GPIOZ_SECCFGR);
  123. }
  124. #endif /* CONFIG_TFABOOT */
  125. /*
  126. * Debug init
  127. */
  128. static void dbgmcu_init(void)
  129. {
  130. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  131. /* Freeze IWDG2 if Cortex-A7 is in debug mode */
  132. setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
  133. }
  134. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  135. #if !defined(CONFIG_TFABOOT) && \
  136. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  137. /* get bootmode from ROM code boot context: saved in TAMP register */
  138. static void update_bootmode(void)
  139. {
  140. u32 boot_mode;
  141. u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
  142. u32 bootrom_device, bootrom_instance;
  143. /* enable TAMP clock = RTCAPBEN */
  144. writel(BIT(8), RCC_MP_APB5ENSETR);
  145. /* read bootrom context */
  146. bootrom_device =
  147. (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
  148. bootrom_instance =
  149. (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
  150. boot_mode =
  151. ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
  152. ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
  153. BOOT_INSTANCE_MASK);
  154. /* save the boot mode in TAMP backup register */
  155. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  156. TAMP_BOOT_MODE_MASK,
  157. boot_mode << TAMP_BOOT_MODE_SHIFT);
  158. }
  159. #endif
  160. u32 get_bootmode(void)
  161. {
  162. /* read bootmode from TAMP backup register */
  163. return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
  164. TAMP_BOOT_MODE_SHIFT;
  165. }
  166. /*
  167. * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
  168. * MMU/TLB is updated in enable_caches() for U-Boot after relocation
  169. * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
  170. */
  171. static void early_enable_caches(void)
  172. {
  173. /* I-cache is already enabled in start.S: cpu_init_cp15 */
  174. if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  175. return;
  176. gd->arch.tlb_size = PGTABLE_SIZE;
  177. gd->arch.tlb_addr = (unsigned long)&early_tlb;
  178. dcache_enable();
  179. if (IS_ENABLED(CONFIG_SPL_BUILD))
  180. mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
  181. STM32_SYSRAM_SIZE,
  182. DCACHE_DEFAULT_OPTION);
  183. else
  184. mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
  185. DCACHE_DEFAULT_OPTION);
  186. }
  187. /*
  188. * Early system init
  189. */
  190. int arch_cpu_init(void)
  191. {
  192. u32 boot_mode;
  193. early_enable_caches();
  194. /* early armv7 timer init: needed for polling */
  195. timer_init();
  196. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  197. dbgmcu_init();
  198. #ifndef CONFIG_TFABOOT
  199. security_init();
  200. update_bootmode();
  201. #endif
  202. /* Reset Coprocessor state unless it wakes up from Standby power mode */
  203. if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
  204. writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
  205. writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
  206. }
  207. #endif
  208. boot_mode = get_bootmode();
  209. if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
  210. gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
  211. #if defined(CONFIG_DEBUG_UART) && \
  212. !defined(CONFIG_TFABOOT) && \
  213. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  214. else
  215. debug_uart_init();
  216. #endif
  217. return 0;
  218. }
  219. void enable_caches(void)
  220. {
  221. /* I-cache is already enabled in start.S: icache_enable() not needed */
  222. /* deactivate the data cache, early enabled in arch_cpu_init() */
  223. dcache_disable();
  224. /*
  225. * update MMU after relocation and enable the data cache
  226. * warning: the TLB location udpated in board_f.c::reserve_mmu
  227. */
  228. dcache_enable();
  229. }
  230. static u32 read_idc(void)
  231. {
  232. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  233. return readl(DBGMCU_IDC);
  234. }
  235. u32 get_cpu_dev(void)
  236. {
  237. return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
  238. }
  239. u32 get_cpu_rev(void)
  240. {
  241. return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
  242. }
  243. static u32 get_otp(int index, int shift, int mask)
  244. {
  245. int ret;
  246. struct udevice *dev;
  247. u32 otp = 0;
  248. ret = uclass_get_device_by_driver(UCLASS_MISC,
  249. DM_GET_DRIVER(stm32mp_bsec),
  250. &dev);
  251. if (!ret)
  252. ret = misc_read(dev, STM32_BSEC_SHADOW(index),
  253. &otp, sizeof(otp));
  254. return (otp >> shift) & mask;
  255. }
  256. /* Get Device Part Number (RPN) from OTP */
  257. static u32 get_cpu_rpn(void)
  258. {
  259. return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
  260. }
  261. u32 get_cpu_type(void)
  262. {
  263. return (get_cpu_dev() << 16) | get_cpu_rpn();
  264. }
  265. /* Get Package options from OTP */
  266. u32 get_cpu_package(void)
  267. {
  268. return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
  269. }
  270. void get_soc_name(char name[SOC_NAME_SIZE])
  271. {
  272. char *cpu_s, *cpu_r, *pkg;
  273. /* MPUs Part Numbers */
  274. switch (get_cpu_type()) {
  275. case CPU_STM32MP157Fxx:
  276. cpu_s = "157F";
  277. break;
  278. case CPU_STM32MP157Dxx:
  279. cpu_s = "157D";
  280. break;
  281. case CPU_STM32MP157Cxx:
  282. cpu_s = "157C";
  283. break;
  284. case CPU_STM32MP157Axx:
  285. cpu_s = "157A";
  286. break;
  287. case CPU_STM32MP153Fxx:
  288. cpu_s = "153F";
  289. break;
  290. case CPU_STM32MP153Dxx:
  291. cpu_s = "153D";
  292. break;
  293. case CPU_STM32MP153Cxx:
  294. cpu_s = "153C";
  295. break;
  296. case CPU_STM32MP153Axx:
  297. cpu_s = "153A";
  298. break;
  299. case CPU_STM32MP151Fxx:
  300. cpu_s = "151F";
  301. break;
  302. case CPU_STM32MP151Dxx:
  303. cpu_s = "151D";
  304. break;
  305. case CPU_STM32MP151Cxx:
  306. cpu_s = "151C";
  307. break;
  308. case CPU_STM32MP151Axx:
  309. cpu_s = "151A";
  310. break;
  311. default:
  312. cpu_s = "????";
  313. break;
  314. }
  315. /* Package */
  316. switch (get_cpu_package()) {
  317. case PKG_AA_LBGA448:
  318. pkg = "AA";
  319. break;
  320. case PKG_AB_LBGA354:
  321. pkg = "AB";
  322. break;
  323. case PKG_AC_TFBGA361:
  324. pkg = "AC";
  325. break;
  326. case PKG_AD_TFBGA257:
  327. pkg = "AD";
  328. break;
  329. default:
  330. pkg = "??";
  331. break;
  332. }
  333. /* REVISION */
  334. switch (get_cpu_rev()) {
  335. case CPU_REVA:
  336. cpu_r = "A";
  337. break;
  338. case CPU_REVB:
  339. cpu_r = "B";
  340. break;
  341. case CPU_REVZ:
  342. cpu_r = "Z";
  343. break;
  344. default:
  345. cpu_r = "?";
  346. break;
  347. }
  348. snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
  349. }
  350. #if defined(CONFIG_DISPLAY_CPUINFO)
  351. int print_cpuinfo(void)
  352. {
  353. char name[SOC_NAME_SIZE];
  354. get_soc_name(name);
  355. printf("CPU: %s\n", name);
  356. return 0;
  357. }
  358. #endif /* CONFIG_DISPLAY_CPUINFO */
  359. static void setup_boot_mode(void)
  360. {
  361. const u32 serial_addr[] = {
  362. STM32_USART1_BASE,
  363. STM32_USART2_BASE,
  364. STM32_USART3_BASE,
  365. STM32_UART4_BASE,
  366. STM32_UART5_BASE,
  367. STM32_USART6_BASE,
  368. STM32_UART7_BASE,
  369. STM32_UART8_BASE
  370. };
  371. char cmd[60];
  372. u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
  373. u32 boot_mode =
  374. (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
  375. unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
  376. u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
  377. struct udevice *dev;
  378. int alias;
  379. pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
  380. __func__, boot_ctx, boot_mode, instance, forced_mode);
  381. switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
  382. case BOOT_SERIAL_UART:
  383. if (instance > ARRAY_SIZE(serial_addr))
  384. break;
  385. /* serial : search associated alias in devicetree */
  386. sprintf(cmd, "serial@%x", serial_addr[instance]);
  387. if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
  388. break;
  389. if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
  390. dev_of_offset(dev), &alias))
  391. break;
  392. sprintf(cmd, "%d", alias);
  393. env_set("boot_device", "serial");
  394. env_set("boot_instance", cmd);
  395. /* restore console on uart when not used */
  396. if (gd->cur_serial_dev != dev) {
  397. gd->flags &= ~(GD_FLG_SILENT |
  398. GD_FLG_DISABLE_CONSOLE);
  399. printf("serial boot with console enabled!\n");
  400. }
  401. break;
  402. case BOOT_SERIAL_USB:
  403. env_set("boot_device", "usb");
  404. env_set("boot_instance", "0");
  405. break;
  406. case BOOT_FLASH_SD:
  407. case BOOT_FLASH_EMMC:
  408. sprintf(cmd, "%d", instance);
  409. env_set("boot_device", "mmc");
  410. env_set("boot_instance", cmd);
  411. break;
  412. case BOOT_FLASH_NAND:
  413. env_set("boot_device", "nand");
  414. env_set("boot_instance", "0");
  415. break;
  416. case BOOT_FLASH_SPINAND:
  417. env_set("boot_device", "spi-nand");
  418. env_set("boot_instance", "0");
  419. break;
  420. case BOOT_FLASH_NOR:
  421. env_set("boot_device", "nor");
  422. env_set("boot_instance", "0");
  423. break;
  424. default:
  425. pr_debug("unexpected boot mode = %x\n", boot_mode);
  426. break;
  427. }
  428. switch (forced_mode) {
  429. case BOOT_FASTBOOT:
  430. printf("Enter fastboot!\n");
  431. env_set("preboot", "env set preboot; fastboot 0");
  432. break;
  433. case BOOT_STM32PROG:
  434. env_set("boot_device", "usb");
  435. env_set("boot_instance", "0");
  436. break;
  437. case BOOT_UMS_MMC0:
  438. case BOOT_UMS_MMC1:
  439. case BOOT_UMS_MMC2:
  440. printf("Enter UMS!\n");
  441. instance = forced_mode - BOOT_UMS_MMC0;
  442. sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
  443. env_set("preboot", cmd);
  444. break;
  445. case BOOT_RECOVERY:
  446. env_set("preboot", "env set preboot; run altbootcmd");
  447. break;
  448. case BOOT_NORMAL:
  449. break;
  450. default:
  451. pr_debug("unexpected forced boot mode = %x\n", forced_mode);
  452. break;
  453. }
  454. /* clear TAMP for next reboot */
  455. clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
  456. }
  457. /*
  458. * If there is no MAC address in the environment, then it will be initialized
  459. * (silently) from the value in the OTP.
  460. */
  461. __weak int setup_mac_address(void)
  462. {
  463. #if defined(CONFIG_NET)
  464. int ret;
  465. int i;
  466. u32 otp[2];
  467. uchar enetaddr[6];
  468. struct udevice *dev;
  469. /* MAC already in environment */
  470. if (eth_env_get_enetaddr("ethaddr", enetaddr))
  471. return 0;
  472. ret = uclass_get_device_by_driver(UCLASS_MISC,
  473. DM_GET_DRIVER(stm32mp_bsec),
  474. &dev);
  475. if (ret)
  476. return ret;
  477. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
  478. otp, sizeof(otp));
  479. if (ret < 0)
  480. return ret;
  481. for (i = 0; i < 6; i++)
  482. enetaddr[i] = ((uint8_t *)&otp)[i];
  483. if (!is_valid_ethaddr(enetaddr)) {
  484. pr_err("invalid MAC address in OTP %pM\n", enetaddr);
  485. return -EINVAL;
  486. }
  487. pr_debug("OTP MAC address = %pM\n", enetaddr);
  488. ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
  489. if (!ret)
  490. pr_err("Failed to set mac address %pM from OTP: %d\n",
  491. enetaddr, ret);
  492. #endif
  493. return 0;
  494. }
  495. static int setup_serial_number(void)
  496. {
  497. char serial_string[25];
  498. u32 otp[3] = {0, 0, 0 };
  499. struct udevice *dev;
  500. int ret;
  501. if (env_get("serial#"))
  502. return 0;
  503. ret = uclass_get_device_by_driver(UCLASS_MISC,
  504. DM_GET_DRIVER(stm32mp_bsec),
  505. &dev);
  506. if (ret)
  507. return ret;
  508. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
  509. otp, sizeof(otp));
  510. if (ret < 0)
  511. return ret;
  512. sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
  513. env_set("serial#", serial_string);
  514. return 0;
  515. }
  516. int arch_misc_init(void)
  517. {
  518. setup_boot_mode();
  519. setup_mac_address();
  520. setup_serial_number();
  521. return 0;
  522. }