misc.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <hang.h>
  8. #include <asm/cache.h>
  9. #include <asm/io.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <linux/libfdt.h>
  13. #include <altera.h>
  14. #include <miiphy.h>
  15. #include <netdev.h>
  16. #include <watchdog.h>
  17. #include <asm/arch/misc.h>
  18. #include <asm/arch/reset_manager.h>
  19. #include <asm/arch/scan_manager.h>
  20. #include <asm/arch/system_manager.h>
  21. #include <asm/arch/nic301.h>
  22. #include <asm/arch/scu.h>
  23. #include <asm/pl310.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. phys_addr_t socfpga_clkmgr_base __section(".data");
  26. phys_addr_t socfpga_rstmgr_base __section(".data");
  27. phys_addr_t socfpga_sysmgr_base __section(".data");
  28. #ifdef CONFIG_SYS_L2_PL310
  29. static const struct pl310_regs *const pl310 =
  30. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  31. #endif
  32. struct bsel bsel_str[] = {
  33. { "rsvd", "Reserved", },
  34. { "fpga", "FPGA (HPS2FPGA Bridge)", },
  35. { "nand", "NAND Flash (1.8V)", },
  36. { "nand", "NAND Flash (3.0V)", },
  37. { "sd", "SD/MMC External Transceiver (1.8V)", },
  38. { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  39. { "qspi", "QSPI Flash (1.8V)", },
  40. { "qspi", "QSPI Flash (3.0V)", },
  41. };
  42. int dram_init(void)
  43. {
  44. if (fdtdec_setup_mem_size_base() != 0)
  45. return -EINVAL;
  46. return 0;
  47. }
  48. void enable_caches(void)
  49. {
  50. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  51. icache_enable();
  52. #endif
  53. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  54. dcache_enable();
  55. #endif
  56. }
  57. #ifdef CONFIG_SYS_L2_PL310
  58. void v7_outer_cache_enable(void)
  59. {
  60. struct udevice *dev;
  61. if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  62. pr_err("cache controller driver NOT found!\n");
  63. }
  64. void v7_outer_cache_disable(void)
  65. {
  66. /* Disable the L2 cache */
  67. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  68. }
  69. void socfpga_pl310_clear(void)
  70. {
  71. u32 mask = 0xff, ena = 0;
  72. icache_enable();
  73. /* Disable the L2 cache */
  74. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  75. writel(0x0, &pl310->pl310_tag_latency_ctrl);
  76. writel(0x10, &pl310->pl310_data_latency_ctrl);
  77. /* enable BRESP, instruction and data prefetch, full line of zeroes */
  78. setbits_le32(&pl310->pl310_aux_ctrl,
  79. L310_AUX_CTRL_DATA_PREFETCH_MASK |
  80. L310_AUX_CTRL_INST_PREFETCH_MASK |
  81. L310_SHARED_ATT_OVERRIDE_ENABLE);
  82. /* Enable the L2 cache */
  83. ena = readl(&pl310->pl310_ctrl);
  84. ena |= L2X0_CTRL_EN;
  85. /*
  86. * Invalidate the PL310 L2 cache. Keep the invalidation code
  87. * entirely in L1 I-cache to avoid any bus traffic through
  88. * the L2.
  89. */
  90. asm volatile(
  91. ".align 5 \n"
  92. " b 3f \n"
  93. "1: str %1, [%4] \n"
  94. " dsb \n"
  95. " isb \n"
  96. " str %0, [%2] \n"
  97. " dsb \n"
  98. " isb \n"
  99. "2: ldr %0, [%2] \n"
  100. " cmp %0, #0 \n"
  101. " bne 2b \n"
  102. " str %0, [%3] \n"
  103. " dsb \n"
  104. " isb \n"
  105. " b 4f \n"
  106. "3: b 1b \n"
  107. "4: nop \n"
  108. : "+r"(mask), "+r"(ena)
  109. : "r"(&pl310->pl310_inv_way),
  110. "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
  111. : "memory", "cc");
  112. /* Disable the L2 cache */
  113. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  114. }
  115. #endif
  116. #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  117. defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  118. int overwrite_console(void)
  119. {
  120. return 0;
  121. }
  122. #endif
  123. #ifdef CONFIG_FPGA
  124. /* add device descriptor to FPGA device table */
  125. void socfpga_fpga_add(void *fpga_desc)
  126. {
  127. fpga_init();
  128. fpga_add(fpga_altera, fpga_desc);
  129. }
  130. #endif
  131. int arch_cpu_init(void)
  132. {
  133. socfpga_get_managers_addr();
  134. #ifdef CONFIG_HW_WATCHDOG
  135. /*
  136. * In case the watchdog is enabled, make sure to (re-)configure it
  137. * so that the defined timeout is valid. Otherwise the SPL (Perloader)
  138. * timeout value is still active which might too short for Linux
  139. * booting.
  140. */
  141. hw_watchdog_init();
  142. #else
  143. /*
  144. * If the HW watchdog is NOT enabled, make sure it is not running,
  145. * for example because it was enabled in the preloader. This might
  146. * trigger a watchdog-triggered reboot of Linux kernel later.
  147. * Toggle watchdog reset, so watchdog in not running state.
  148. */
  149. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  150. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  151. #endif
  152. return 0;
  153. }
  154. #ifndef CONFIG_SPL_BUILD
  155. static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  156. {
  157. unsigned int mask = ~0;
  158. if (argc < 2 || argc > 3)
  159. return CMD_RET_USAGE;
  160. argv++;
  161. if (argc == 3)
  162. mask = simple_strtoul(argv[1], NULL, 16);
  163. switch (*argv[0]) {
  164. case 'e': /* Enable */
  165. do_bridge_reset(1, mask);
  166. break;
  167. case 'd': /* Disable */
  168. do_bridge_reset(0, mask);
  169. break;
  170. default:
  171. return CMD_RET_USAGE;
  172. }
  173. return 0;
  174. }
  175. U_BOOT_CMD(bridge, 3, 1, do_bridge,
  176. "SoCFPGA HPS FPGA bridge control",
  177. "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  178. "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  179. ""
  180. );
  181. #endif
  182. static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
  183. {
  184. const void *blob = gd->fdt_blob;
  185. struct fdt_resource r;
  186. int node;
  187. int ret;
  188. node = fdt_node_offset_by_compatible(blob, -1, compat);
  189. if (node < 0)
  190. return node;
  191. if (!fdtdec_get_is_enabled(blob, node))
  192. return -ENODEV;
  193. ret = fdt_get_resource(blob, node, "reg", 0, &r);
  194. if (ret)
  195. return ret;
  196. *base = (phys_addr_t)r.start;
  197. return 0;
  198. }
  199. void socfpga_get_managers_addr(void)
  200. {
  201. int ret;
  202. ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
  203. if (ret)
  204. hang();
  205. ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
  206. if (ret)
  207. hang();
  208. #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
  209. ret = socfpga_get_base_addr("intel,agilex-clkmgr",
  210. &socfpga_clkmgr_base);
  211. #else
  212. ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
  213. #endif
  214. if (ret)
  215. hang();
  216. }
  217. phys_addr_t socfpga_get_rstmgr_addr(void)
  218. {
  219. return socfpga_rstmgr_base;
  220. }
  221. phys_addr_t socfpga_get_sysmgr_addr(void)
  222. {
  223. return socfpga_sysmgr_base;
  224. }
  225. phys_addr_t socfpga_get_clkmgr_addr(void)
  226. {
  227. return socfpga_clkmgr_base;
  228. }