init.c 2.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Copyright (C) 2019 BayLibre, SAS
  5. * Author: Fabien Parent <fparent@baylibre.com>
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <ram.h>
  13. #include <asm/arch/misc.h>
  14. #include <asm/armv8/mmu.h>
  15. #include <asm/cache.h>
  16. #include <asm/sections.h>
  17. #include <dm/uclass.h>
  18. #include <dt-bindings/clock/mt8516-clk.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. int dram_init(void)
  21. {
  22. int ret;
  23. ret = fdtdec_setup_memory_banksize();
  24. if (ret)
  25. return ret;
  26. return fdtdec_setup_mem_size_base();
  27. }
  28. int dram_init_banksize(void)
  29. {
  30. gd->bd->bi_dram[0].start = gd->ram_base;
  31. gd->bd->bi_dram[0].size = gd->ram_size;
  32. return 0;
  33. }
  34. int mtk_pll_early_init(void)
  35. {
  36. unsigned long pll_rates[] = {
  37. [CLK_APMIXED_ARMPLL] = 1300000000,
  38. [CLK_APMIXED_MAINPLL] = 1501000000,
  39. [CLK_APMIXED_UNIVPLL] = 1248000000,
  40. [CLK_APMIXED_MMPLL] = 380000000,
  41. };
  42. struct udevice *dev;
  43. int ret, i;
  44. ret = uclass_get_device_by_driver(UCLASS_CLK,
  45. DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
  46. if (ret)
  47. return ret;
  48. /* configure default rate then enable apmixedsys */
  49. for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
  50. struct clk clk = { .id = i, .dev = dev };
  51. ret = clk_set_rate(&clk, pll_rates[i]);
  52. if (ret)
  53. return ret;
  54. ret = clk_enable(&clk);
  55. if (ret)
  56. return ret;
  57. }
  58. return 0;
  59. }
  60. int mtk_soc_early_init(void)
  61. {
  62. int ret;
  63. /* initialize early clocks */
  64. ret = mtk_pll_early_init();
  65. if (ret)
  66. return ret;
  67. return 0;
  68. }
  69. void reset_cpu(ulong addr)
  70. {
  71. psci_system_reset();
  72. }
  73. int print_cpuinfo(void)
  74. {
  75. printf("CPU: MediaTek MT8516\n");
  76. return 0;
  77. }
  78. static struct mm_region mt8516_mem_map[] = {
  79. {
  80. /* DDR */
  81. .virt = 0x40000000UL,
  82. .phys = 0x40000000UL,
  83. .size = 0x20000000UL,
  84. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
  85. }, {
  86. .virt = 0x00000000UL,
  87. .phys = 0x00000000UL,
  88. .size = 0x20000000UL,
  89. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  90. PTE_BLOCK_NON_SHARE |
  91. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  92. }, {
  93. 0,
  94. }
  95. };
  96. struct mm_region *mem_map = mt8516_mem_map;