cpu.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <cpu_func.h>
  10. #include <env.h>
  11. #include <net.h>
  12. #include <netdev.h>
  13. #include <asm/cache.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/soc.h>
  17. #include <mvebu_mmc.h>
  18. void reset_cpu(unsigned long ignored)
  19. {
  20. struct kwcpu_registers *cpureg =
  21. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  22. writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  23. &cpureg->rstoutn_mask);
  24. writel(readl(&cpureg->sys_soft_rst) | 1,
  25. &cpureg->sys_soft_rst);
  26. while (1) ;
  27. }
  28. /*
  29. * Window Size
  30. * Used with the Base register to set the address window size and location.
  31. * Must be programmed from LSB to MSB as sequence of ones followed by
  32. * sequence of zeros. The number of ones specifies the size of the window in
  33. * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
  34. * NOTE: A value of 0x0 specifies 64-KByte size.
  35. */
  36. unsigned int kw_winctrl_calcsize(unsigned int sizeval)
  37. {
  38. int i;
  39. unsigned int j = 0;
  40. u32 val = sizeval >> 1;
  41. for (i = 0; val >= 0x10000; i++) {
  42. j |= (1 << i);
  43. val = val >> 1;
  44. }
  45. return (0x0000ffff & j);
  46. }
  47. static struct mbus_win windows[] = {
  48. /* Window 0: PCIE MEM address space */
  49. { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
  50. KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
  51. /* Window 1: PCIE IO address space */
  52. { KW_DEFADR_PCI_IO, 1024 * 64,
  53. KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
  54. /* Window 2: NAND Flash address space */
  55. { KW_DEFADR_NANDF, 1024 * 1024 * 128,
  56. KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
  57. /* Window 3: SPI Flash address space */
  58. { KW_DEFADR_SPIF, 1024 * 1024 * 128,
  59. KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
  60. /* Window 4: BOOT Memory address space */
  61. { KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
  62. KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
  63. /* Window 5: Security SRAM address space */
  64. { KW_DEFADR_SASRAM, 1024 * 64,
  65. KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
  66. };
  67. /*
  68. * SYSRSTn Duration Counter Support
  69. *
  70. * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
  71. * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
  72. * The SYSRSTn duration counter is useful for implementing a manufacturer
  73. * or factory reset. Upon a long reset assertion that is greater than a
  74. * pre-configured environment variable value for sysrstdelay,
  75. * The counter value is stored in the SYSRSTn Length Counter Register
  76. * The counter is based on the 25-MHz reference clock (40ns)
  77. * It is a 29-bit counter, yielding a maximum counting duration of
  78. * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
  79. * it remains at this value until counter reset is triggered by setting
  80. * bit 31 of KW_REG_SYSRST_CNT
  81. */
  82. static void kw_sysrst_action(void)
  83. {
  84. int ret;
  85. char *s = env_get("sysrstcmd");
  86. if (!s) {
  87. debug("Error.. %s failed, check sysrstcmd\n",
  88. __FUNCTION__);
  89. return;
  90. }
  91. debug("Starting %s process...\n", __FUNCTION__);
  92. ret = run_command(s, 0);
  93. if (ret != 0)
  94. debug("Error.. %s failed\n", __FUNCTION__);
  95. else
  96. debug("%s process finished\n", __FUNCTION__);
  97. }
  98. static void kw_sysrst_check(void)
  99. {
  100. u32 sysrst_cnt, sysrst_dly;
  101. char *s;
  102. /*
  103. * no action if sysrstdelay environment variable is not defined
  104. */
  105. s = env_get("sysrstdelay");
  106. if (s == NULL)
  107. return;
  108. /* read sysrstdelay value */
  109. sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
  110. /* read SysRst Length counter register (bits 28:0) */
  111. sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
  112. debug("H/w Rst hold time: %d.%d secs\n",
  113. sysrst_cnt / SYSRST_CNT_1SEC_VAL,
  114. sysrst_cnt % SYSRST_CNT_1SEC_VAL);
  115. /* clear the counter for next valid read*/
  116. writel(1 << 31, KW_REG_SYSRST_CNT);
  117. /*
  118. * sysrst_action:
  119. * if H/w Reset key is pressed and hold for time
  120. * more than sysrst_dly in seconds
  121. */
  122. if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
  123. kw_sysrst_action();
  124. }
  125. #if defined(CONFIG_DISPLAY_CPUINFO)
  126. int print_cpuinfo(void)
  127. {
  128. char *rev = "??";
  129. u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
  130. u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
  131. if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
  132. printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
  133. return -1;
  134. }
  135. switch (revid) {
  136. case 0:
  137. if (devid == 0x6281)
  138. rev = "Z0";
  139. else if (devid == 0x6282)
  140. rev = "A0";
  141. break;
  142. case 1:
  143. rev = "A1";
  144. break;
  145. case 2:
  146. rev = "A0";
  147. break;
  148. case 3:
  149. rev = "A1";
  150. break;
  151. default:
  152. break;
  153. }
  154. printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
  155. return 0;
  156. }
  157. #endif /* CONFIG_DISPLAY_CPUINFO */
  158. #ifdef CONFIG_ARCH_CPU_INIT
  159. int arch_cpu_init(void)
  160. {
  161. u32 reg;
  162. struct kwcpu_registers *cpureg =
  163. (struct kwcpu_registers *)KW_CPU_REG_BASE;
  164. /* Linux expects the internal registers to be at 0xf1000000 */
  165. writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
  166. /* Enable and invalidate L2 cache in write through mode */
  167. writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
  168. invalidate_l2_cache();
  169. #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
  170. /*
  171. * Configures the I/O voltage of the pads connected to Egigabit
  172. * Ethernet interface to 1.8V
  173. * By default it is set to 3.3V
  174. */
  175. reg = readl(KW_REG_MPP_OUT_DRV_REG);
  176. reg |= (1 << 7);
  177. writel(reg, KW_REG_MPP_OUT_DRV_REG);
  178. #endif
  179. #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
  180. /*
  181. * Set egiga port0/1 in normal functional mode
  182. * This is required becasue on kirkwood by default ports are in reset mode
  183. * OS egiga driver may not have provision to set them in normal mode
  184. * and if u-boot is build without network support, network may fail at OS level
  185. */
  186. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
  187. reg &= ~(1 << 4); /* Clear PortReset Bit */
  188. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
  189. reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
  190. reg &= ~(1 << 4); /* Clear PortReset Bit */
  191. writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
  192. #endif
  193. #ifdef CONFIG_KIRKWOOD_PCIE_INIT
  194. /*
  195. * Enable PCI Express Port0
  196. */
  197. reg = readl(&cpureg->ctrl_stat);
  198. reg |= (1 << 0); /* Set PEX0En Bit */
  199. writel(reg, &cpureg->ctrl_stat);
  200. #endif
  201. return 0;
  202. }
  203. #endif /* CONFIG_ARCH_CPU_INIT */
  204. /*
  205. * SOC specific misc init
  206. */
  207. #if defined(CONFIG_ARCH_MISC_INIT)
  208. int arch_misc_init(void)
  209. {
  210. volatile u32 temp;
  211. /*CPU streaming & write allocate */
  212. temp = readfr_extra_feature_reg();
  213. temp &= ~(1 << 28); /* disable wr alloc */
  214. writefr_extra_feature_reg(temp);
  215. temp = readfr_extra_feature_reg();
  216. temp &= ~(1 << 29); /* streaming disabled */
  217. writefr_extra_feature_reg(temp);
  218. /* L2Cache settings */
  219. temp = readfr_extra_feature_reg();
  220. /* Disable L2C pre fetch - Set bit 24 */
  221. temp |= (1 << 24);
  222. /* enable L2C - Set bit 22 */
  223. temp |= (1 << 22);
  224. writefr_extra_feature_reg(temp);
  225. /* Change reset vector to address 0x0 */
  226. temp = get_cr();
  227. set_cr(temp & ~CR_V);
  228. /* Configure mbus windows */
  229. mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  230. /* checks and execute resset to factory event */
  231. kw_sysrst_check();
  232. return 0;
  233. }
  234. #endif /* CONFIG_ARCH_MISC_INIT */
  235. #ifdef CONFIG_MVGBE
  236. int cpu_eth_init(bd_t *bis)
  237. {
  238. mvgbe_initialize(bis);
  239. return 0;
  240. }
  241. #endif
  242. #ifdef CONFIG_MVEBU_MMC
  243. int board_mmc_init(bd_t *bis)
  244. {
  245. mvebu_mmc_init(bis);
  246. return 0;
  247. }
  248. #endif /* CONFIG_MVEBU_MMC */