init.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone2: Architecture initialization
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <ns16550.h>
  11. #include <asm/cache.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/msmc.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/psc_defs.h>
  17. #define MAX_PCI_PORTS 2
  18. enum pci_mode {
  19. ENDPOINT,
  20. LEGACY_ENDPOINT,
  21. ROOTCOMPLEX,
  22. };
  23. #define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
  24. #define DEVCFG_MODE_SHIFT 1
  25. void chip_configuration_unlock(void)
  26. {
  27. __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  28. __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  29. }
  30. #ifdef CONFIG_SOC_K2L
  31. void osr_init(void)
  32. {
  33. u32 i;
  34. u32 j;
  35. u32 val;
  36. u32 base = KS2_OSR_CFG_BASE;
  37. u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
  38. /* Enable the OSR clock domain */
  39. psc_enable_module(KS2_LPSC_OSR);
  40. /* Disable OSR ECC check for all the ram banks */
  41. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
  42. val = i | KS2_OSR_ECC_VEC_TRIG_RD |
  43. (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
  44. writel(val , base + KS2_OSR_ECC_VEC);
  45. /**
  46. * wait till read is done.
  47. * Print should be added after earlyprintk support is added.
  48. */
  49. for (j = 0; j < 10000; j++) {
  50. val = readl(base + KS2_OSR_ECC_VEC);
  51. if (val & KS2_OSR_ECC_VEC_RD_DONE)
  52. break;
  53. }
  54. ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
  55. KS2_OSR_ECC_CTRL_CHK;
  56. writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
  57. writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
  58. }
  59. /* Reset OSR memory to all zeros */
  60. for (i = 0; i < KS2_OSR_SIZE; i += 4)
  61. writel(0, KS2_OSR_DATA_BASE + i);
  62. /* Enable OSR ECC check for all the ram banks */
  63. for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
  64. writel(ecc_ctrl[i] |
  65. KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
  66. }
  67. #endif
  68. /* Function to set up PCIe mode */
  69. static void config_pcie_mode(int pcie_port, enum pci_mode mode)
  70. {
  71. u32 val = __raw_readl(KS2_DEVCFG);
  72. if (pcie_port >= MAX_PCI_PORTS)
  73. return;
  74. /**
  75. * each pci port has two bits for mode and it starts at
  76. * bit 1. So use port number to get the right bit position.
  77. */
  78. pcie_port <<= 1;
  79. val &= ~(DEVCFG_MODE_MASK << pcie_port);
  80. val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
  81. __raw_writel(val, KS2_DEVCFG);
  82. }
  83. static void msmc_k2hkle_common_setup(void)
  84. {
  85. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  86. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
  87. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
  88. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
  89. msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
  90. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  91. }
  92. static void msmc_k2hk_setup(void)
  93. {
  94. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  95. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  96. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  97. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
  98. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
  99. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
  100. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
  101. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  102. }
  103. static inline void msmc_k2l_setup(void)
  104. {
  105. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
  106. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
  107. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
  108. msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
  109. }
  110. static inline void msmc_k2e_setup(void)
  111. {
  112. msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
  113. msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
  114. msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
  115. }
  116. static void msmc_k2g_setup(void)
  117. {
  118. msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
  119. msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
  120. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
  121. msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
  122. msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
  123. msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
  124. msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
  125. msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
  126. msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
  127. msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
  128. msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
  129. msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
  130. }
  131. int arch_cpu_init(void)
  132. {
  133. chip_configuration_unlock();
  134. icache_enable();
  135. if (cpu_is_k2g()) {
  136. msmc_k2g_setup();
  137. } else {
  138. msmc_k2hkle_common_setup();
  139. if (cpu_is_k2e())
  140. msmc_k2e_setup();
  141. else if (cpu_is_k2l())
  142. msmc_k2l_setup();
  143. else
  144. msmc_k2hk_setup();
  145. }
  146. /* Initialize the PCIe-0 to work as Root Complex */
  147. config_pcie_mode(0, ROOTCOMPLEX);
  148. #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
  149. /* Initialize the PCIe-1 to work as Root Complex */
  150. config_pcie_mode(1, ROOTCOMPLEX);
  151. #endif
  152. #ifdef CONFIG_SOC_K2L
  153. osr_init();
  154. #endif
  155. /*
  156. * just initialise the COM2 port so that TI specific
  157. * UART register PWREMU_MGMT is initialized. Linux UART
  158. * driver doesn't handle this.
  159. */
  160. #ifndef CONFIG_DM_SERIAL
  161. NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
  162. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  163. #endif
  164. return 0;
  165. }
  166. void reset_cpu(ulong addr)
  167. {
  168. volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
  169. u32 tmp;
  170. tmp = *rstctrl & KS2_RSTCTRL_MASK;
  171. *rstctrl = tmp | KS2_RSTCTRL_KEY;
  172. *rstctrl &= KS2_RSTCTRL_SWRST;
  173. for (;;)
  174. ;
  175. }
  176. void enable_caches(void)
  177. {
  178. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  179. /* Enable D-cache. I-cache is already enabled in start.S */
  180. dcache_enable();
  181. #endif
  182. }
  183. #if defined(CONFIG_DISPLAY_CPUINFO)
  184. int print_cpuinfo(void)
  185. {
  186. u16 cpu = get_part_number();
  187. u8 rev = cpu_revision();
  188. puts("CPU: ");
  189. switch (cpu) {
  190. case CPU_66AK2Hx:
  191. puts("66AK2Hx SR");
  192. break;
  193. case CPU_66AK2Lx:
  194. puts("66AK2Lx SR");
  195. break;
  196. case CPU_66AK2Ex:
  197. puts("66AK2Ex SR");
  198. break;
  199. case CPU_66AK2Gx:
  200. puts("66AK2Gx");
  201. #ifdef CONFIG_SOC_K2G
  202. {
  203. int speed = get_max_arm_speed(speeds);
  204. if (speed == SPD1000)
  205. puts("-100 ");
  206. else if (speed == SPD600)
  207. puts("-60 ");
  208. else
  209. puts("-xx ");
  210. }
  211. #endif
  212. puts("SR");
  213. break;
  214. default:
  215. puts("Unknown\n");
  216. }
  217. if (rev == 2)
  218. puts("2.0\n");
  219. else if (rev == 1)
  220. puts("1.1\n");
  221. else if (rev == 0)
  222. puts("1.0\n");
  223. else if (rev == 8)
  224. puts("1.0\n");
  225. return 0;
  226. }
  227. #endif