cpu.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu.h>
  8. #include <cpu_func.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <asm/cache.h>
  12. #include <dm/device-internal.h>
  13. #include <dm/lists.h>
  14. #include <dm/uclass.h>
  15. #include <errno.h>
  16. #include <spl.h>
  17. #include <thermal.h>
  18. #include <asm/arch/sci/sci.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch-imx/cpu.h>
  21. #include <asm/armv8/cpu.h>
  22. #include <asm/armv8/mmu.h>
  23. #include <asm/setup.h>
  24. #include <asm/mach-imx/boot_mode.h>
  25. #include <spl.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define BT_PASSOVER_TAG 0x504F
  28. struct pass_over_info_t *get_pass_over_info(void)
  29. {
  30. struct pass_over_info_t *p =
  31. (struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
  32. if (p->barker != BT_PASSOVER_TAG ||
  33. p->len != sizeof(struct pass_over_info_t))
  34. return NULL;
  35. return p;
  36. }
  37. int arch_cpu_init(void)
  38. {
  39. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
  40. spl_save_restore_data();
  41. #endif
  42. #ifdef CONFIG_SPL_BUILD
  43. struct pass_over_info_t *pass_over;
  44. if (is_soc_rev(CHIP_REV_A)) {
  45. pass_over = get_pass_over_info();
  46. if (pass_over && pass_over->g_ap_mu == 0) {
  47. /*
  48. * When ap_mu is 0, means the U-Boot booted
  49. * from first container
  50. */
  51. sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
  52. }
  53. }
  54. #endif
  55. return 0;
  56. }
  57. int arch_cpu_init_dm(void)
  58. {
  59. struct udevice *devp;
  60. int node, ret;
  61. node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
  62. ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
  63. if (ret) {
  64. printf("could not get scu %d\n", ret);
  65. return ret;
  66. }
  67. if (is_imx8qm()) {
  68. ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
  69. SC_PM_PW_MODE_ON);
  70. if (ret)
  71. return ret;
  72. }
  73. return 0;
  74. }
  75. int print_bootinfo(void)
  76. {
  77. enum boot_device bt_dev = get_boot_device();
  78. puts("Boot: ");
  79. switch (bt_dev) {
  80. case SD1_BOOT:
  81. puts("SD0\n");
  82. break;
  83. case SD2_BOOT:
  84. puts("SD1\n");
  85. break;
  86. case SD3_BOOT:
  87. puts("SD2\n");
  88. break;
  89. case MMC1_BOOT:
  90. puts("MMC0\n");
  91. break;
  92. case MMC2_BOOT:
  93. puts("MMC1\n");
  94. break;
  95. case MMC3_BOOT:
  96. puts("MMC2\n");
  97. break;
  98. case FLEXSPI_BOOT:
  99. puts("FLEXSPI\n");
  100. break;
  101. case SATA_BOOT:
  102. puts("SATA\n");
  103. break;
  104. case NAND_BOOT:
  105. puts("NAND\n");
  106. break;
  107. case USB_BOOT:
  108. puts("USB\n");
  109. break;
  110. default:
  111. printf("Unknown device %u\n", bt_dev);
  112. break;
  113. }
  114. return 0;
  115. }
  116. enum boot_device get_boot_device(void)
  117. {
  118. enum boot_device boot_dev = SD1_BOOT;
  119. sc_rsrc_t dev_rsrc;
  120. sc_misc_get_boot_dev(-1, &dev_rsrc);
  121. switch (dev_rsrc) {
  122. case SC_R_SDHC_0:
  123. boot_dev = MMC1_BOOT;
  124. break;
  125. case SC_R_SDHC_1:
  126. boot_dev = SD2_BOOT;
  127. break;
  128. case SC_R_SDHC_2:
  129. boot_dev = SD3_BOOT;
  130. break;
  131. case SC_R_NAND:
  132. boot_dev = NAND_BOOT;
  133. break;
  134. case SC_R_FSPI_0:
  135. boot_dev = FLEXSPI_BOOT;
  136. break;
  137. case SC_R_SATA_0:
  138. boot_dev = SATA_BOOT;
  139. break;
  140. case SC_R_USB_0:
  141. case SC_R_USB_1:
  142. case SC_R_USB_2:
  143. boot_dev = USB_BOOT;
  144. break;
  145. default:
  146. break;
  147. }
  148. return boot_dev;
  149. }
  150. #ifdef CONFIG_SERIAL_TAG
  151. #define FUSE_UNIQUE_ID_WORD0 16
  152. #define FUSE_UNIQUE_ID_WORD1 17
  153. void get_board_serial(struct tag_serialnr *serialnr)
  154. {
  155. sc_err_t err;
  156. u32 val1 = 0, val2 = 0;
  157. u32 word1, word2;
  158. if (!serialnr)
  159. return;
  160. word1 = FUSE_UNIQUE_ID_WORD0;
  161. word2 = FUSE_UNIQUE_ID_WORD1;
  162. err = sc_misc_otp_fuse_read(-1, word1, &val1);
  163. if (err != SC_ERR_NONE) {
  164. printf("%s fuse %d read error: %d\n", __func__, word1, err);
  165. return;
  166. }
  167. err = sc_misc_otp_fuse_read(-1, word2, &val2);
  168. if (err != SC_ERR_NONE) {
  169. printf("%s fuse %d read error: %d\n", __func__, word2, err);
  170. return;
  171. }
  172. serialnr->low = val1;
  173. serialnr->high = val2;
  174. }
  175. #endif /*CONFIG_SERIAL_TAG*/
  176. #ifdef CONFIG_ENV_IS_IN_MMC
  177. __weak int board_mmc_get_env_dev(int devno)
  178. {
  179. return CONFIG_SYS_MMC_ENV_DEV;
  180. }
  181. int mmc_get_env_dev(void)
  182. {
  183. sc_rsrc_t dev_rsrc;
  184. int devno;
  185. sc_misc_get_boot_dev(-1, &dev_rsrc);
  186. switch (dev_rsrc) {
  187. case SC_R_SDHC_0:
  188. devno = 0;
  189. break;
  190. case SC_R_SDHC_1:
  191. devno = 1;
  192. break;
  193. case SC_R_SDHC_2:
  194. devno = 2;
  195. break;
  196. default:
  197. /* If not boot from sd/mmc, use default value */
  198. return CONFIG_SYS_MMC_ENV_DEV;
  199. }
  200. return board_mmc_get_env_dev(devno);
  201. }
  202. #endif
  203. #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
  204. static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
  205. sc_faddr_t *addr_end)
  206. {
  207. sc_faddr_t start, end;
  208. int ret;
  209. bool owned;
  210. owned = sc_rm_is_memreg_owned(-1, mr);
  211. if (owned) {
  212. ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
  213. if (ret) {
  214. printf("Memreg get info failed, %d\n", ret);
  215. return -EINVAL;
  216. }
  217. debug("0x%llx -- 0x%llx\n", start, end);
  218. *addr_start = start;
  219. *addr_end = end;
  220. return 0;
  221. }
  222. return -EINVAL;
  223. }
  224. phys_size_t get_effective_memsize(void)
  225. {
  226. sc_rm_mr_t mr;
  227. sc_faddr_t start, end, end1, start_aligned;
  228. int err;
  229. end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
  230. for (mr = 0; mr < 64; mr++) {
  231. err = get_owned_memreg(mr, &start, &end);
  232. if (!err) {
  233. start_aligned = roundup(start, MEMSTART_ALIGNMENT);
  234. /* Too small memory region, not use it */
  235. if (start_aligned > end)
  236. continue;
  237. /* Find the memory region runs the U-Boot */
  238. if (start >= PHYS_SDRAM_1 && start <= end1 &&
  239. (start <= CONFIG_SYS_TEXT_BASE &&
  240. end >= CONFIG_SYS_TEXT_BASE)) {
  241. if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
  242. PHYS_SDRAM_1_SIZE))
  243. return (end - PHYS_SDRAM_1 + 1);
  244. else
  245. return PHYS_SDRAM_1_SIZE;
  246. }
  247. }
  248. }
  249. return PHYS_SDRAM_1_SIZE;
  250. }
  251. int dram_init(void)
  252. {
  253. sc_rm_mr_t mr;
  254. sc_faddr_t start, end, end1, end2;
  255. int err;
  256. end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
  257. end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
  258. for (mr = 0; mr < 64; mr++) {
  259. err = get_owned_memreg(mr, &start, &end);
  260. if (!err) {
  261. start = roundup(start, MEMSTART_ALIGNMENT);
  262. /* Too small memory region, not use it */
  263. if (start > end)
  264. continue;
  265. if (start >= PHYS_SDRAM_1 && start <= end1) {
  266. if ((end + 1) <= end1)
  267. gd->ram_size += end - start + 1;
  268. else
  269. gd->ram_size += end1 - start;
  270. } else if (start >= PHYS_SDRAM_2 && start <= end2) {
  271. if ((end + 1) <= end2)
  272. gd->ram_size += end - start + 1;
  273. else
  274. gd->ram_size += end2 - start;
  275. }
  276. }
  277. }
  278. /* If error, set to the default value */
  279. if (!gd->ram_size) {
  280. gd->ram_size = PHYS_SDRAM_1_SIZE;
  281. gd->ram_size += PHYS_SDRAM_2_SIZE;
  282. }
  283. return 0;
  284. }
  285. static void dram_bank_sort(int current_bank)
  286. {
  287. phys_addr_t start;
  288. phys_size_t size;
  289. while (current_bank > 0) {
  290. if (gd->bd->bi_dram[current_bank - 1].start >
  291. gd->bd->bi_dram[current_bank].start) {
  292. start = gd->bd->bi_dram[current_bank - 1].start;
  293. size = gd->bd->bi_dram[current_bank - 1].size;
  294. gd->bd->bi_dram[current_bank - 1].start =
  295. gd->bd->bi_dram[current_bank].start;
  296. gd->bd->bi_dram[current_bank - 1].size =
  297. gd->bd->bi_dram[current_bank].size;
  298. gd->bd->bi_dram[current_bank].start = start;
  299. gd->bd->bi_dram[current_bank].size = size;
  300. }
  301. current_bank--;
  302. }
  303. }
  304. int dram_init_banksize(void)
  305. {
  306. sc_rm_mr_t mr;
  307. sc_faddr_t start, end, end1, end2;
  308. int i = 0;
  309. int err;
  310. end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
  311. end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
  312. for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
  313. err = get_owned_memreg(mr, &start, &end);
  314. if (!err) {
  315. start = roundup(start, MEMSTART_ALIGNMENT);
  316. if (start > end) /* Small memory region, no use it */
  317. continue;
  318. if (start >= PHYS_SDRAM_1 && start <= end1) {
  319. gd->bd->bi_dram[i].start = start;
  320. if ((end + 1) <= end1)
  321. gd->bd->bi_dram[i].size =
  322. end - start + 1;
  323. else
  324. gd->bd->bi_dram[i].size = end1 - start;
  325. dram_bank_sort(i);
  326. i++;
  327. } else if (start >= PHYS_SDRAM_2 && start <= end2) {
  328. gd->bd->bi_dram[i].start = start;
  329. if ((end + 1) <= end2)
  330. gd->bd->bi_dram[i].size =
  331. end - start + 1;
  332. else
  333. gd->bd->bi_dram[i].size = end2 - start;
  334. dram_bank_sort(i);
  335. i++;
  336. }
  337. }
  338. }
  339. /* If error, set to the default value */
  340. if (!i) {
  341. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  342. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  343. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  344. gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  345. }
  346. return 0;
  347. }
  348. static u64 get_block_attrs(sc_faddr_t addr_start)
  349. {
  350. u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
  351. PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  352. if ((addr_start >= PHYS_SDRAM_1 &&
  353. addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
  354. (addr_start >= PHYS_SDRAM_2 &&
  355. addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
  356. return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
  357. return attr;
  358. }
  359. static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
  360. {
  361. sc_faddr_t end1, end2;
  362. end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
  363. end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
  364. if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
  365. if ((addr_end + 1) > end1)
  366. return end1 - addr_start;
  367. } else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
  368. if ((addr_end + 1) > end2)
  369. return end2 - addr_start;
  370. }
  371. return (addr_end - addr_start + 1);
  372. }
  373. #define MAX_PTE_ENTRIES 512
  374. #define MAX_MEM_MAP_REGIONS 16
  375. static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
  376. struct mm_region *mem_map = imx8_mem_map;
  377. void enable_caches(void)
  378. {
  379. sc_rm_mr_t mr;
  380. sc_faddr_t start, end;
  381. int err, i;
  382. /* Create map for registers access from 0x1c000000 to 0x80000000*/
  383. imx8_mem_map[0].virt = 0x1c000000UL;
  384. imx8_mem_map[0].phys = 0x1c000000UL;
  385. imx8_mem_map[0].size = 0x64000000UL;
  386. imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  387. PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  388. i = 1;
  389. for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
  390. err = get_owned_memreg(mr, &start, &end);
  391. if (!err) {
  392. imx8_mem_map[i].virt = start;
  393. imx8_mem_map[i].phys = start;
  394. imx8_mem_map[i].size = get_block_size(start, end);
  395. imx8_mem_map[i].attrs = get_block_attrs(start);
  396. i++;
  397. }
  398. }
  399. if (i < MAX_MEM_MAP_REGIONS) {
  400. imx8_mem_map[i].size = 0;
  401. imx8_mem_map[i].attrs = 0;
  402. } else {
  403. puts("Error, need more MEM MAP REGIONS reserved\n");
  404. icache_enable();
  405. return;
  406. }
  407. for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
  408. debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
  409. i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
  410. imx8_mem_map[i].size, imx8_mem_map[i].attrs);
  411. }
  412. icache_enable();
  413. dcache_enable();
  414. }
  415. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  416. u64 get_page_table_size(void)
  417. {
  418. u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
  419. u64 size = 0;
  420. /*
  421. * For each memory region, the max table size:
  422. * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
  423. */
  424. size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
  425. /*
  426. * We need to duplicate our page table once to have an emergency pt to
  427. * resort to when splitting page tables later on
  428. */
  429. size *= 2;
  430. /*
  431. * We may need to split page tables later on if dcache settings change,
  432. * so reserve up to 4 (random pick) page tables for that.
  433. */
  434. size += one_pt * 4;
  435. return size;
  436. }
  437. #endif
  438. #if defined(CONFIG_IMX8QM)
  439. #define FUSE_MAC0_WORD0 452
  440. #define FUSE_MAC0_WORD1 453
  441. #define FUSE_MAC1_WORD0 454
  442. #define FUSE_MAC1_WORD1 455
  443. #elif defined(CONFIG_IMX8QXP)
  444. #define FUSE_MAC0_WORD0 708
  445. #define FUSE_MAC0_WORD1 709
  446. #define FUSE_MAC1_WORD0 710
  447. #define FUSE_MAC1_WORD1 711
  448. #endif
  449. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  450. {
  451. u32 word[2], val[2] = {};
  452. int i, ret;
  453. if (dev_id == 0) {
  454. word[0] = FUSE_MAC0_WORD0;
  455. word[1] = FUSE_MAC0_WORD1;
  456. } else {
  457. word[0] = FUSE_MAC1_WORD0;
  458. word[1] = FUSE_MAC1_WORD1;
  459. }
  460. for (i = 0; i < 2; i++) {
  461. ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
  462. if (ret < 0)
  463. goto err;
  464. }
  465. mac[0] = val[0];
  466. mac[1] = val[0] >> 8;
  467. mac[2] = val[0] >> 16;
  468. mac[3] = val[0] >> 24;
  469. mac[4] = val[1];
  470. mac[5] = val[1] >> 8;
  471. debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
  472. __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  473. return;
  474. err:
  475. printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
  476. }
  477. u32 get_cpu_rev(void)
  478. {
  479. u32 id = 0, rev = 0;
  480. int ret;
  481. ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
  482. if (ret)
  483. return 0;
  484. rev = (id >> 5) & 0xf;
  485. id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
  486. return (id << 12) | rev;
  487. }
  488. void board_boot_order(u32 *spl_boot_list)
  489. {
  490. spl_boot_list[0] = spl_boot_device();
  491. if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
  492. /* Check whether we own the flexspi0, if not, use NOR boot */
  493. if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
  494. spl_boot_list[0] = BOOT_DEVICE_NOR;
  495. }
  496. }
  497. bool m4_parts_booted(void)
  498. {
  499. sc_rm_pt_t m4_parts[2];
  500. int err;
  501. err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
  502. if (err) {
  503. printf("%s get resource [%d] owner error: %d\n", __func__,
  504. SC_R_M4_0_PID0, err);
  505. return false;
  506. }
  507. if (sc_pm_is_partition_started(-1, m4_parts[0]))
  508. return true;
  509. if (is_imx8qm()) {
  510. err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
  511. if (err) {
  512. printf("%s get resource [%d] owner error: %d\n",
  513. __func__, SC_R_M4_1_PID0, err);
  514. return false;
  515. }
  516. if (sc_pm_is_partition_started(-1, m4_parts[1]))
  517. return true;
  518. }
  519. return false;
  520. }