spl_boot.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. */
  5. #include <common.h>
  6. #include <config.h>
  7. #include <asm/cache.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/clk.h>
  10. #include <asm/arch/dmc.h>
  11. #include <asm/arch/periph.h>
  12. #include <asm/arch/pinmux.h>
  13. #include <asm/arch/power.h>
  14. #include <asm/arch/spl.h>
  15. #include <asm/arch/spi.h>
  16. #include "common_setup.h"
  17. #include "clock_init.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /* Index into irom ptr table */
  20. enum index {
  21. MMC_INDEX,
  22. EMMC44_INDEX,
  23. EMMC44_END_INDEX,
  24. SPI_INDEX,
  25. USB_INDEX,
  26. };
  27. /* IROM Function Pointers Table */
  28. u32 irom_ptr_table[] = {
  29. [MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
  30. [EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
  31. [EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
  32. -EMMC4.4 end boot operation */
  33. [SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
  34. [USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
  35. };
  36. void *get_irom_func(int index)
  37. {
  38. return (void *)*(u32 *)irom_ptr_table[index];
  39. }
  40. #ifdef CONFIG_USB_BOOTING
  41. /*
  42. * Set/clear program flow prediction and return the previous state.
  43. */
  44. static int config_branch_prediction(int set_cr_z)
  45. {
  46. unsigned int cr;
  47. /* System Control Register: 11th bit Z Branch prediction enable */
  48. cr = get_cr();
  49. set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
  50. return cr & CR_Z;
  51. }
  52. #endif
  53. #ifdef CONFIG_SPI_BOOTING
  54. static void spi_rx_tx(struct exynos_spi *regs, int todo,
  55. void *dinp, void const *doutp, int i)
  56. {
  57. uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
  58. int rx_lvl, tx_lvl;
  59. uint out_bytes, in_bytes;
  60. out_bytes = todo;
  61. in_bytes = todo;
  62. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  63. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  64. writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  65. while (in_bytes) {
  66. uint32_t spi_sts;
  67. int temp;
  68. spi_sts = readl(&regs->spi_sts);
  69. rx_lvl = ((spi_sts >> 15) & 0x7f);
  70. tx_lvl = ((spi_sts >> 6) & 0x7f);
  71. while (tx_lvl < 32 && out_bytes) {
  72. temp = 0xffffffff;
  73. writel(temp, &regs->tx_data);
  74. out_bytes -= 4;
  75. tx_lvl += 4;
  76. }
  77. while (rx_lvl >= 4 && in_bytes) {
  78. temp = readl(&regs->rx_data);
  79. if (rxp)
  80. *rxp++ = temp;
  81. in_bytes -= 4;
  82. rx_lvl -= 4;
  83. }
  84. }
  85. }
  86. /*
  87. * Copy uboot from spi flash to RAM
  88. *
  89. * @parma uboot_size size of u-boot to copy
  90. * @param uboot_addr address in u-boot to copy
  91. */
  92. static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
  93. {
  94. int upto, todo;
  95. int i, timeout = 100;
  96. struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
  97. set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
  98. /* set the spi1 GPIO */
  99. exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
  100. /* set pktcnt and enable it */
  101. writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
  102. /* set FB_CLK_SEL */
  103. writel(SPI_FB_DELAY_180, &regs->fb_clk);
  104. /* set CH_WIDTH and BUS_WIDTH as word */
  105. setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  106. SPI_MODE_BUS_WIDTH_WORD);
  107. clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
  108. /* clear rx and tx channel if set priveously */
  109. clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
  110. setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
  111. SPI_RX_BYTE_SWAP |
  112. SPI_RX_HWORD_SWAP);
  113. /* do a soft reset */
  114. setbits_le32(&regs->ch_cfg, SPI_CH_RST);
  115. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  116. /* now set rx and tx channel ON */
  117. setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
  118. clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
  119. /* Send read instruction (0x3h) followed by a 24 bit addr */
  120. writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
  121. /* waiting for TX done */
  122. while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
  123. if (!timeout) {
  124. debug("SPI TIMEOUT\n");
  125. break;
  126. }
  127. timeout--;
  128. }
  129. for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
  130. todo = min(uboot_size - upto, (unsigned int)(1 << 15));
  131. spi_rx_tx(regs, todo, (void *)(uboot_addr),
  132. (void *)(SPI_FLASH_UBOOT_POS), i);
  133. }
  134. setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
  135. /*
  136. * Let put controller mode to BYTE as
  137. * SPI driver does not support WORD mode yet
  138. */
  139. clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
  140. SPI_MODE_BUS_WIDTH_WORD);
  141. writel(0, &regs->swap_cfg);
  142. /*
  143. * Flush spi tx, rx fifos and reset the SPI controller
  144. * and clear rx/tx channel
  145. */
  146. clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
  147. clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
  148. clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
  149. }
  150. #endif
  151. /*
  152. * Copy U-Boot from mmc to RAM:
  153. * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
  154. * Pointer to API (Data transfer from mmc to ram)
  155. */
  156. void copy_uboot_to_ram(void)
  157. {
  158. unsigned int bootmode = BOOT_MODE_OM;
  159. u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
  160. u32 offset = 0, size = 0;
  161. #ifdef CONFIG_SPI_BOOTING
  162. struct spl_machine_param *param = spl_get_machine_params();
  163. #endif
  164. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  165. u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
  166. void (*end_bootop_from_emmc)(void);
  167. #endif
  168. #ifdef CONFIG_USB_BOOTING
  169. int is_cr_z_set;
  170. unsigned int sec_boot_check;
  171. /*
  172. * Note that older hardware (before Exynos5800) does not expect any
  173. * arguments, but it does not hurt to pass them, so a common function
  174. * prototype is used.
  175. */
  176. u32 (*usb_copy)(u32 num_of_block, u32 *dst);
  177. /* Read iRAM location to check for secondary USB boot mode */
  178. sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
  179. if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
  180. bootmode = BOOT_MODE_USB;
  181. #endif
  182. if (bootmode == BOOT_MODE_OM)
  183. bootmode = get_boot_mode();
  184. switch (bootmode) {
  185. #ifdef CONFIG_SPI_BOOTING
  186. case BOOT_MODE_SERIAL:
  187. /* Customised function to copy u-boot from SF */
  188. exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
  189. break;
  190. #endif
  191. case BOOT_MODE_SD:
  192. offset = BL2_START_OFFSET;
  193. size = BL2_SIZE_BLOC_COUNT;
  194. copy_bl2 = get_irom_func(MMC_INDEX);
  195. break;
  196. #ifdef CONFIG_SUPPORT_EMMC_BOOT
  197. case BOOT_MODE_EMMC:
  198. /* Set the FSYS1 clock divisor value for EMMC boot */
  199. emmc_boot_clk_div_set();
  200. copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
  201. end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
  202. copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
  203. end_bootop_from_emmc();
  204. break;
  205. #endif
  206. #ifdef CONFIG_USB_BOOTING
  207. case BOOT_MODE_USB:
  208. /*
  209. * iROM needs program flow prediction to be disabled
  210. * before copy from USB device to RAM
  211. */
  212. is_cr_z_set = config_branch_prediction(0);
  213. usb_copy = get_irom_func(USB_INDEX);
  214. usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
  215. config_branch_prediction(is_cr_z_set);
  216. break;
  217. #endif
  218. default:
  219. break;
  220. }
  221. if (copy_bl2)
  222. copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
  223. }
  224. void memzero(void *s, size_t n)
  225. {
  226. char *ptr = s;
  227. size_t i;
  228. for (i = 0; i < n; i++)
  229. *ptr++ = '\0';
  230. }
  231. /**
  232. * Set up the U-Boot global_data pointer
  233. *
  234. * This sets the address of the global data, and sets up basic values.
  235. *
  236. * @param gdp Value to give to gd
  237. */
  238. static void setup_global_data(gd_t *gdp)
  239. {
  240. gd = gdp;
  241. memzero((void *)gd, sizeof(gd_t));
  242. gd->flags |= GD_FLG_RELOC;
  243. gd->baudrate = CONFIG_BAUDRATE;
  244. gd->have_console = 1;
  245. }
  246. void board_init_f(unsigned long bootflag)
  247. {
  248. __aligned(8) gd_t local_gd;
  249. __attribute__((noreturn)) void (*uboot)(void);
  250. setup_global_data(&local_gd);
  251. if (do_lowlevel_init())
  252. power_exit_wakeup();
  253. copy_uboot_to_ram();
  254. /* Jump to U-Boot image */
  255. uboot = (void *)CONFIG_SYS_TEXT_BASE;
  256. (*uboot)();
  257. /* Never returns Here */
  258. }
  259. /* Place Holders */
  260. void board_init_r(gd_t *id, ulong dest_addr)
  261. {
  262. /* Function attribute is no-return */
  263. /* This Function never executes */
  264. while (1)
  265. ;
  266. }