virt-v7.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Andre Przywara, Linaro <andre.przywara@linaro.org>
  5. *
  6. * Routines to transition ARMv7 processors from secure into non-secure state
  7. * and from non-secure SVC into HYP mode
  8. * needed to enable ARMv7 virtualization for current hypervisors
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <asm/armv7.h>
  13. #include <asm/cache.h>
  14. #include <asm/gic.h>
  15. #include <asm/io.h>
  16. #include <asm/secure.h>
  17. static unsigned int read_id_pfr1(void)
  18. {
  19. unsigned int reg;
  20. asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
  21. return reg;
  22. }
  23. static unsigned long get_gicd_base_address(void)
  24. {
  25. #ifdef CONFIG_ARM_GIC_BASE_ADDRESS
  26. return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
  27. #else
  28. unsigned periphbase;
  29. /* get the GIC base address from the CBAR register */
  30. asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
  31. /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
  32. * encode this). Bail out here since we cannot access this without
  33. * enabling paging.
  34. */
  35. if ((periphbase & 0xff) != 0) {
  36. printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");
  37. return -1;
  38. }
  39. return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
  40. #endif
  41. }
  42. /* Define a specific version of this function to enable any available
  43. * hardware protections for the reserved region */
  44. void __weak protect_secure_section(void) {}
  45. static void relocate_secure_section(void)
  46. {
  47. #ifdef CONFIG_ARMV7_SECURE_BASE
  48. size_t sz = __secure_end - __secure_start;
  49. unsigned long szflush = ALIGN(sz + 1, CONFIG_SYS_CACHELINE_SIZE);
  50. memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz);
  51. flush_dcache_range(CONFIG_ARMV7_SECURE_BASE,
  52. CONFIG_ARMV7_SECURE_BASE + szflush);
  53. protect_secure_section();
  54. invalidate_icache_all();
  55. #endif
  56. }
  57. static void kick_secondary_cpus_gic(unsigned long gicdaddr)
  58. {
  59. /* kick all CPUs (except this one) by writing to GICD_SGIR */
  60. writel(1U << 24, gicdaddr + GICD_SGIR);
  61. }
  62. void __weak smp_kick_all_cpus(void)
  63. {
  64. unsigned long gic_dist_addr;
  65. gic_dist_addr = get_gicd_base_address();
  66. if (gic_dist_addr == -1)
  67. return;
  68. kick_secondary_cpus_gic(gic_dist_addr);
  69. }
  70. __weak void psci_board_init(void)
  71. {
  72. }
  73. int armv7_init_nonsec(void)
  74. {
  75. unsigned int reg;
  76. unsigned itlinesnr, i;
  77. unsigned long gic_dist_addr;
  78. /* check whether the CPU supports the security extensions */
  79. reg = read_id_pfr1();
  80. if ((reg & 0xF0) == 0) {
  81. printf("nonsec: Security extensions not implemented.\n");
  82. return -1;
  83. }
  84. /* the SCR register will be set directly in the monitor mode handler,
  85. * according to the spec one should not tinker with it in secure state
  86. * in SVC mode. Do not try to read it once in non-secure state,
  87. * any access to it will trap.
  88. */
  89. gic_dist_addr = get_gicd_base_address();
  90. if (gic_dist_addr == -1)
  91. return -1;
  92. /* enable the GIC distributor */
  93. writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
  94. gic_dist_addr + GICD_CTLR);
  95. /* TYPER[4:0] contains an encoded number of available interrupts */
  96. itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
  97. /* set all bits in the GIC group registers to one to allow access
  98. * from non-secure state. The first 32 interrupts are private per
  99. * CPU and will be set later when enabling the GIC for each core
  100. */
  101. for (i = 1; i <= itlinesnr; i++)
  102. writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
  103. psci_board_init();
  104. /*
  105. * Relocate secure section before any cpu runs in secure ram.
  106. * smp_kick_all_cpus may enable other cores and runs into secure
  107. * ram, so need to relocate secure section before enabling other
  108. * cores.
  109. */
  110. relocate_secure_section();
  111. #ifndef CONFIG_ARMV7_PSCI
  112. smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
  113. smp_kick_all_cpus();
  114. #endif
  115. /* call the non-sec switching code on this CPU also */
  116. secure_ram_addr(_nonsec_init)();
  117. return 0;
  118. }