cpu.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <net.h>
  8. #include <vsprintf.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/immap_ls102xa.h>
  12. #include <asm/cache.h>
  13. #include <asm/system.h>
  14. #include <tsec.h>
  15. #include <netdev.h>
  16. #include <fsl_esdhc.h>
  17. #include <config.h>
  18. #include <fsl_wdog.h>
  19. #include "fsl_epu.h"
  20. #define DCSR_RCPM2_BLOCK_OFFSET 0x223000
  21. #define DCSR_RCPM2_CPMFSMCR0 0x400
  22. #define DCSR_RCPM2_CPMFSMSR0 0x404
  23. #define DCSR_RCPM2_CPMFSMCR1 0x414
  24. #define DCSR_RCPM2_CPMFSMSR1 0x418
  25. #define CPMFSMSR_FSM_STATE_MASK 0x7f
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  28. /*
  29. * Bit[1] of the descriptor indicates the descriptor type,
  30. * and bit[0] indicates whether the descriptor is valid.
  31. */
  32. #define PMD_TYPE_TABLE 0x3
  33. #define PMD_TYPE_SECT 0x1
  34. /* AttrIndx[2:0] */
  35. #define PMD_ATTRINDX(t) ((t) << 2)
  36. /* Section */
  37. #define PMD_SECT_AF (1 << 10)
  38. #define BLOCK_SIZE_L1 (1UL << 30)
  39. #define BLOCK_SIZE_L2 (1UL << 21)
  40. /* TTBCR flags */
  41. #define TTBCR_EAE (1 << 31)
  42. #define TTBCR_T0SZ(x) ((x) << 0)
  43. #define TTBCR_T1SZ(x) ((x) << 16)
  44. #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
  45. #define TTBCR_IRGN0_NC (0 << 8)
  46. #define TTBCR_IRGN0_WBWA (1 << 8)
  47. #define TTBCR_IRGN0_WT (2 << 8)
  48. #define TTBCR_IRGN0_WBNWA (3 << 8)
  49. #define TTBCR_IRGN0_MASK (3 << 8)
  50. #define TTBCR_ORGN0_NC (0 << 10)
  51. #define TTBCR_ORGN0_WBWA (1 << 10)
  52. #define TTBCR_ORGN0_WT (2 << 10)
  53. #define TTBCR_ORGN0_WBNWA (3 << 10)
  54. #define TTBCR_ORGN0_MASK (3 << 10)
  55. #define TTBCR_SHARED_NON (0 << 12)
  56. #define TTBCR_SHARED_OUTER (2 << 12)
  57. #define TTBCR_SHARED_INNER (3 << 12)
  58. #define TTBCR_EPD0 (0 << 7)
  59. #define TTBCR (TTBCR_SHARED_NON | \
  60. TTBCR_ORGN0_NC | \
  61. TTBCR_IRGN0_NC | \
  62. TTBCR_USING_TTBR0 | \
  63. TTBCR_EAE)
  64. /*
  65. * Memory region attributes for LPAE (defined in pgtable):
  66. *
  67. * n = AttrIndx[2:0]
  68. *
  69. * n MAIR
  70. * UNCACHED 000 00000000
  71. * BUFFERABLE 001 01000100
  72. * DEV_WC 001 01000100
  73. * WRITETHROUGH 010 10101010
  74. * WRITEBACK 011 11101110
  75. * DEV_CACHED 011 11101110
  76. * DEV_SHARED 100 00000100
  77. * DEV_NONSHARED 100 00000100
  78. * unused 101
  79. * unused 110
  80. * WRITEALLOC 111 11111111
  81. */
  82. #define MT_MAIR0 0xeeaa4400
  83. #define MT_MAIR1 0xff000004
  84. #define MT_STRONLY_ORDER 0
  85. #define MT_NORMAL_NC 1
  86. #define MT_DEVICE_MEM 4
  87. #define MT_NORMAL 7
  88. /* The phy_addr must be aligned to 4KB */
  89. static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
  90. {
  91. u32 value = phy_addr | PMD_TYPE_TABLE;
  92. page_table[2 * index] = value;
  93. page_table[2 * index + 1] = 0;
  94. }
  95. /* The phy_addr must be aligned to 4KB */
  96. static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
  97. u32 memory_type)
  98. {
  99. u64 value;
  100. value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
  101. value |= PMD_ATTRINDX(memory_type);
  102. page_table[2 * index] = value & 0xFFFFFFFF;
  103. page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
  104. }
  105. /*
  106. * Start MMU after DDR is available, we create MMU table in DRAM.
  107. * The base address of TTLB is gd->arch.tlb_addr. We use two
  108. * levels of translation tables here to cover 40-bit address space.
  109. *
  110. * The TTLBs are located at PHY 2G~4G.
  111. *
  112. * VA mapping:
  113. *
  114. * ------- <---- 0GB
  115. * | |
  116. * | |
  117. * |-------| <---- 0x24000000
  118. * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
  119. * |-------| <---- 0x300000000
  120. * | |
  121. * |-------| <---- 0x34000000
  122. * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
  123. * |-------| <---- 0x40000000
  124. * | |
  125. * |-------| <---- 0x80000000 DDR0 space start
  126. * |\\\\\\\|
  127. *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
  128. * |\\\\\\\|
  129. * ------- <---- 4GB DDR0 space end
  130. */
  131. static void mmu_setup(void)
  132. {
  133. u32 *level0_table = (u32 *)gd->arch.tlb_addr;
  134. u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
  135. u64 va_start = 0;
  136. u32 reg;
  137. int i;
  138. /* Level 0 Table 2-3 are used to map DDR */
  139. set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
  140. set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
  141. /* Level 0 Table 1 is used to map device */
  142. set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
  143. /* Level 0 Table 0 is used to map device including PCIe MEM */
  144. set_pgtable(level0_table, 0, (u32)level1_table);
  145. /* Level 1 has 512 entries */
  146. for (i = 0; i < 512; i++) {
  147. /* Mapping for PCIe 1 */
  148. if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
  149. va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
  150. CONFIG_SYS_PCIE_MMAP_SIZE))
  151. set_pgsection(level1_table, i,
  152. CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
  153. MT_DEVICE_MEM);
  154. /* Mapping for PCIe 2 */
  155. else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
  156. va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
  157. CONFIG_SYS_PCIE_MMAP_SIZE))
  158. set_pgsection(level1_table, i,
  159. CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
  160. MT_DEVICE_MEM);
  161. else
  162. set_pgsection(level1_table, i,
  163. va_start,
  164. MT_DEVICE_MEM);
  165. va_start += BLOCK_SIZE_L2;
  166. }
  167. asm volatile("dsb sy;isb");
  168. asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
  169. : : "r" (TTBCR) : "memory");
  170. asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
  171. : : "r" ((u32)level0_table), "r" (0) : "memory");
  172. asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
  173. : : "r" (MT_MAIR0) : "memory");
  174. asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
  175. : : "r" (MT_MAIR1) : "memory");
  176. /* Set the access control to all-supervisor */
  177. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  178. : : "r" (~0));
  179. /* Enable the mmu */
  180. reg = get_cr();
  181. set_cr(reg | CR_M);
  182. }
  183. /*
  184. * This function is called from lib/board.c. It recreates MMU
  185. * table in main memory. MMU and i/d-cache are enabled here.
  186. */
  187. void enable_caches(void)
  188. {
  189. /* Invalidate all TLB */
  190. mmu_page_table_flush(gd->arch.tlb_addr,
  191. gd->arch.tlb_addr + gd->arch.tlb_size);
  192. /* Set up and enable mmu */
  193. mmu_setup();
  194. /* Invalidate & Enable d-cache */
  195. invalidate_dcache_all();
  196. set_cr(get_cr() | CR_C);
  197. }
  198. #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  199. uint get_svr(void)
  200. {
  201. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  202. return in_be32(&gur->svr);
  203. }
  204. #if defined(CONFIG_DISPLAY_CPUINFO)
  205. int print_cpuinfo(void)
  206. {
  207. char buf1[32], buf2[32];
  208. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  209. unsigned int svr, major, minor, ver, i;
  210. svr = in_be32(&gur->svr);
  211. major = SVR_MAJ(svr);
  212. minor = SVR_MIN(svr);
  213. puts("CPU: Freescale LayerScape ");
  214. ver = SVR_SOC_VER(svr);
  215. switch (ver) {
  216. case SOC_VER_SLS1020:
  217. puts("SLS1020");
  218. break;
  219. case SOC_VER_LS1020:
  220. puts("LS1020");
  221. break;
  222. case SOC_VER_LS1021:
  223. puts("LS1021");
  224. break;
  225. case SOC_VER_LS1022:
  226. puts("LS1022");
  227. break;
  228. default:
  229. puts("Unknown");
  230. break;
  231. }
  232. if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
  233. puts("E");
  234. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  235. puts("Clock Configuration:");
  236. printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
  237. printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
  238. printf("DDR:%-4s MHz (%s MT/s data rate), ",
  239. strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
  240. puts("\n");
  241. /* Display the RCW, so that no one gets confused as to what RCW
  242. * we're actually using for this boot.
  243. */
  244. puts("Reset Configuration Word (RCW):");
  245. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  246. u32 rcw = in_be32(&gur->rcwsr[i]);
  247. if ((i % 4) == 0)
  248. printf("\n %08x:", i * 4);
  249. printf(" %08x", rcw);
  250. }
  251. puts("\n");
  252. return 0;
  253. }
  254. #endif
  255. #ifdef CONFIG_FSL_ESDHC
  256. int cpu_mmc_init(bd_t *bis)
  257. {
  258. return fsl_esdhc_mmc_init(bis);
  259. }
  260. #endif
  261. int cpu_eth_init(bd_t *bis)
  262. {
  263. #if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
  264. tsec_standard_init(bis);
  265. #endif
  266. return 0;
  267. }
  268. int arch_cpu_init(void)
  269. {
  270. void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
  271. void *rcpm2_base =
  272. (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
  273. struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  274. u32 state;
  275. /*
  276. * The RCPM FSM state may not be reset after power-on.
  277. * So, reset them.
  278. */
  279. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
  280. CPMFSMSR_FSM_STATE_MASK;
  281. if (state != 0) {
  282. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
  283. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
  284. }
  285. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
  286. CPMFSMSR_FSM_STATE_MASK;
  287. if (state != 0) {
  288. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
  289. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
  290. }
  291. /*
  292. * After wakeup from deep sleep, Clear EPU registers
  293. * as early as possible to prevent from possible issue.
  294. * It's also safe to clear at normal boot.
  295. */
  296. fsl_epu_clean(epu_base);
  297. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
  298. return 0;
  299. }
  300. #ifdef CONFIG_ARMV7_NONSEC
  301. /* Set the address at which the secondary core starts from.*/
  302. void smp_set_core_boot_addr(unsigned long addr, int corenr)
  303. {
  304. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  305. out_be32(&gur->scratchrw[0], addr);
  306. }
  307. /* Release the secondary core from holdoff state and kick it */
  308. void smp_kick_all_cpus(void)
  309. {
  310. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  311. out_be32(&gur->brrl, 0x2);
  312. /*
  313. * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
  314. * So add a delay to wait bootrom execute WFE.
  315. */
  316. udelay(1);
  317. asm volatile("sev");
  318. }
  319. #endif
  320. void reset_cpu(ulong addr)
  321. {
  322. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  323. clrbits_be16(&wdog->wcr, WCR_SRS);
  324. while (1) {
  325. /*
  326. * Let the watchdog trigger
  327. */
  328. }
  329. }
  330. void arch_preboot_os(void)
  331. {
  332. unsigned long ctrl;
  333. /* Disable PL1 Physical Timer */
  334. asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
  335. ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
  336. asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
  337. }