max98090.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * max98090.c -- MAX98090 ALSA SoC Audio driver
  4. *
  5. * Copyright 2011 Maxim Integrated Products
  6. */
  7. #include <common.h>
  8. #include <audio_codec.h>
  9. #include <div64.h>
  10. #include <dm.h>
  11. #include <i2c.h>
  12. #include <i2s.h>
  13. #include <sound.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clk.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/power.h>
  19. #include "maxim_codec.h"
  20. #include "max98090.h"
  21. /*
  22. * Sets hw params for max98090
  23. *
  24. * @priv: max98090 information pointer
  25. * @rate: Sampling rate
  26. * @bits_per_sample: Bits per sample
  27. *
  28. * @return -EIO for error, 0 for success.
  29. */
  30. int max98090_hw_params(struct maxim_priv *priv, unsigned int rate,
  31. unsigned int bits_per_sample)
  32. {
  33. int error;
  34. unsigned char value;
  35. switch (bits_per_sample) {
  36. case 16:
  37. maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
  38. error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT,
  39. M98090_WS_MASK, 0);
  40. maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
  41. break;
  42. default:
  43. debug("%s: Illegal bits per sample %d.\n",
  44. __func__, bits_per_sample);
  45. return -1;
  46. }
  47. /* Update filter mode */
  48. if (rate < 240000)
  49. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  50. M98090_MODE_MASK, 0);
  51. else
  52. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  53. M98090_MODE_MASK, M98090_MODE_MASK);
  54. /* Update sample rate mode */
  55. if (rate < 50000)
  56. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  57. M98090_DHF_MASK, 0);
  58. else
  59. error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
  60. M98090_DHF_MASK, M98090_DHF_MASK);
  61. if (error < 0) {
  62. debug("%s: Error setting hardware params.\n", __func__);
  63. return -EIO;
  64. }
  65. priv->rate = rate;
  66. return 0;
  67. }
  68. /*
  69. * Configures Audio interface system clock for the given frequency
  70. *
  71. * @priv: max98090 information
  72. * @freq: Sampling frequency in Hz
  73. *
  74. * @return -EIO for error, 0 for success.
  75. */
  76. int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq)
  77. {
  78. int error = 0;
  79. /* Requested clock frequency is already setup */
  80. if (freq == priv->sysclk)
  81. return 0;
  82. /* Setup clocks for slave mode, and using the PLL
  83. * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
  84. * 0x02 (when master clk is 20MHz to 40MHz)..
  85. * 0x03 (when master clk is 40MHz to 60MHz)..
  86. */
  87. if (freq >= 10000000 && freq < 20000000) {
  88. error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
  89. M98090_PSCLK_DIV1);
  90. } else if (freq >= 20000000 && freq < 40000000) {
  91. error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
  92. M98090_PSCLK_DIV2);
  93. } else if (freq >= 40000000 && freq < 60000000) {
  94. error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
  95. M98090_PSCLK_DIV4);
  96. } else {
  97. debug("%s: Invalid master clock frequency\n", __func__);
  98. return -1;
  99. }
  100. debug("%s: Clock at %uHz\n", __func__, freq);
  101. if (error < 0)
  102. return -1;
  103. priv->sysclk = freq;
  104. return 0;
  105. }
  106. /*
  107. * Sets Max98090 I2S format
  108. *
  109. * @priv: max98090 information
  110. * @fmt: i2S format - supports a subset of the options defined in i2s.h.
  111. *
  112. * @return -EIO for error, 0 for success.
  113. */
  114. int max98090_set_fmt(struct maxim_priv *priv, int fmt)
  115. {
  116. u8 regval = 0;
  117. int error = 0;
  118. if (fmt == priv->fmt)
  119. return 0;
  120. priv->fmt = fmt;
  121. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  122. case SND_SOC_DAIFMT_CBS_CFS:
  123. /* Set to slave mode PLL - MAS mode off */
  124. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB,
  125. 0x00);
  126. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB,
  127. 0x00);
  128. error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE,
  129. M98090_USE_M1_MASK, 0);
  130. break;
  131. case SND_SOC_DAIFMT_CBM_CFM:
  132. /* Set to master mode */
  133. debug("Master mode not supported\n");
  134. break;
  135. case SND_SOC_DAIFMT_CBS_CFM:
  136. case SND_SOC_DAIFMT_CBM_CFS:
  137. default:
  138. debug("%s: Clock mode unsupported\n", __func__);
  139. return -EINVAL;
  140. }
  141. error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval);
  142. regval = 0;
  143. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  144. case SND_SOC_DAIFMT_I2S:
  145. regval |= M98090_DLY_MASK;
  146. break;
  147. case SND_SOC_DAIFMT_LEFT_J:
  148. break;
  149. case SND_SOC_DAIFMT_RIGHT_J:
  150. regval |= M98090_RJ_MASK;
  151. break;
  152. case SND_SOC_DAIFMT_DSP_A:
  153. /* Not supported mode */
  154. default:
  155. debug("%s: Unrecognized format.\n", __func__);
  156. return -EINVAL;
  157. }
  158. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  159. case SND_SOC_DAIFMT_NB_NF:
  160. break;
  161. case SND_SOC_DAIFMT_NB_IF:
  162. regval |= M98090_WCI_MASK;
  163. break;
  164. case SND_SOC_DAIFMT_IB_NF:
  165. regval |= M98090_BCI_MASK;
  166. break;
  167. case SND_SOC_DAIFMT_IB_IF:
  168. regval |= M98090_BCI_MASK | M98090_WCI_MASK;
  169. break;
  170. default:
  171. debug("%s: Unrecognized inversion settings.\n", __func__);
  172. return -EINVAL;
  173. }
  174. error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval);
  175. if (error < 0) {
  176. debug("%s: Error setting i2s format.\n", __func__);
  177. return -EIO;
  178. }
  179. return 0;
  180. }
  181. /*
  182. * resets the audio codec
  183. *
  184. * @priv: max98090 information
  185. * @return -EIO for error, 0 for success.
  186. */
  187. static int max98090_reset(struct maxim_priv *priv)
  188. {
  189. int ret;
  190. /*
  191. * Gracefully reset the DSP core and the codec hardware in a proper
  192. * sequence.
  193. */
  194. ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET,
  195. M98090_SWRESET_MASK);
  196. if (ret != 0) {
  197. debug("%s: Failed to reset DSP: %d\n", __func__, ret);
  198. return ret;
  199. }
  200. mdelay(20);
  201. return 0;
  202. }
  203. /*
  204. * Initialise max98090 codec device
  205. *
  206. * @priv: max98090 information
  207. *
  208. * @return -EIO for error, 0 for success.
  209. */
  210. int max98090_device_init(struct maxim_priv *priv)
  211. {
  212. unsigned char id;
  213. int error = 0;
  214. /* Enable codec clock */
  215. set_xclkout();
  216. /* reset the codec, the DSP core, and disable all interrupts */
  217. error = max98090_reset(priv);
  218. if (error != 0) {
  219. debug("Reset\n");
  220. return error;
  221. }
  222. /* initialize private data */
  223. priv->sysclk = -1U;
  224. priv->rate = -1U;
  225. priv->fmt = -1U;
  226. error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id);
  227. if (error < 0) {
  228. debug("%s: Failure reading hardware revision: %d\n",
  229. __func__, id);
  230. return -EIO;
  231. }
  232. debug("%s: Hardware revision: %d\n", __func__, id);
  233. return 0;
  234. }
  235. static int max98090_setup_interface(struct maxim_priv *priv)
  236. {
  237. unsigned char id;
  238. int error;
  239. /* Reading interrupt status to clear them */
  240. error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id);
  241. error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL,
  242. M98090_DACHP_MASK);
  243. error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL,
  244. M98090_VCM_MODE_MASK);
  245. error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1);
  246. error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2);
  247. error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25);
  248. error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
  249. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
  250. error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
  251. error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0);
  252. error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0);
  253. error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
  254. M98090_SDIEN_MASK);
  255. error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN,
  256. M98090_SHDNN_MASK);
  257. error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE,
  258. M98090_HPREN_MASK | M98090_HPLEN_MASK |
  259. M98090_SPREN_MASK | M98090_SPLEN_MASK |
  260. M98090_DAREN_MASK | M98090_DALEN_MASK);
  261. error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
  262. M98090_SDOEN_MASK | M98090_SDIEN_MASK);
  263. if (error < 0)
  264. return -EIO;
  265. return 0;
  266. }
  267. static int max98090_do_init(struct maxim_priv *priv, int sampling_rate,
  268. int mclk_freq, int bits_per_sample)
  269. {
  270. int ret = 0;
  271. ret = max98090_setup_interface(priv);
  272. if (ret < 0) {
  273. debug("%s: max98090 setup interface failed\n", __func__);
  274. return ret;
  275. }
  276. ret = max98090_set_sysclk(priv, mclk_freq);
  277. if (ret < 0) {
  278. debug("%s: max98090 codec set sys clock failed\n", __func__);
  279. return ret;
  280. }
  281. ret = max98090_hw_params(priv, sampling_rate, bits_per_sample);
  282. if (ret == 0) {
  283. ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S |
  284. SND_SOC_DAIFMT_NB_NF |
  285. SND_SOC_DAIFMT_CBS_CFS);
  286. }
  287. return ret;
  288. }
  289. static int max98090_set_params(struct udevice *dev, int interface, int rate,
  290. int mclk_freq, int bits_per_sample,
  291. uint channels)
  292. {
  293. struct maxim_priv *priv = dev_get_priv(dev);
  294. return max98090_do_init(priv, rate, mclk_freq, bits_per_sample);
  295. }
  296. static int max98090_probe(struct udevice *dev)
  297. {
  298. struct maxim_priv *priv = dev_get_priv(dev);
  299. int ret;
  300. priv->dev = dev;
  301. ret = max98090_device_init(priv);
  302. if (ret < 0) {
  303. debug("%s: max98090 codec chip init failed\n", __func__);
  304. return ret;
  305. }
  306. return 0;
  307. }
  308. static const struct audio_codec_ops max98090_ops = {
  309. .set_params = max98090_set_params,
  310. };
  311. static const struct udevice_id max98090_ids[] = {
  312. { .compatible = "maxim,max98090" },
  313. { }
  314. };
  315. U_BOOT_DRIVER(max98090) = {
  316. .name = "max98090",
  317. .id = UCLASS_AUDIO_CODEC,
  318. .of_match = max98090_ids,
  319. .probe = max98090_probe,
  320. .ops = &max98090_ops,
  321. .priv_auto_alloc_size = sizeof(struct maxim_priv),
  322. };