spi-nor.h 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. * Synced from Linux v4.19
  5. */
  6. #ifndef __LINUX_MTD_SPI_NOR_H
  7. #define __LINUX_MTD_SPI_NOR_H
  8. #include <mtd.h>
  9. #include <linux/bitops.h>
  10. #include <linux/mtd/cfi.h>
  11. #include <linux/mtd/mtd.h>
  12. /*
  13. * Manufacturer IDs
  14. *
  15. * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  16. * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  17. */
  18. #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
  19. #define SNOR_MFR_GIGADEVICE 0xc8
  20. #define SNOR_MFR_INTEL CFI_MFR_INTEL
  21. #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
  22. #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
  23. #define SNOR_MFR_ISSI CFI_MFR_PMC
  24. #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
  25. #define SNOR_MFR_SPANSION CFI_MFR_AMD
  26. #define SNOR_MFR_SST CFI_MFR_SST
  27. #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
  28. #define SNOR_MFR_CYPRESS 0x34
  29. /*
  30. * Note on opcode nomenclature: some opcodes have a format like
  31. * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  32. * of I/O lines used for the opcode, address, and data (respectively). The
  33. * FUNCTION has an optional suffix of '4', to represent an opcode which
  34. * requires a 4-byte (32-bit) address.
  35. */
  36. /* Flash opcodes. */
  37. #define SPINOR_OP_WREN 0x06 /* Write enable */
  38. #define SPINOR_OP_RDSR 0x05 /* Read status register */
  39. #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
  40. #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
  41. #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
  42. #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
  43. #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
  44. #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
  45. #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
  46. #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
  47. #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
  48. #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
  49. #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
  50. #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
  51. #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
  52. #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
  53. #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
  54. #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
  55. #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
  56. #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
  57. #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
  58. #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
  59. #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
  60. #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
  61. #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
  62. #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
  63. #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
  64. #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
  65. #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
  66. #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
  67. #define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
  68. #define SPINOR_OP_SRST 0x99 /* Software Reset */
  69. /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
  70. #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
  71. #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
  72. #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
  73. #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
  74. #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
  75. #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
  76. #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
  77. #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
  78. #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
  79. #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
  80. #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
  81. #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
  82. #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
  83. #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
  84. #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
  85. #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
  86. /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
  87. #define SPINOR_OP_READ_1_1_1_DTR 0x0d
  88. #define SPINOR_OP_READ_1_2_2_DTR 0xbd
  89. #define SPINOR_OP_READ_1_4_4_DTR 0xed
  90. #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
  91. #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
  92. #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
  93. /* Used for SST flashes only. */
  94. #define SPINOR_OP_BP 0x02 /* Byte program */
  95. #define SPINOR_OP_WRDI 0x04 /* Write disable */
  96. #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
  97. /* Used for SST26* flashes only. */
  98. #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
  99. #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
  100. /* Used for S3AN flashes only */
  101. #define SPINOR_OP_XSE 0x50 /* Sector erase */
  102. #define SPINOR_OP_XPP 0x82 /* Page program */
  103. #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
  104. #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
  105. #define XSR_RDY BIT(7) /* Ready */
  106. /* Used for Macronix and Winbond flashes. */
  107. #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
  108. #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
  109. /* Used for Spansion flashes only. */
  110. #define SPINOR_OP_BRWR 0x17 /* Bank register write */
  111. #define SPINOR_OP_BRRD 0x16 /* Bank register read */
  112. #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
  113. #define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */
  114. #define SPINOR_OP_RDAR 0x65 /* Read any register */
  115. #define SPINOR_OP_WRAR 0x71 /* Write any register */
  116. #define SPINOR_REG_ADDR_STR1V 0x00800000
  117. #define SPINOR_REG_ADDR_CFR1V 0x00800002
  118. #define SPINOR_REG_ADDR_CFR3V 0x00800004
  119. #define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */
  120. #define CFR3V_PGMBUF BIT(4) /* Program buffer size */
  121. /* Used for Micron flashes only. */
  122. #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
  123. #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
  124. #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
  125. #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
  126. #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
  127. #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
  128. #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
  129. #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR with DQS. */
  130. /* Status Register bits. */
  131. #define SR_WIP BIT(0) /* Write in progress */
  132. #define SR_WEL BIT(1) /* Write enable latch */
  133. /* meaning of other SR_* bits may differ between vendors */
  134. #define SR_BP0 BIT(2) /* Block protect 0 */
  135. #define SR_BP1 BIT(3) /* Block protect 1 */
  136. #define SR_BP2 BIT(4) /* Block protect 2 */
  137. #define SR_TB BIT(5) /* Top/Bottom protect */
  138. #define SR_SRWD BIT(7) /* SR write protect */
  139. /* Spansion/Cypress specific status bits */
  140. #define SR_E_ERR BIT(5)
  141. #define SR_P_ERR BIT(6)
  142. #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
  143. /* Enhanced Volatile Configuration Register bits */
  144. #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
  145. /* Flag Status Register bits */
  146. #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
  147. #define FSR_E_ERR BIT(5) /* Erase operation status */
  148. #define FSR_P_ERR BIT(4) /* Program operation status */
  149. #define FSR_PT_ERR BIT(1) /* Protection error bit */
  150. /* Configuration Register bits. */
  151. #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
  152. /* Status Register 2 bits. */
  153. #define SR2_QUAD_EN_BIT7 BIT(7)
  154. /* For Cypress flash. */
  155. #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
  156. #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
  157. #define SPINOR_OP_S28_SE_4K 0x21
  158. #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
  159. #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb
  160. #define SPINOR_REG_CYPRESS_CFR3V 0x00800004
  161. #define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */
  162. #define SPINOR_REG_CYPRESS_CFR3V_UNISECT BIT(3) /* Uniform sector mode */
  163. #define SPINOR_REG_CYPRESS_CFR5V 0x00800006
  164. #define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3
  165. #define SPINOR_OP_CYPRESS_RD_FAST 0xee
  166. /* Supported SPI protocols */
  167. #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
  168. #define SNOR_PROTO_INST_SHIFT 16
  169. #define SNOR_PROTO_INST(_nbits) \
  170. ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
  171. SNOR_PROTO_INST_MASK)
  172. #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
  173. #define SNOR_PROTO_ADDR_SHIFT 8
  174. #define SNOR_PROTO_ADDR(_nbits) \
  175. ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
  176. SNOR_PROTO_ADDR_MASK)
  177. #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
  178. #define SNOR_PROTO_DATA_SHIFT 0
  179. #define SNOR_PROTO_DATA(_nbits) \
  180. ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
  181. SNOR_PROTO_DATA_MASK)
  182. #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
  183. #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
  184. (SNOR_PROTO_INST(_inst_nbits) | \
  185. SNOR_PROTO_ADDR(_addr_nbits) | \
  186. SNOR_PROTO_DATA(_data_nbits))
  187. #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
  188. (SNOR_PROTO_IS_DTR | \
  189. SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
  190. enum spi_nor_protocol {
  191. SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
  192. SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
  193. SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
  194. SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
  195. SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
  196. SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
  197. SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
  198. SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
  199. SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
  200. SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
  201. SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
  202. SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
  203. SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
  204. SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
  205. SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
  206. };
  207. static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
  208. {
  209. return !!(proto & SNOR_PROTO_IS_DTR);
  210. }
  211. static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
  212. {
  213. return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
  214. SNOR_PROTO_INST_SHIFT;
  215. }
  216. static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
  217. {
  218. return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
  219. SNOR_PROTO_ADDR_SHIFT;
  220. }
  221. static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
  222. {
  223. return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
  224. SNOR_PROTO_DATA_SHIFT;
  225. }
  226. static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
  227. {
  228. return spi_nor_get_protocol_data_nbits(proto);
  229. }
  230. #define SPI_NOR_MAX_CMD_SIZE 8
  231. enum spi_nor_ops {
  232. SPI_NOR_OPS_READ = 0,
  233. SPI_NOR_OPS_WRITE,
  234. SPI_NOR_OPS_ERASE,
  235. SPI_NOR_OPS_LOCK,
  236. SPI_NOR_OPS_UNLOCK,
  237. };
  238. enum spi_nor_option_flags {
  239. SNOR_F_USE_FSR = BIT(0),
  240. SNOR_F_HAS_SR_TB = BIT(1),
  241. SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
  242. SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
  243. SNOR_F_READY_XSR_RDY = BIT(4),
  244. SNOR_F_USE_CLSR = BIT(5),
  245. SNOR_F_BROKEN_RESET = BIT(6),
  246. SNOR_F_SOFT_RESET = BIT(7),
  247. };
  248. struct spi_nor;
  249. /**
  250. * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
  251. * supported by the SPI controller (bus master).
  252. * @mask: the bitmask listing all the supported hw capabilies
  253. */
  254. struct spi_nor_hwcaps {
  255. u32 mask;
  256. };
  257. /*
  258. *(Fast) Read capabilities.
  259. * MUST be ordered by priority: the higher bit position, the higher priority.
  260. * As a matter of performances, it is relevant to use Octo SPI protocols first,
  261. * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
  262. * (Slow) Read.
  263. */
  264. #define SNOR_HWCAPS_READ_MASK GENMASK(15, 0)
  265. #define SNOR_HWCAPS_READ BIT(0)
  266. #define SNOR_HWCAPS_READ_FAST BIT(1)
  267. #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
  268. #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
  269. #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
  270. #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
  271. #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
  272. #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
  273. #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
  274. #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
  275. #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
  276. #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
  277. #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
  278. #define SNOR_HWCPAS_READ_OCTO GENMASK(15, 11)
  279. #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
  280. #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
  281. #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
  282. #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
  283. #define SNOR_HWCAPS_READ_8_8_8_DTR BIT(15)
  284. /*
  285. * Page Program capabilities.
  286. * MUST be ordered by priority: the higher bit position, the higher priority.
  287. * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
  288. * legacy SPI 1-1-1 protocol.
  289. * Note that Dual Page Programs are not supported because there is no existing
  290. * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
  291. * implements such commands.
  292. */
  293. #define SNOR_HWCAPS_PP_MASK GENMASK(23, 16)
  294. #define SNOR_HWCAPS_PP BIT(16)
  295. #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
  296. #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
  297. #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
  298. #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
  299. #define SNOR_HWCAPS_PP_OCTO GENMASK(23, 20)
  300. #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
  301. #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
  302. #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
  303. #define SNOR_HWCAPS_PP_8_8_8_DTR BIT(23)
  304. #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
  305. SNOR_HWCAPS_READ_4_4_4 | \
  306. SNOR_HWCAPS_READ_8_8_8 | \
  307. SNOR_HWCAPS_PP_4_4_4 | \
  308. SNOR_HWCAPS_PP_8_8_8)
  309. #define SNOR_HWCAPS_X_X_X_DTR (SNOR_HWCAPS_READ_8_8_8_DTR | \
  310. SNOR_HWCAPS_PP_8_8_8_DTR)
  311. #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
  312. SNOR_HWCAPS_READ_1_2_2_DTR | \
  313. SNOR_HWCAPS_READ_1_4_4_DTR | \
  314. SNOR_HWCAPS_READ_1_8_8_DTR)
  315. #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
  316. SNOR_HWCAPS_PP_MASK)
  317. struct spi_nor_read_command {
  318. u8 num_mode_clocks;
  319. u8 num_wait_states;
  320. u8 opcode;
  321. enum spi_nor_protocol proto;
  322. };
  323. struct spi_nor_pp_command {
  324. u8 opcode;
  325. enum spi_nor_protocol proto;
  326. };
  327. enum spi_nor_read_command_index {
  328. SNOR_CMD_READ,
  329. SNOR_CMD_READ_FAST,
  330. SNOR_CMD_READ_1_1_1_DTR,
  331. /* Dual SPI */
  332. SNOR_CMD_READ_1_1_2,
  333. SNOR_CMD_READ_1_2_2,
  334. SNOR_CMD_READ_2_2_2,
  335. SNOR_CMD_READ_1_2_2_DTR,
  336. /* Quad SPI */
  337. SNOR_CMD_READ_1_1_4,
  338. SNOR_CMD_READ_1_4_4,
  339. SNOR_CMD_READ_4_4_4,
  340. SNOR_CMD_READ_1_4_4_DTR,
  341. /* Octo SPI */
  342. SNOR_CMD_READ_1_1_8,
  343. SNOR_CMD_READ_1_8_8,
  344. SNOR_CMD_READ_8_8_8,
  345. SNOR_CMD_READ_1_8_8_DTR,
  346. SNOR_CMD_READ_8_8_8_DTR,
  347. SNOR_CMD_READ_MAX
  348. };
  349. enum spi_nor_pp_command_index {
  350. SNOR_CMD_PP,
  351. /* Quad SPI */
  352. SNOR_CMD_PP_1_1_4,
  353. SNOR_CMD_PP_1_4_4,
  354. SNOR_CMD_PP_4_4_4,
  355. /* Octo SPI */
  356. SNOR_CMD_PP_1_1_8,
  357. SNOR_CMD_PP_1_8_8,
  358. SNOR_CMD_PP_8_8_8,
  359. SNOR_CMD_PP_8_8_8_DTR,
  360. SNOR_CMD_PP_MAX
  361. };
  362. struct spi_nor_flash_parameter {
  363. u64 size;
  364. u32 page_size;
  365. u8 rdsr_dummy;
  366. u8 rdsr_addr_nbytes;
  367. struct spi_nor_hwcaps hwcaps;
  368. struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
  369. struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
  370. int (*quad_enable)(struct spi_nor *nor);
  371. };
  372. /**
  373. * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
  374. * @SPI_MEM_NOR_NONE: no extension. This is the default, and is used in Legacy
  375. * SPI mode
  376. * @SPI_MEM_NOR_REPEAT: the extension is same as the opcode
  377. * @SPI_MEM_NOR_INVERT: the extension is the bitwise inverse of the opcode
  378. * @SPI_MEM_NOR_HEX: the extension is any hex value. The command and opcode
  379. * combine to form a 16-bit opcode.
  380. */
  381. enum spi_nor_cmd_ext {
  382. SPI_NOR_EXT_NONE = 0,
  383. SPI_NOR_EXT_REPEAT,
  384. SPI_NOR_EXT_INVERT,
  385. SPI_NOR_EXT_HEX,
  386. };
  387. /**
  388. * struct flash_info - Forward declaration of a structure used internally by
  389. * spi_nor_scan()
  390. */
  391. struct flash_info;
  392. /*
  393. * TODO: Remove, once all users of spi_flash interface are moved to MTD
  394. *
  395. struct spi_flash {
  396. * Defined below (keep this text to enable searching for spi_flash decl)
  397. * }
  398. */
  399. #ifndef DT_PLAT_C
  400. #define spi_flash spi_nor
  401. #endif
  402. /**
  403. * struct spi_nor - Structure for defining a the SPI NOR layer
  404. * @mtd: point to a mtd_info structure
  405. * @lock: the lock for the read/write/erase/lock/unlock operations
  406. * @dev: point to a spi device, or a spi nor controller device.
  407. * @info: spi-nor part JDEC MFR id and other info
  408. * @manufacturer_sfdp: manufacturer specific SFDP table
  409. * @page_size: the page size of the SPI NOR
  410. * @addr_width: number of address bytes
  411. * @erase_opcode: the opcode for erasing a sector
  412. * @read_opcode: the read opcode
  413. * @read_dummy: the dummy needed by the read operation
  414. * @program_opcode: the program opcode
  415. * @rdsr_dummy dummy cycles needed for Read Status Register command.
  416. * @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register
  417. * command.
  418. * @bank_read_cmd: Bank read cmd
  419. * @bank_write_cmd: Bank write cmd
  420. * @bank_curr: Current flash bank
  421. * @sst_write_second: used by the SST write operation
  422. * @flags: flag options for the current SPI-NOR (SNOR_F_*)
  423. * @read_proto: the SPI protocol for read operations
  424. * @write_proto: the SPI protocol for write operations
  425. * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
  426. * @cmd_buf: used by the write_reg
  427. * @cmd_ext_type: the command opcode extension for DTR mode.
  428. * @fixups: flash-specific fixup hooks.
  429. * @prepare: [OPTIONAL] do some preparations for the
  430. * read/write/erase/lock/unlock operations
  431. * @unprepare: [OPTIONAL] do some post work after the
  432. * read/write/erase/lock/unlock operations
  433. * @read_reg: [DRIVER-SPECIFIC] read out the register
  434. * @write_reg: [DRIVER-SPECIFIC] write data to the register
  435. * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
  436. * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
  437. * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
  438. * at the offset @offs; if not provided by the driver,
  439. * spi-nor will send the erase opcode via write_reg()
  440. * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
  441. * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
  442. * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
  443. * completely locked
  444. * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
  445. * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode.
  446. * @ready: [FLASH-SPECIFIC] check if the flash is ready
  447. * @priv: the private data
  448. */
  449. struct spi_nor {
  450. struct mtd_info mtd;
  451. struct udevice *dev;
  452. struct spi_slave *spi;
  453. const struct flash_info *info;
  454. u8 *manufacturer_sfdp;
  455. u32 page_size;
  456. u8 addr_width;
  457. u8 erase_opcode;
  458. u8 read_opcode;
  459. u8 read_dummy;
  460. u8 program_opcode;
  461. u8 rdsr_dummy;
  462. u8 rdsr_addr_nbytes;
  463. #ifdef CONFIG_SPI_FLASH_BAR
  464. u8 bank_read_cmd;
  465. u8 bank_write_cmd;
  466. u8 bank_curr;
  467. #endif
  468. enum spi_nor_protocol read_proto;
  469. enum spi_nor_protocol write_proto;
  470. enum spi_nor_protocol reg_proto;
  471. bool sst_write_second;
  472. u32 flags;
  473. u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
  474. enum spi_nor_cmd_ext cmd_ext_type;
  475. struct spi_nor_fixups *fixups;
  476. int (*setup)(struct spi_nor *nor, const struct flash_info *info,
  477. const struct spi_nor_flash_parameter *params);
  478. int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  479. void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  480. int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  481. int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  482. ssize_t (*read)(struct spi_nor *nor, loff_t from,
  483. size_t len, u_char *read_buf);
  484. ssize_t (*write)(struct spi_nor *nor, loff_t to,
  485. size_t len, const u_char *write_buf);
  486. int (*erase)(struct spi_nor *nor, loff_t offs);
  487. int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  488. int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  489. int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  490. int (*quad_enable)(struct spi_nor *nor);
  491. int (*octal_dtr_enable)(struct spi_nor *nor);
  492. int (*ready)(struct spi_nor *nor);
  493. void *priv;
  494. char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
  495. /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
  496. const char *name;
  497. u32 size;
  498. u32 sector_size;
  499. u32 erase_size;
  500. };
  501. #ifndef __UBOOT__
  502. static inline void spi_nor_set_flash_node(struct spi_nor *nor,
  503. const struct device_node *np)
  504. {
  505. mtd_set_of_node(&nor->mtd, np);
  506. }
  507. static inline const struct
  508. device_node *spi_nor_get_flash_node(struct spi_nor *nor)
  509. {
  510. return mtd_get_of_node(&nor->mtd);
  511. }
  512. #endif /* __UBOOT__ */
  513. /**
  514. * spi_nor_scan() - scan the SPI NOR
  515. * @nor: the spi_nor structure
  516. *
  517. * The drivers can use this function to scan the SPI NOR.
  518. * In the scanning, it will try to get all the necessary information to
  519. * fill the mtd_info{} and the spi_nor{}.
  520. *
  521. * Return: 0 for success, others for failure.
  522. */
  523. int spi_nor_scan(struct spi_nor *nor);
  524. #if CONFIG_IS_ENABLED(SPI_FLASH_TINY)
  525. static inline int spi_nor_remove(struct spi_nor *nor)
  526. {
  527. return 0;
  528. }
  529. #else
  530. /**
  531. * spi_nor_remove() - perform cleanup before booting to the next stage
  532. * @nor: the spi_nor structure
  533. *
  534. * Return: 0 for success, -errno for failure.
  535. */
  536. int spi_nor_remove(struct spi_nor *nor);
  537. #endif
  538. #endif