spi-nor-core.c 102 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  4. * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  5. *
  6. * Copyright (C) 2005, Intec Automation Inc.
  7. * Copyright (C) 2014, Freescale Semiconductor, Inc.
  8. *
  9. * Synced from Linux v4.19
  10. */
  11. #include <common.h>
  12. #include <flash.h>
  13. #include <log.h>
  14. #include <watchdog.h>
  15. #include <dm.h>
  16. #include <dm/device_compat.h>
  17. #include <dm/devres.h>
  18. #include <linux/bitops.h>
  19. #include <linux/err.h>
  20. #include <linux/errno.h>
  21. #include <linux/log2.h>
  22. #include <linux/math64.h>
  23. #include <linux/sizes.h>
  24. #include <linux/bitfield.h>
  25. #include <linux/delay.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/spi-nor.h>
  28. #include <mtd/cfi_flash.h>
  29. #include <spi-mem.h>
  30. #include <spi.h>
  31. #include "sf_internal.h"
  32. /* Define max times to check status register before we give up. */
  33. /*
  34. * For everything but full-chip erase; probably could be much smaller, but kept
  35. * around for safety for now
  36. */
  37. #define HZ CONFIG_SYS_HZ
  38. #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  39. #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
  40. struct sfdp_parameter_header {
  41. u8 id_lsb;
  42. u8 minor;
  43. u8 major;
  44. u8 length; /* in double words */
  45. u8 parameter_table_pointer[3]; /* byte address */
  46. u8 id_msb;
  47. };
  48. #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
  49. #define SFDP_PARAM_HEADER_PTP(p) \
  50. (((p)->parameter_table_pointer[2] << 16) | \
  51. ((p)->parameter_table_pointer[1] << 8) | \
  52. ((p)->parameter_table_pointer[0] << 0))
  53. #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
  54. #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
  55. #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
  56. #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */
  57. #define SFDP_SIGNATURE 0x50444653U
  58. #define SFDP_JESD216_MAJOR 1
  59. #define SFDP_JESD216_MINOR 0
  60. #define SFDP_JESD216A_MINOR 5
  61. #define SFDP_JESD216B_MINOR 6
  62. struct sfdp_header {
  63. u32 signature; /* Ox50444653U <=> "SFDP" */
  64. u8 minor;
  65. u8 major;
  66. u8 nph; /* 0-base number of parameter headers */
  67. u8 unused;
  68. /* Basic Flash Parameter Table. */
  69. struct sfdp_parameter_header bfpt_header;
  70. };
  71. /* Basic Flash Parameter Table */
  72. /*
  73. * JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs.
  74. * They are indexed from 1 but C arrays are indexed from 0.
  75. */
  76. #define BFPT_DWORD(i) ((i) - 1)
  77. #define BFPT_DWORD_MAX 20
  78. /* The first version of JESB216 defined only 9 DWORDs. */
  79. #define BFPT_DWORD_MAX_JESD216 9
  80. #define BFPT_DWORD_MAX_JESD216B 16
  81. /* 1st DWORD. */
  82. #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
  83. #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
  84. #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
  85. #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
  86. #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
  87. #define BFPT_DWORD1_DTR BIT(19)
  88. #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
  89. #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
  90. #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
  91. /* 5th DWORD. */
  92. #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
  93. #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
  94. /* 11th DWORD. */
  95. #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
  96. #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
  97. /* 15th DWORD. */
  98. /*
  99. * (from JESD216 rev B)
  100. * Quad Enable Requirements (QER):
  101. * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
  102. * reads based on instruction. DQ3/HOLD# functions are hold during
  103. * instruction phase.
  104. * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
  105. * two data bytes where bit 1 of the second byte is one.
  106. * [...]
  107. * Writing only one byte to the status register has the side-effect of
  108. * clearing status register 2, including the QE bit. The 100b code is
  109. * used if writing one byte to the status register does not modify
  110. * status register 2.
  111. * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
  112. * one data byte where bit 6 is one.
  113. * [...]
  114. * - 011b: QE is bit 7 of status register 2. It is set via Write status
  115. * register 2 instruction 3Eh with one data byte where bit 7 is one.
  116. * [...]
  117. * The status register 2 is read using instruction 3Fh.
  118. * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
  119. * two data bytes where bit 1 of the second byte is one.
  120. * [...]
  121. * In contrast to the 001b code, writing one byte to the status
  122. * register does not modify status register 2.
  123. * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
  124. * Read Status instruction 05h. Status register2 is read using
  125. * instruction 35h. QE is set via Writ Status instruction 01h with
  126. * two data bytes where bit 1 of the second byte is one.
  127. * [...]
  128. */
  129. #define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
  130. #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
  131. #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
  132. #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
  133. #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
  134. #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
  135. #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
  136. #define BFPT_DWORD16_SOFT_RST BIT(12)
  137. #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29)
  138. #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */
  139. #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
  140. #define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
  141. #define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
  142. /* xSPI Profile 1.0 table (from JESD216D.01). */
  143. #define PROFILE1_DWORD1_RD_FAST_CMD GENMASK(15, 8)
  144. #define PROFILE1_DWORD1_RDSR_DUMMY BIT(28)
  145. #define PROFILE1_DWORD1_RDSR_ADDR_BYTES BIT(29)
  146. #define PROFILE1_DWORD4_DUMMY_200MHZ GENMASK(11, 7)
  147. #define PROFILE1_DWORD5_DUMMY_166MHZ GENMASK(31, 27)
  148. #define PROFILE1_DWORD5_DUMMY_133MHZ GENMASK(21, 17)
  149. #define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7)
  150. #define PROFILE1_DUMMY_DEFAULT 20
  151. struct sfdp_bfpt {
  152. u32 dwords[BFPT_DWORD_MAX];
  153. };
  154. /**
  155. * struct spi_nor_fixups - SPI NOR fixup hooks
  156. * @default_init: called after default flash parameters init. Used to tweak
  157. * flash parameters when information provided by the flash_info
  158. * table is incomplete or wrong.
  159. * @post_bfpt: called after the BFPT table has been parsed
  160. * @post_sfdp: called after SFDP has been parsed (is also called for SPI NORs
  161. * that do not support RDSFDP). Typically used to tweak various
  162. * parameters that could not be extracted by other means (i.e.
  163. * when information provided by the SFDP/flash_info tables are
  164. * incomplete or wrong).
  165. *
  166. * Those hooks can be used to tweak the SPI NOR configuration when the SFDP
  167. * table is broken or not available.
  168. */
  169. struct spi_nor_fixups {
  170. void (*default_init)(struct spi_nor *nor);
  171. int (*post_bfpt)(struct spi_nor *nor,
  172. const struct sfdp_parameter_header *bfpt_header,
  173. const struct sfdp_bfpt *bfpt,
  174. struct spi_nor_flash_parameter *params);
  175. void (*post_sfdp)(struct spi_nor *nor,
  176. struct spi_nor_flash_parameter *params);
  177. };
  178. #define SPI_NOR_SRST_SLEEP_LEN 200
  179. /**
  180. * spi_nor_get_cmd_ext() - Get the command opcode extension based on the
  181. * extension type.
  182. * @nor: pointer to a 'struct spi_nor'
  183. * @op: pointer to the 'struct spi_mem_op' whose properties
  184. * need to be initialized.
  185. *
  186. * Right now, only "repeat" and "invert" are supported.
  187. *
  188. * Return: The opcode extension.
  189. */
  190. static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
  191. const struct spi_mem_op *op)
  192. {
  193. switch (nor->cmd_ext_type) {
  194. case SPI_NOR_EXT_INVERT:
  195. return ~op->cmd.opcode;
  196. case SPI_NOR_EXT_REPEAT:
  197. return op->cmd.opcode;
  198. default:
  199. dev_dbg(nor->dev, "Unknown command extension type\n");
  200. return 0;
  201. }
  202. }
  203. /**
  204. * spi_nor_setup_op() - Set up common properties of a spi-mem op.
  205. * @nor: pointer to a 'struct spi_nor'
  206. * @op: pointer to the 'struct spi_mem_op' whose properties
  207. * need to be initialized.
  208. * @proto: the protocol from which the properties need to be set.
  209. */
  210. static void spi_nor_setup_op(const struct spi_nor *nor,
  211. struct spi_mem_op *op,
  212. const enum spi_nor_protocol proto)
  213. {
  214. u8 ext;
  215. op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);
  216. if (op->addr.nbytes)
  217. op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
  218. if (op->dummy.nbytes)
  219. op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
  220. if (op->data.nbytes)
  221. op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
  222. if (spi_nor_protocol_is_dtr(proto)) {
  223. /*
  224. * spi-mem supports mixed DTR modes, but right now we can only
  225. * have all phases either DTR or STR. IOW, spi-mem can have
  226. * something like 4S-4D-4D, but spi-nor can't. So, set all 4
  227. * phases to either DTR or STR.
  228. */
  229. op->cmd.dtr = op->addr.dtr = op->dummy.dtr =
  230. op->data.dtr = true;
  231. /* 2 bytes per clock cycle in DTR mode. */
  232. op->dummy.nbytes *= 2;
  233. ext = spi_nor_get_cmd_ext(nor, op);
  234. op->cmd.opcode = (op->cmd.opcode << 8) | ext;
  235. op->cmd.nbytes = 2;
  236. }
  237. }
  238. static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
  239. *op, void *buf)
  240. {
  241. if (op->data.dir == SPI_MEM_DATA_IN)
  242. op->data.buf.in = buf;
  243. else
  244. op->data.buf.out = buf;
  245. return spi_mem_exec_op(nor->spi, op);
  246. }
  247. static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
  248. {
  249. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 0),
  250. SPI_MEM_OP_NO_ADDR,
  251. SPI_MEM_OP_NO_DUMMY,
  252. SPI_MEM_OP_DATA_IN(len, NULL, 0));
  253. int ret;
  254. spi_nor_setup_op(nor, &op, nor->reg_proto);
  255. ret = spi_nor_read_write_reg(nor, &op, val);
  256. if (ret < 0)
  257. dev_dbg(nor->dev, "error %d reading %x\n", ret, code);
  258. return ret;
  259. }
  260. static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  261. {
  262. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0),
  263. SPI_MEM_OP_NO_ADDR,
  264. SPI_MEM_OP_NO_DUMMY,
  265. SPI_MEM_OP_DATA_OUT(len, NULL, 0));
  266. spi_nor_setup_op(nor, &op, nor->reg_proto);
  267. if (len == 0)
  268. op.data.dir = SPI_MEM_NO_DATA;
  269. return spi_nor_read_write_reg(nor, &op, buf);
  270. }
  271. #ifdef CONFIG_SPI_FLASH_SPANSION
  272. static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy,
  273. u8 *val)
  274. {
  275. struct spi_mem_op op =
  276. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1),
  277. SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
  278. SPI_MEM_OP_DUMMY(dummy / 8, 1),
  279. SPI_MEM_OP_DATA_IN(1, NULL, 1));
  280. return spi_nor_read_write_reg(nor, &op, val);
  281. }
  282. static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val)
  283. {
  284. struct spi_mem_op op =
  285. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1),
  286. SPI_MEM_OP_ADDR(nor->addr_width, addr, 1),
  287. SPI_MEM_OP_NO_DUMMY,
  288. SPI_MEM_OP_DATA_OUT(1, NULL, 1));
  289. return spi_nor_read_write_reg(nor, &op, &val);
  290. }
  291. #endif
  292. static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
  293. u_char *buf)
  294. {
  295. struct spi_mem_op op =
  296. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
  297. SPI_MEM_OP_ADDR(nor->addr_width, from, 0),
  298. SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
  299. SPI_MEM_OP_DATA_IN(len, buf, 0));
  300. size_t remaining = len;
  301. int ret;
  302. spi_nor_setup_op(nor, &op, nor->read_proto);
  303. /* convert the dummy cycles to the number of bytes */
  304. op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
  305. if (spi_nor_protocol_is_dtr(nor->read_proto))
  306. op.dummy.nbytes *= 2;
  307. while (remaining) {
  308. op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
  309. ret = spi_mem_adjust_op_size(nor->spi, &op);
  310. if (ret)
  311. return ret;
  312. ret = spi_mem_exec_op(nor->spi, &op);
  313. if (ret)
  314. return ret;
  315. op.addr.val += op.data.nbytes;
  316. remaining -= op.data.nbytes;
  317. op.data.buf.in += op.data.nbytes;
  318. }
  319. return len;
  320. }
  321. static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
  322. const u_char *buf)
  323. {
  324. struct spi_mem_op op =
  325. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
  326. SPI_MEM_OP_ADDR(nor->addr_width, to, 0),
  327. SPI_MEM_OP_NO_DUMMY,
  328. SPI_MEM_OP_DATA_OUT(len, buf, 0));
  329. int ret;
  330. if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
  331. op.addr.nbytes = 0;
  332. spi_nor_setup_op(nor, &op, nor->write_proto);
  333. ret = spi_mem_adjust_op_size(nor->spi, &op);
  334. if (ret)
  335. return ret;
  336. op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes;
  337. ret = spi_mem_exec_op(nor->spi, &op);
  338. if (ret)
  339. return ret;
  340. return op.data.nbytes;
  341. }
  342. /*
  343. * Read the status register, returning its value in the location
  344. * Return the status register value.
  345. * Returns negative if error occurred.
  346. */
  347. static int read_sr(struct spi_nor *nor)
  348. {
  349. struct spi_mem_op op;
  350. int ret;
  351. u8 val[2];
  352. u8 addr_nbytes, dummy;
  353. if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
  354. addr_nbytes = nor->rdsr_addr_nbytes;
  355. dummy = nor->rdsr_dummy;
  356. } else {
  357. addr_nbytes = 0;
  358. dummy = 0;
  359. }
  360. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 0),
  361. SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
  362. SPI_MEM_OP_DUMMY(dummy, 0),
  363. SPI_MEM_OP_DATA_IN(1, NULL, 0));
  364. spi_nor_setup_op(nor, &op, nor->reg_proto);
  365. /*
  366. * We don't want to read only one byte in DTR mode. So, read 2 and then
  367. * discard the second byte.
  368. */
  369. if (spi_nor_protocol_is_dtr(nor->reg_proto))
  370. op.data.nbytes = 2;
  371. ret = spi_nor_read_write_reg(nor, &op, val);
  372. if (ret < 0) {
  373. pr_debug("error %d reading SR\n", (int)ret);
  374. return ret;
  375. }
  376. return *val;
  377. }
  378. /*
  379. * Read the flag status register, returning its value in the location
  380. * Return the status register value.
  381. * Returns negative if error occurred.
  382. */
  383. static int read_fsr(struct spi_nor *nor)
  384. {
  385. struct spi_mem_op op;
  386. int ret;
  387. u8 val[2];
  388. u8 addr_nbytes, dummy;
  389. if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
  390. addr_nbytes = nor->rdsr_addr_nbytes;
  391. dummy = nor->rdsr_dummy;
  392. } else {
  393. addr_nbytes = 0;
  394. dummy = 0;
  395. }
  396. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0),
  397. SPI_MEM_OP_ADDR(addr_nbytes, 0, 0),
  398. SPI_MEM_OP_DUMMY(dummy, 0),
  399. SPI_MEM_OP_DATA_IN(1, NULL, 0));
  400. spi_nor_setup_op(nor, &op, nor->reg_proto);
  401. /*
  402. * We don't want to read only one byte in DTR mode. So, read 2 and then
  403. * discard the second byte.
  404. */
  405. if (spi_nor_protocol_is_dtr(nor->reg_proto))
  406. op.data.nbytes = 2;
  407. ret = spi_nor_read_write_reg(nor, &op, val);
  408. if (ret < 0) {
  409. pr_debug("error %d reading FSR\n", ret);
  410. return ret;
  411. }
  412. return *val;
  413. }
  414. /*
  415. * Read configuration register, returning its value in the
  416. * location. Return the configuration register value.
  417. * Returns negative if error occurred.
  418. */
  419. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  420. static int read_cr(struct spi_nor *nor)
  421. {
  422. int ret;
  423. u8 val;
  424. ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
  425. if (ret < 0) {
  426. dev_dbg(nor->dev, "error %d reading CR\n", ret);
  427. return ret;
  428. }
  429. return val;
  430. }
  431. #endif
  432. /*
  433. * Write status register 1 byte
  434. * Returns negative if error occurred.
  435. */
  436. static int write_sr(struct spi_nor *nor, u8 val)
  437. {
  438. nor->cmd_buf[0] = val;
  439. return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  440. }
  441. /*
  442. * Set write enable latch with Write Enable command.
  443. * Returns negative if error occurred.
  444. */
  445. static int write_enable(struct spi_nor *nor)
  446. {
  447. return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  448. }
  449. /*
  450. * Send write disable instruction to the chip.
  451. */
  452. static int write_disable(struct spi_nor *nor)
  453. {
  454. return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  455. }
  456. static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  457. {
  458. return mtd->priv;
  459. }
  460. #ifndef CONFIG_SPI_FLASH_BAR
  461. static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
  462. {
  463. size_t i;
  464. for (i = 0; i < size; i++)
  465. if (table[i][0] == opcode)
  466. return table[i][1];
  467. /* No conversion found, keep input op code. */
  468. return opcode;
  469. }
  470. static u8 spi_nor_convert_3to4_read(u8 opcode)
  471. {
  472. static const u8 spi_nor_3to4_read[][2] = {
  473. { SPINOR_OP_READ, SPINOR_OP_READ_4B },
  474. { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
  475. { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
  476. { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
  477. { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
  478. { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
  479. { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
  480. { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
  481. { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
  482. { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
  483. { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },
  484. };
  485. return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
  486. ARRAY_SIZE(spi_nor_3to4_read));
  487. }
  488. static u8 spi_nor_convert_3to4_program(u8 opcode)
  489. {
  490. static const u8 spi_nor_3to4_program[][2] = {
  491. { SPINOR_OP_PP, SPINOR_OP_PP_4B },
  492. { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
  493. { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
  494. { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
  495. { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
  496. };
  497. return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
  498. ARRAY_SIZE(spi_nor_3to4_program));
  499. }
  500. static u8 spi_nor_convert_3to4_erase(u8 opcode)
  501. {
  502. static const u8 spi_nor_3to4_erase[][2] = {
  503. { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
  504. { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
  505. { SPINOR_OP_SE, SPINOR_OP_SE_4B },
  506. };
  507. return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
  508. ARRAY_SIZE(spi_nor_3to4_erase));
  509. }
  510. static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
  511. const struct flash_info *info)
  512. {
  513. /* Do some manufacturer fixups first */
  514. switch (JEDEC_MFR(info)) {
  515. case SNOR_MFR_SPANSION:
  516. /* No small sector erase for 4-byte command set */
  517. nor->erase_opcode = SPINOR_OP_SE;
  518. nor->mtd.erasesize = info->sector_size;
  519. break;
  520. default:
  521. break;
  522. }
  523. nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
  524. nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
  525. nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
  526. }
  527. #endif /* !CONFIG_SPI_FLASH_BAR */
  528. /* Enable/disable 4-byte addressing mode. */
  529. static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  530. int enable)
  531. {
  532. int status;
  533. bool need_wren = false;
  534. u8 cmd;
  535. switch (JEDEC_MFR(info)) {
  536. case SNOR_MFR_ST:
  537. case SNOR_MFR_MICRON:
  538. /* Some Micron need WREN command; all will accept it */
  539. need_wren = true;
  540. case SNOR_MFR_ISSI:
  541. case SNOR_MFR_MACRONIX:
  542. case SNOR_MFR_WINBOND:
  543. if (need_wren)
  544. write_enable(nor);
  545. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  546. status = nor->write_reg(nor, cmd, NULL, 0);
  547. if (need_wren)
  548. write_disable(nor);
  549. if (!status && !enable &&
  550. JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
  551. /*
  552. * On Winbond W25Q256FV, leaving 4byte mode causes
  553. * the Extended Address Register to be set to 1, so all
  554. * 3-byte-address reads come from the second 16M.
  555. * We must clear the register to enable normal behavior.
  556. */
  557. write_enable(nor);
  558. nor->cmd_buf[0] = 0;
  559. nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
  560. write_disable(nor);
  561. }
  562. return status;
  563. case SNOR_MFR_CYPRESS:
  564. cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS;
  565. return nor->write_reg(nor, cmd, NULL, 0);
  566. default:
  567. /* Spansion style */
  568. nor->cmd_buf[0] = enable << 7;
  569. return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  570. }
  571. }
  572. #ifdef CONFIG_SPI_FLASH_SPANSION
  573. /*
  574. * Read status register 1 by using Read Any Register command to support multi
  575. * die package parts.
  576. */
  577. static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
  578. {
  579. u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V;
  580. u8 sr;
  581. int ret;
  582. ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr);
  583. if (ret < 0)
  584. return ret;
  585. if (sr & (SR_E_ERR | SR_P_ERR)) {
  586. if (sr & SR_E_ERR)
  587. dev_dbg(nor->dev, "Erase Error occurred\n");
  588. else
  589. dev_dbg(nor->dev, "Programming Error occurred\n");
  590. nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
  591. return -EIO;
  592. }
  593. return !(sr & SR_WIP);
  594. }
  595. #endif
  596. static int spi_nor_sr_ready(struct spi_nor *nor)
  597. {
  598. int sr = read_sr(nor);
  599. if (sr < 0)
  600. return sr;
  601. if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
  602. if (sr & SR_E_ERR)
  603. dev_dbg(nor->dev, "Erase Error occurred\n");
  604. else
  605. dev_dbg(nor->dev, "Programming Error occurred\n");
  606. nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
  607. return -EIO;
  608. }
  609. return !(sr & SR_WIP);
  610. }
  611. static int spi_nor_fsr_ready(struct spi_nor *nor)
  612. {
  613. int fsr = read_fsr(nor);
  614. if (fsr < 0)
  615. return fsr;
  616. if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
  617. if (fsr & FSR_E_ERR)
  618. dev_err(nor->dev, "Erase operation failed.\n");
  619. else
  620. dev_err(nor->dev, "Program operation failed.\n");
  621. if (fsr & FSR_PT_ERR)
  622. dev_err(nor->dev,
  623. "Attempted to modify a protected sector.\n");
  624. nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
  625. return -EIO;
  626. }
  627. return fsr & FSR_READY;
  628. }
  629. static int spi_nor_default_ready(struct spi_nor *nor)
  630. {
  631. int sr, fsr;
  632. sr = spi_nor_sr_ready(nor);
  633. if (sr < 0)
  634. return sr;
  635. fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  636. if (fsr < 0)
  637. return fsr;
  638. return sr && fsr;
  639. }
  640. static int spi_nor_ready(struct spi_nor *nor)
  641. {
  642. if (nor->ready)
  643. return nor->ready(nor);
  644. return spi_nor_default_ready(nor);
  645. }
  646. /*
  647. * Service routine to read status register until ready, or timeout occurs.
  648. * Returns non-zero if error.
  649. */
  650. static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  651. unsigned long timeout)
  652. {
  653. unsigned long timebase;
  654. int ret;
  655. timebase = get_timer(0);
  656. while (get_timer(timebase) < timeout) {
  657. ret = spi_nor_ready(nor);
  658. if (ret < 0)
  659. return ret;
  660. if (ret)
  661. return 0;
  662. }
  663. dev_err(nor->dev, "flash operation timed out\n");
  664. return -ETIMEDOUT;
  665. }
  666. static int spi_nor_wait_till_ready(struct spi_nor *nor)
  667. {
  668. return spi_nor_wait_till_ready_with_timeout(nor,
  669. DEFAULT_READY_WAIT_JIFFIES);
  670. }
  671. #ifdef CONFIG_SPI_FLASH_BAR
  672. /*
  673. * This "clean_bar" is necessary in a situation when one was accessing
  674. * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
  675. *
  676. * After it the BA24 bit shall be cleared to allow access to correct
  677. * memory region after SW reset (by calling "reset" command).
  678. *
  679. * Otherwise, the BA24 bit may be left set and then after reset, the
  680. * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
  681. */
  682. static int clean_bar(struct spi_nor *nor)
  683. {
  684. u8 cmd, bank_sel = 0;
  685. if (nor->bank_curr == 0)
  686. return 0;
  687. cmd = nor->bank_write_cmd;
  688. nor->bank_curr = 0;
  689. write_enable(nor);
  690. return nor->write_reg(nor, cmd, &bank_sel, 1);
  691. }
  692. static int write_bar(struct spi_nor *nor, u32 offset)
  693. {
  694. u8 cmd, bank_sel;
  695. int ret;
  696. bank_sel = offset / SZ_16M;
  697. if (bank_sel == nor->bank_curr)
  698. goto bar_end;
  699. cmd = nor->bank_write_cmd;
  700. write_enable(nor);
  701. ret = nor->write_reg(nor, cmd, &bank_sel, 1);
  702. if (ret < 0) {
  703. debug("SF: fail to write bank register\n");
  704. return ret;
  705. }
  706. bar_end:
  707. nor->bank_curr = bank_sel;
  708. return nor->bank_curr;
  709. }
  710. static int read_bar(struct spi_nor *nor, const struct flash_info *info)
  711. {
  712. u8 curr_bank = 0;
  713. int ret;
  714. switch (JEDEC_MFR(info)) {
  715. case SNOR_MFR_SPANSION:
  716. nor->bank_read_cmd = SPINOR_OP_BRRD;
  717. nor->bank_write_cmd = SPINOR_OP_BRWR;
  718. break;
  719. default:
  720. nor->bank_read_cmd = SPINOR_OP_RDEAR;
  721. nor->bank_write_cmd = SPINOR_OP_WREAR;
  722. }
  723. ret = nor->read_reg(nor, nor->bank_read_cmd,
  724. &curr_bank, 1);
  725. if (ret) {
  726. debug("SF: fail to read bank addr register\n");
  727. return ret;
  728. }
  729. nor->bank_curr = curr_bank;
  730. return 0;
  731. }
  732. #endif
  733. /*
  734. * Initiate the erasure of a single sector. Returns the number of bytes erased
  735. * on success, a negative error code on error.
  736. */
  737. static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
  738. {
  739. struct spi_mem_op op =
  740. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
  741. SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
  742. SPI_MEM_OP_NO_DUMMY,
  743. SPI_MEM_OP_NO_DATA);
  744. int ret;
  745. spi_nor_setup_op(nor, &op, nor->write_proto);
  746. if (nor->erase)
  747. return nor->erase(nor, addr);
  748. /*
  749. * Default implementation, if driver doesn't have a specialized HW
  750. * control
  751. */
  752. ret = spi_mem_exec_op(nor->spi, &op);
  753. if (ret)
  754. return ret;
  755. return nor->mtd.erasesize;
  756. }
  757. /*
  758. * Erase an address range on the nor chip. The address range may extend
  759. * one or more erase sectors. Return an error is there is a problem erasing.
  760. */
  761. static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
  762. {
  763. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  764. u32 addr, len, rem;
  765. int ret;
  766. dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
  767. (long long)instr->len);
  768. if (!instr->len)
  769. return 0;
  770. div_u64_rem(instr->len, mtd->erasesize, &rem);
  771. if (rem)
  772. return -EINVAL;
  773. addr = instr->addr;
  774. len = instr->len;
  775. while (len) {
  776. WATCHDOG_RESET();
  777. #ifdef CONFIG_SPI_FLASH_BAR
  778. ret = write_bar(nor, addr);
  779. if (ret < 0)
  780. return ret;
  781. #endif
  782. write_enable(nor);
  783. ret = spi_nor_erase_sector(nor, addr);
  784. if (ret < 0)
  785. goto erase_err;
  786. addr += ret;
  787. len -= ret;
  788. ret = spi_nor_wait_till_ready(nor);
  789. if (ret)
  790. goto erase_err;
  791. }
  792. erase_err:
  793. #ifdef CONFIG_SPI_FLASH_BAR
  794. ret = clean_bar(nor);
  795. #endif
  796. write_disable(nor);
  797. return ret;
  798. }
  799. #ifdef CONFIG_SPI_FLASH_SPANSION
  800. /**
  801. * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress
  802. * chips
  803. * @nor: pointer to a 'struct spi_nor'
  804. * @addr: address of the sector to erase
  805. * @opcode_4k: opcode for 4K sector erase
  806. * @ovlsz_top: size of overlaid portion at the top address
  807. * @ovlsz_btm: size of overlaid portion at the bottom address
  808. *
  809. * Erase an address range on the nor chip that can contain 4KB sectors overlaid
  810. * on top and/or bottom. The appropriate erase opcode and size are chosen by
  811. * address to erase and size of overlaid portion.
  812. *
  813. * Return: number of bytes erased on success, -errno otherwise.
  814. */
  815. static int spansion_erase_non_uniform(struct spi_nor *nor, u32 addr,
  816. u8 opcode_4k, u32 ovlsz_top,
  817. u32 ovlsz_btm)
  818. {
  819. struct spi_mem_op op =
  820. SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 0),
  821. SPI_MEM_OP_ADDR(nor->addr_width, addr, 0),
  822. SPI_MEM_OP_NO_DUMMY,
  823. SPI_MEM_OP_NO_DATA);
  824. struct mtd_info *mtd = &nor->mtd;
  825. u32 erasesize;
  826. int ret;
  827. /* 4KB sectors */
  828. if (op.addr.val < ovlsz_btm ||
  829. op.addr.val >= mtd->size - ovlsz_top) {
  830. op.cmd.opcode = opcode_4k;
  831. erasesize = SZ_4K;
  832. /* Non-overlaid portion in the normal sector at the bottom */
  833. } else if (op.addr.val == ovlsz_btm) {
  834. op.cmd.opcode = nor->erase_opcode;
  835. erasesize = mtd->erasesize - ovlsz_btm;
  836. /* Non-overlaid portion in the normal sector at the top */
  837. } else if (op.addr.val == mtd->size - mtd->erasesize) {
  838. op.cmd.opcode = nor->erase_opcode;
  839. erasesize = mtd->erasesize - ovlsz_top;
  840. /* Normal sectors */
  841. } else {
  842. op.cmd.opcode = nor->erase_opcode;
  843. erasesize = mtd->erasesize;
  844. }
  845. spi_nor_setup_op(nor, &op, nor->write_proto);
  846. ret = spi_mem_exec_op(nor->spi, &op);
  847. if (ret)
  848. return ret;
  849. return erasesize;
  850. }
  851. #endif
  852. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  853. /* Write status register and ensure bits in mask match written values */
  854. static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
  855. {
  856. int ret;
  857. write_enable(nor);
  858. ret = write_sr(nor, status_new);
  859. if (ret)
  860. return ret;
  861. ret = spi_nor_wait_till_ready(nor);
  862. if (ret)
  863. return ret;
  864. ret = read_sr(nor);
  865. if (ret < 0)
  866. return ret;
  867. return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
  868. }
  869. static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
  870. uint64_t *len)
  871. {
  872. struct mtd_info *mtd = &nor->mtd;
  873. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  874. int shift = ffs(mask) - 1;
  875. int pow;
  876. if (!(sr & mask)) {
  877. /* No protection */
  878. *ofs = 0;
  879. *len = 0;
  880. } else {
  881. pow = ((sr & mask) ^ mask) >> shift;
  882. *len = mtd->size >> pow;
  883. if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
  884. *ofs = 0;
  885. else
  886. *ofs = mtd->size - *len;
  887. }
  888. }
  889. /*
  890. * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
  891. * @locked is false); 0 otherwise
  892. */
  893. static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
  894. u8 sr, bool locked)
  895. {
  896. loff_t lock_offs;
  897. uint64_t lock_len;
  898. if (!len)
  899. return 1;
  900. stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
  901. if (locked)
  902. /* Requested range is a sub-range of locked range */
  903. return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  904. else
  905. /* Requested range does not overlap with locked range */
  906. return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
  907. }
  908. static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  909. u8 sr)
  910. {
  911. return stm_check_lock_status_sr(nor, ofs, len, sr, true);
  912. }
  913. static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  914. u8 sr)
  915. {
  916. return stm_check_lock_status_sr(nor, ofs, len, sr, false);
  917. }
  918. /*
  919. * Lock a region of the flash. Compatible with ST Micro and similar flash.
  920. * Supports the block protection bits BP{0,1,2} in the status register
  921. * (SR). Does not support these features found in newer SR bitfields:
  922. * - SEC: sector/block protect - only handle SEC=0 (block protect)
  923. * - CMP: complement protect - only support CMP=0 (range is not complemented)
  924. *
  925. * Support for the following is provided conditionally for some flash:
  926. * - TB: top/bottom protect
  927. *
  928. * Sample table portion for 8MB flash (Winbond w25q64fw):
  929. *
  930. * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  931. * --------------------------------------------------------------------------
  932. * X | X | 0 | 0 | 0 | NONE | NONE
  933. * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  934. * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  935. * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  936. * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  937. * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  938. * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  939. * X | X | 1 | 1 | 1 | 8 MB | ALL
  940. * ------|-------|-------|-------|-------|---------------|-------------------
  941. * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64
  942. * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32
  943. * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16
  944. * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8
  945. * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4
  946. * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2
  947. *
  948. * Returns negative on errors, 0 on success.
  949. */
  950. static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  951. {
  952. struct mtd_info *mtd = &nor->mtd;
  953. int status_old, status_new;
  954. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  955. u8 shift = ffs(mask) - 1, pow, val;
  956. loff_t lock_len;
  957. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  958. bool use_top;
  959. status_old = read_sr(nor);
  960. if (status_old < 0)
  961. return status_old;
  962. /* If nothing in our range is unlocked, we don't need to do anything */
  963. if (stm_is_locked_sr(nor, ofs, len, status_old))
  964. return 0;
  965. /* If anything below us is unlocked, we can't use 'bottom' protection */
  966. if (!stm_is_locked_sr(nor, 0, ofs, status_old))
  967. can_be_bottom = false;
  968. /* If anything above us is unlocked, we can't use 'top' protection */
  969. if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
  970. status_old))
  971. can_be_top = false;
  972. if (!can_be_bottom && !can_be_top)
  973. return -EINVAL;
  974. /* Prefer top, if both are valid */
  975. use_top = can_be_top;
  976. /* lock_len: length of region that should end up locked */
  977. if (use_top)
  978. lock_len = mtd->size - ofs;
  979. else
  980. lock_len = ofs + len;
  981. /*
  982. * Need smallest pow such that:
  983. *
  984. * 1 / (2^pow) <= (len / size)
  985. *
  986. * so (assuming power-of-2 size) we do:
  987. *
  988. * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  989. */
  990. pow = ilog2(mtd->size) - ilog2(lock_len);
  991. val = mask - (pow << shift);
  992. if (val & ~mask)
  993. return -EINVAL;
  994. /* Don't "lock" with no region! */
  995. if (!(val & mask))
  996. return -EINVAL;
  997. status_new = (status_old & ~mask & ~SR_TB) | val;
  998. /* Disallow further writes if WP pin is asserted */
  999. status_new |= SR_SRWD;
  1000. if (!use_top)
  1001. status_new |= SR_TB;
  1002. /* Don't bother if they're the same */
  1003. if (status_new == status_old)
  1004. return 0;
  1005. /* Only modify protection if it will not unlock other areas */
  1006. if ((status_new & mask) < (status_old & mask))
  1007. return -EINVAL;
  1008. return write_sr_and_check(nor, status_new, mask);
  1009. }
  1010. /*
  1011. * Unlock a region of the flash. See stm_lock() for more info
  1012. *
  1013. * Returns negative on errors, 0 on success.
  1014. */
  1015. static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1016. {
  1017. struct mtd_info *mtd = &nor->mtd;
  1018. int status_old, status_new;
  1019. u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  1020. u8 shift = ffs(mask) - 1, pow, val;
  1021. loff_t lock_len;
  1022. bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
  1023. bool use_top;
  1024. status_old = read_sr(nor);
  1025. if (status_old < 0)
  1026. return status_old;
  1027. /* If nothing in our range is locked, we don't need to do anything */
  1028. if (stm_is_unlocked_sr(nor, ofs, len, status_old))
  1029. return 0;
  1030. /* If anything below us is locked, we can't use 'top' protection */
  1031. if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
  1032. can_be_top = false;
  1033. /* If anything above us is locked, we can't use 'bottom' protection */
  1034. if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
  1035. status_old))
  1036. can_be_bottom = false;
  1037. if (!can_be_bottom && !can_be_top)
  1038. return -EINVAL;
  1039. /* Prefer top, if both are valid */
  1040. use_top = can_be_top;
  1041. /* lock_len: length of region that should remain locked */
  1042. if (use_top)
  1043. lock_len = mtd->size - (ofs + len);
  1044. else
  1045. lock_len = ofs;
  1046. /*
  1047. * Need largest pow such that:
  1048. *
  1049. * 1 / (2^pow) >= (len / size)
  1050. *
  1051. * so (assuming power-of-2 size) we do:
  1052. *
  1053. * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  1054. */
  1055. pow = ilog2(mtd->size) - order_base_2(lock_len);
  1056. if (lock_len == 0) {
  1057. val = 0; /* fully unlocked */
  1058. } else {
  1059. val = mask - (pow << shift);
  1060. /* Some power-of-two sizes are not supported */
  1061. if (val & ~mask)
  1062. return -EINVAL;
  1063. }
  1064. status_new = (status_old & ~mask & ~SR_TB) | val;
  1065. /* Don't protect status register if we're fully unlocked */
  1066. if (lock_len == 0)
  1067. status_new &= ~SR_SRWD;
  1068. if (!use_top)
  1069. status_new |= SR_TB;
  1070. /* Don't bother if they're the same */
  1071. if (status_new == status_old)
  1072. return 0;
  1073. /* Only modify protection if it will not lock other areas */
  1074. if ((status_new & mask) > (status_old & mask))
  1075. return -EINVAL;
  1076. return write_sr_and_check(nor, status_new, mask);
  1077. }
  1078. /*
  1079. * Check if a region of the flash is (completely) locked. See stm_lock() for
  1080. * more info.
  1081. *
  1082. * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  1083. * negative on errors.
  1084. */
  1085. static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1086. {
  1087. int status;
  1088. status = read_sr(nor);
  1089. if (status < 0)
  1090. return status;
  1091. return stm_is_locked_sr(nor, ofs, len, status);
  1092. }
  1093. #endif /* CONFIG_SPI_FLASH_STMICRO */
  1094. static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  1095. {
  1096. int tmp;
  1097. u8 id[SPI_NOR_MAX_ID_LEN];
  1098. const struct flash_info *info;
  1099. tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  1100. if (tmp < 0) {
  1101. dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
  1102. return ERR_PTR(tmp);
  1103. }
  1104. info = spi_nor_ids;
  1105. for (; info->name; info++) {
  1106. if (info->id_len) {
  1107. if (!memcmp(info->id, id, info->id_len))
  1108. return info;
  1109. }
  1110. }
  1111. dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
  1112. id[0], id[1], id[2]);
  1113. return ERR_PTR(-ENODEV);
  1114. }
  1115. static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
  1116. size_t *retlen, u_char *buf)
  1117. {
  1118. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1119. int ret;
  1120. dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
  1121. while (len) {
  1122. loff_t addr = from;
  1123. size_t read_len = len;
  1124. #ifdef CONFIG_SPI_FLASH_BAR
  1125. u32 remain_len;
  1126. ret = write_bar(nor, addr);
  1127. if (ret < 0)
  1128. return log_ret(ret);
  1129. remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
  1130. if (len < remain_len)
  1131. read_len = len;
  1132. else
  1133. read_len = remain_len;
  1134. #endif
  1135. ret = nor->read(nor, addr, read_len, buf);
  1136. if (ret == 0) {
  1137. /* We shouldn't see 0-length reads */
  1138. ret = -EIO;
  1139. goto read_err;
  1140. }
  1141. if (ret < 0)
  1142. goto read_err;
  1143. *retlen += ret;
  1144. buf += ret;
  1145. from += ret;
  1146. len -= ret;
  1147. }
  1148. ret = 0;
  1149. read_err:
  1150. #ifdef CONFIG_SPI_FLASH_BAR
  1151. ret = clean_bar(nor);
  1152. #endif
  1153. return ret;
  1154. }
  1155. #ifdef CONFIG_SPI_FLASH_SST
  1156. /*
  1157. * sst26 flash series has its own block protection implementation:
  1158. * 4x - 8 KByte blocks - read & write protection bits - upper addresses
  1159. * 1x - 32 KByte blocks - write protection bits
  1160. * rest - 64 KByte blocks - write protection bits
  1161. * 1x - 32 KByte blocks - write protection bits
  1162. * 4x - 8 KByte blocks - read & write protection bits - lower addresses
  1163. *
  1164. * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
  1165. * will be treated as single block.
  1166. */
  1167. #define SST26_BPR_8K_NUM 4
  1168. #define SST26_MAX_BPR_REG_LEN (18 + 1)
  1169. #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
  1170. enum lock_ctl {
  1171. SST26_CTL_LOCK,
  1172. SST26_CTL_UNLOCK,
  1173. SST26_CTL_CHECK
  1174. };
  1175. static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl)
  1176. {
  1177. switch (ctl) {
  1178. case SST26_CTL_LOCK:
  1179. cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
  1180. break;
  1181. case SST26_CTL_UNLOCK:
  1182. cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
  1183. break;
  1184. case SST26_CTL_CHECK:
  1185. return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
  1186. }
  1187. return false;
  1188. }
  1189. /*
  1190. * Lock, unlock or check lock status of the flash region of the flash (depending
  1191. * on the lock_ctl value)
  1192. */
  1193. static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum lock_ctl ctl)
  1194. {
  1195. struct mtd_info *mtd = &nor->mtd;
  1196. u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
  1197. bool lower_64k = false, upper_64k = false;
  1198. u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
  1199. int ret;
  1200. /* Check length and offset for 64k alignment */
  1201. if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
  1202. dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
  1203. return -EINVAL;
  1204. }
  1205. if (ofs + len > mtd->size) {
  1206. dev_err(nor->dev, "range is more than device size: %#llx + %#llx > %#llx\n",
  1207. ofs, len, mtd->size);
  1208. return -EINVAL;
  1209. }
  1210. /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
  1211. if (mtd->size != SZ_2M &&
  1212. mtd->size != SZ_4M &&
  1213. mtd->size != SZ_8M)
  1214. return -EINVAL;
  1215. bpr_size = 2 + (mtd->size / SZ_64K / 8);
  1216. ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
  1217. if (ret < 0) {
  1218. dev_err(nor->dev, "fail to read block-protection register\n");
  1219. return ret;
  1220. }
  1221. rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
  1222. lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
  1223. upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
  1224. lower_64k = (ofs < SST26_BOUND_REG_SIZE);
  1225. /* Lower bits in block-protection register are about 64k region */
  1226. bpr_ptr = lptr_64k / SZ_64K - 1;
  1227. /* Process 64K blocks region */
  1228. while (lptr_64k < rptr_64k) {
  1229. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1230. return EACCES;
  1231. bpr_ptr++;
  1232. lptr_64k += SZ_64K;
  1233. }
  1234. /* 32K and 8K region bits in BPR are after 64k region bits */
  1235. bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
  1236. /* Process lower 32K block region */
  1237. if (lower_64k)
  1238. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1239. return EACCES;
  1240. bpr_ptr++;
  1241. /* Process upper 32K block region */
  1242. if (upper_64k)
  1243. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1244. return EACCES;
  1245. bpr_ptr++;
  1246. /* Process lower 8K block regions */
  1247. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  1248. if (lower_64k)
  1249. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1250. return EACCES;
  1251. /* In 8K area BPR has both read and write protection bits */
  1252. bpr_ptr += 2;
  1253. }
  1254. /* Process upper 8K block regions */
  1255. for (i = 0; i < SST26_BPR_8K_NUM; i++) {
  1256. if (upper_64k)
  1257. if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
  1258. return EACCES;
  1259. /* In 8K area BPR has both read and write protection bits */
  1260. bpr_ptr += 2;
  1261. }
  1262. /* If we check region status we don't need to write BPR back */
  1263. if (ctl == SST26_CTL_CHECK)
  1264. return 0;
  1265. ret = nor->write_reg(nor, SPINOR_OP_WRITE_BPR, bpr_buff, bpr_size);
  1266. if (ret < 0) {
  1267. dev_err(nor->dev, "fail to write block-protection register\n");
  1268. return ret;
  1269. }
  1270. return 0;
  1271. }
  1272. static int sst26_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1273. {
  1274. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_UNLOCK);
  1275. }
  1276. static int sst26_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1277. {
  1278. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_LOCK);
  1279. }
  1280. /*
  1281. * Returns EACCES (positive value) if region is locked, 0 if region is unlocked,
  1282. * and negative on errors.
  1283. */
  1284. static int sst26_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  1285. {
  1286. /*
  1287. * is_locked function is used for check before reading or erasing flash
  1288. * region, so offset and length might be not 64k allighned, so adjust
  1289. * them to be 64k allighned as sst26_lock_ctl works only with 64k
  1290. * allighned regions.
  1291. */
  1292. ofs -= ofs & (SZ_64K - 1);
  1293. len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len;
  1294. return sst26_lock_ctl(nor, ofs, len, SST26_CTL_CHECK);
  1295. }
  1296. static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
  1297. size_t *retlen, const u_char *buf)
  1298. {
  1299. size_t actual;
  1300. int ret = 0;
  1301. for (actual = 0; actual < len; actual++) {
  1302. nor->program_opcode = SPINOR_OP_BP;
  1303. write_enable(nor);
  1304. /* write one byte. */
  1305. ret = nor->write(nor, to, 1, buf + actual);
  1306. if (ret < 0)
  1307. goto sst_write_err;
  1308. ret = spi_nor_wait_till_ready(nor);
  1309. if (ret)
  1310. goto sst_write_err;
  1311. to++;
  1312. }
  1313. sst_write_err:
  1314. write_disable(nor);
  1315. return ret;
  1316. }
  1317. static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
  1318. size_t *retlen, const u_char *buf)
  1319. {
  1320. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1321. struct spi_slave *spi = nor->spi;
  1322. size_t actual;
  1323. int ret;
  1324. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  1325. if (spi->mode & SPI_TX_BYTE)
  1326. return sst_write_byteprogram(nor, to, len, retlen, buf);
  1327. write_enable(nor);
  1328. nor->sst_write_second = false;
  1329. actual = to % 2;
  1330. /* Start write from odd address. */
  1331. if (actual) {
  1332. nor->program_opcode = SPINOR_OP_BP;
  1333. /* write one byte. */
  1334. ret = nor->write(nor, to, 1, buf);
  1335. if (ret < 0)
  1336. goto sst_write_err;
  1337. ret = spi_nor_wait_till_ready(nor);
  1338. if (ret)
  1339. goto sst_write_err;
  1340. }
  1341. to += actual;
  1342. /* Write out most of the data here. */
  1343. for (; actual < len - 1; actual += 2) {
  1344. nor->program_opcode = SPINOR_OP_AAI_WP;
  1345. /* write two bytes. */
  1346. ret = nor->write(nor, to, 2, buf + actual);
  1347. if (ret < 0)
  1348. goto sst_write_err;
  1349. ret = spi_nor_wait_till_ready(nor);
  1350. if (ret)
  1351. goto sst_write_err;
  1352. to += 2;
  1353. nor->sst_write_second = true;
  1354. }
  1355. nor->sst_write_second = false;
  1356. write_disable(nor);
  1357. ret = spi_nor_wait_till_ready(nor);
  1358. if (ret)
  1359. goto sst_write_err;
  1360. /* Write out trailing byte if it exists. */
  1361. if (actual != len) {
  1362. write_enable(nor);
  1363. nor->program_opcode = SPINOR_OP_BP;
  1364. ret = nor->write(nor, to, 1, buf + actual);
  1365. if (ret < 0)
  1366. goto sst_write_err;
  1367. ret = spi_nor_wait_till_ready(nor);
  1368. if (ret)
  1369. goto sst_write_err;
  1370. write_disable(nor);
  1371. actual += 1;
  1372. }
  1373. sst_write_err:
  1374. *retlen += actual;
  1375. return ret;
  1376. }
  1377. #endif
  1378. /*
  1379. * Write an address range to the nor chip. Data must be written in
  1380. * FLASH_PAGESIZE chunks. The address range may be any size provided
  1381. * it is within the physical boundaries.
  1382. */
  1383. static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
  1384. size_t *retlen, const u_char *buf)
  1385. {
  1386. struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1387. size_t page_offset, page_remain, i;
  1388. ssize_t ret;
  1389. #ifdef CONFIG_SPI_FLASH_SST
  1390. /* sst nor chips use AAI word program */
  1391. if (nor->info->flags & SST_WRITE)
  1392. return sst_write(mtd, to, len, retlen, buf);
  1393. #endif
  1394. dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
  1395. if (!len)
  1396. return 0;
  1397. for (i = 0; i < len; ) {
  1398. ssize_t written;
  1399. loff_t addr = to + i;
  1400. WATCHDOG_RESET();
  1401. /*
  1402. * If page_size is a power of two, the offset can be quickly
  1403. * calculated with an AND operation. On the other cases we
  1404. * need to do a modulus operation (more expensive).
  1405. */
  1406. if (is_power_of_2(nor->page_size)) {
  1407. page_offset = addr & (nor->page_size - 1);
  1408. } else {
  1409. u64 aux = addr;
  1410. page_offset = do_div(aux, nor->page_size);
  1411. }
  1412. /* the size of data remaining on the first page */
  1413. page_remain = min_t(size_t,
  1414. nor->page_size - page_offset, len - i);
  1415. #ifdef CONFIG_SPI_FLASH_BAR
  1416. ret = write_bar(nor, addr);
  1417. if (ret < 0)
  1418. return ret;
  1419. #endif
  1420. write_enable(nor);
  1421. ret = nor->write(nor, addr, page_remain, buf + i);
  1422. if (ret < 0)
  1423. goto write_err;
  1424. written = ret;
  1425. ret = spi_nor_wait_till_ready(nor);
  1426. if (ret)
  1427. goto write_err;
  1428. *retlen += written;
  1429. i += written;
  1430. }
  1431. write_err:
  1432. #ifdef CONFIG_SPI_FLASH_BAR
  1433. ret = clean_bar(nor);
  1434. #endif
  1435. return ret;
  1436. }
  1437. #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
  1438. /**
  1439. * macronix_quad_enable() - set QE bit in Status Register.
  1440. * @nor: pointer to a 'struct spi_nor'
  1441. *
  1442. * Set the Quad Enable (QE) bit in the Status Register.
  1443. *
  1444. * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  1445. *
  1446. * Return: 0 on success, -errno otherwise.
  1447. */
  1448. static int macronix_quad_enable(struct spi_nor *nor)
  1449. {
  1450. int ret, val;
  1451. val = read_sr(nor);
  1452. if (val < 0)
  1453. return val;
  1454. if (val & SR_QUAD_EN_MX)
  1455. return 0;
  1456. write_enable(nor);
  1457. write_sr(nor, val | SR_QUAD_EN_MX);
  1458. ret = spi_nor_wait_till_ready(nor);
  1459. if (ret)
  1460. return ret;
  1461. ret = read_sr(nor);
  1462. if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
  1463. dev_err(nor->dev, "Macronix Quad bit not set\n");
  1464. return -EINVAL;
  1465. }
  1466. return 0;
  1467. }
  1468. #endif
  1469. #ifdef CONFIG_SPI_FLASH_SPANSION
  1470. /**
  1471. * spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register.
  1472. * @nor: pointer to a 'struct spi_nor'
  1473. * @addr_base: base address of register (can be >0 in multi-die parts)
  1474. * @dummy: number of dummy cycles for register read
  1475. *
  1476. * It is recommended to update volatile registers in the field application due
  1477. * to a risk of the non-volatile registers corruption by power interrupt. This
  1478. * function sets Quad Enable bit in CFR1 volatile.
  1479. *
  1480. * Return: 0 on success, -errno otherwise.
  1481. */
  1482. static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base,
  1483. u8 dummy)
  1484. {
  1485. u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V;
  1486. u8 cr;
  1487. int ret;
  1488. /* Check current Quad Enable bit value. */
  1489. ret = spansion_read_any_reg(nor, addr, dummy, &cr);
  1490. if (ret < 0) {
  1491. dev_dbg(nor->dev,
  1492. "error while reading configuration register\n");
  1493. return -EINVAL;
  1494. }
  1495. if (cr & CR_QUAD_EN_SPAN)
  1496. return 0;
  1497. cr |= CR_QUAD_EN_SPAN;
  1498. write_enable(nor);
  1499. ret = spansion_write_any_reg(nor, addr, cr);
  1500. if (ret < 0) {
  1501. dev_dbg(nor->dev,
  1502. "error while writing configuration register\n");
  1503. return -EINVAL;
  1504. }
  1505. /* Read back and check it. */
  1506. ret = spansion_read_any_reg(nor, addr, dummy, &cr);
  1507. if (ret || !(cr & CR_QUAD_EN_SPAN)) {
  1508. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  1509. return -EINVAL;
  1510. }
  1511. return 0;
  1512. }
  1513. #endif
  1514. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1515. /*
  1516. * Write status Register and configuration register with 2 bytes
  1517. * The first byte will be written to the status register, while the
  1518. * second byte will be written to the configuration register.
  1519. * Return negative if error occurred.
  1520. */
  1521. static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
  1522. {
  1523. int ret;
  1524. write_enable(nor);
  1525. ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
  1526. if (ret < 0) {
  1527. dev_dbg(nor->dev,
  1528. "error while writing configuration register\n");
  1529. return -EINVAL;
  1530. }
  1531. ret = spi_nor_wait_till_ready(nor);
  1532. if (ret) {
  1533. dev_dbg(nor->dev,
  1534. "timeout while writing configuration register\n");
  1535. return ret;
  1536. }
  1537. return 0;
  1538. }
  1539. /**
  1540. * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  1541. * @nor: pointer to a 'struct spi_nor'
  1542. *
  1543. * Set the Quad Enable (QE) bit in the Configuration Register.
  1544. * This function should be used with QSPI memories supporting the Read
  1545. * Configuration Register (35h) instruction.
  1546. *
  1547. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1548. * memories.
  1549. *
  1550. * Return: 0 on success, -errno otherwise.
  1551. */
  1552. static int spansion_read_cr_quad_enable(struct spi_nor *nor)
  1553. {
  1554. u8 sr_cr[2];
  1555. int ret;
  1556. /* Check current Quad Enable bit value. */
  1557. ret = read_cr(nor);
  1558. if (ret < 0) {
  1559. dev_dbg(nor->dev,
  1560. "error while reading configuration register\n");
  1561. return -EINVAL;
  1562. }
  1563. if (ret & CR_QUAD_EN_SPAN)
  1564. return 0;
  1565. sr_cr[1] = ret | CR_QUAD_EN_SPAN;
  1566. /* Keep the current value of the Status Register. */
  1567. ret = read_sr(nor);
  1568. if (ret < 0) {
  1569. dev_dbg(nor->dev, "error while reading status register\n");
  1570. return -EINVAL;
  1571. }
  1572. sr_cr[0] = ret;
  1573. ret = write_sr_cr(nor, sr_cr);
  1574. if (ret)
  1575. return ret;
  1576. /* Read back and check it. */
  1577. ret = read_cr(nor);
  1578. if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
  1579. dev_dbg(nor->dev, "Spansion Quad bit not set\n");
  1580. return -EINVAL;
  1581. }
  1582. return 0;
  1583. }
  1584. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1585. /**
  1586. * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
  1587. * @nor: pointer to a 'struct spi_nor'
  1588. *
  1589. * Set the Quad Enable (QE) bit in the Configuration Register.
  1590. * This function should be used with QSPI memories not supporting the Read
  1591. * Configuration Register (35h) instruction.
  1592. *
  1593. * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  1594. * memories.
  1595. *
  1596. * Return: 0 on success, -errno otherwise.
  1597. */
  1598. static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
  1599. {
  1600. u8 sr_cr[2];
  1601. int ret;
  1602. /* Keep the current value of the Status Register. */
  1603. ret = read_sr(nor);
  1604. if (ret < 0) {
  1605. dev_dbg(nor->dev, "error while reading status register\n");
  1606. return -EINVAL;
  1607. }
  1608. sr_cr[0] = ret;
  1609. sr_cr[1] = CR_QUAD_EN_SPAN;
  1610. return write_sr_cr(nor, sr_cr);
  1611. }
  1612. #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
  1613. #endif /* CONFIG_SPI_FLASH_SPANSION */
  1614. static void
  1615. spi_nor_set_read_settings(struct spi_nor_read_command *read,
  1616. u8 num_mode_clocks,
  1617. u8 num_wait_states,
  1618. u8 opcode,
  1619. enum spi_nor_protocol proto)
  1620. {
  1621. read->num_mode_clocks = num_mode_clocks;
  1622. read->num_wait_states = num_wait_states;
  1623. read->opcode = opcode;
  1624. read->proto = proto;
  1625. }
  1626. static void
  1627. spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
  1628. u8 opcode,
  1629. enum spi_nor_protocol proto)
  1630. {
  1631. pp->opcode = opcode;
  1632. pp->proto = proto;
  1633. }
  1634. #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
  1635. /*
  1636. * Serial Flash Discoverable Parameters (SFDP) parsing.
  1637. */
  1638. /**
  1639. * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
  1640. * @nor: pointer to a 'struct spi_nor'
  1641. * @addr: offset in the SFDP area to start reading data from
  1642. * @len: number of bytes to read
  1643. * @buf: buffer where the SFDP data are copied into (dma-safe memory)
  1644. *
  1645. * Whatever the actual numbers of bytes for address and dummy cycles are
  1646. * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
  1647. * followed by a 3-byte address and 8 dummy clock cycles.
  1648. *
  1649. * Return: 0 on success, -errno otherwise.
  1650. */
  1651. static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
  1652. size_t len, void *buf)
  1653. {
  1654. u8 addr_width, read_opcode, read_dummy;
  1655. int ret;
  1656. read_opcode = nor->read_opcode;
  1657. addr_width = nor->addr_width;
  1658. read_dummy = nor->read_dummy;
  1659. nor->read_opcode = SPINOR_OP_RDSFDP;
  1660. nor->addr_width = 3;
  1661. nor->read_dummy = 8;
  1662. while (len) {
  1663. ret = nor->read(nor, addr, len, (u8 *)buf);
  1664. if (!ret || ret > len) {
  1665. ret = -EIO;
  1666. goto read_err;
  1667. }
  1668. if (ret < 0)
  1669. goto read_err;
  1670. buf += ret;
  1671. addr += ret;
  1672. len -= ret;
  1673. }
  1674. ret = 0;
  1675. read_err:
  1676. nor->read_opcode = read_opcode;
  1677. nor->addr_width = addr_width;
  1678. nor->read_dummy = read_dummy;
  1679. return ret;
  1680. }
  1681. /* Fast Read settings. */
  1682. static void
  1683. spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
  1684. u16 half,
  1685. enum spi_nor_protocol proto)
  1686. {
  1687. read->num_mode_clocks = (half >> 5) & 0x07;
  1688. read->num_wait_states = (half >> 0) & 0x1f;
  1689. read->opcode = (half >> 8) & 0xff;
  1690. read->proto = proto;
  1691. }
  1692. struct sfdp_bfpt_read {
  1693. /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
  1694. u32 hwcaps;
  1695. /*
  1696. * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
  1697. * whether the Fast Read x-y-z command is supported.
  1698. */
  1699. u32 supported_dword;
  1700. u32 supported_bit;
  1701. /*
  1702. * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
  1703. * encodes the op code, the number of mode clocks and the number of wait
  1704. * states to be used by Fast Read x-y-z command.
  1705. */
  1706. u32 settings_dword;
  1707. u32 settings_shift;
  1708. /* The SPI protocol for this Fast Read x-y-z command. */
  1709. enum spi_nor_protocol proto;
  1710. };
  1711. static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
  1712. /* Fast Read 1-1-2 */
  1713. {
  1714. SNOR_HWCAPS_READ_1_1_2,
  1715. BFPT_DWORD(1), BIT(16), /* Supported bit */
  1716. BFPT_DWORD(4), 0, /* Settings */
  1717. SNOR_PROTO_1_1_2,
  1718. },
  1719. /* Fast Read 1-2-2 */
  1720. {
  1721. SNOR_HWCAPS_READ_1_2_2,
  1722. BFPT_DWORD(1), BIT(20), /* Supported bit */
  1723. BFPT_DWORD(4), 16, /* Settings */
  1724. SNOR_PROTO_1_2_2,
  1725. },
  1726. /* Fast Read 2-2-2 */
  1727. {
  1728. SNOR_HWCAPS_READ_2_2_2,
  1729. BFPT_DWORD(5), BIT(0), /* Supported bit */
  1730. BFPT_DWORD(6), 16, /* Settings */
  1731. SNOR_PROTO_2_2_2,
  1732. },
  1733. /* Fast Read 1-1-4 */
  1734. {
  1735. SNOR_HWCAPS_READ_1_1_4,
  1736. BFPT_DWORD(1), BIT(22), /* Supported bit */
  1737. BFPT_DWORD(3), 16, /* Settings */
  1738. SNOR_PROTO_1_1_4,
  1739. },
  1740. /* Fast Read 1-4-4 */
  1741. {
  1742. SNOR_HWCAPS_READ_1_4_4,
  1743. BFPT_DWORD(1), BIT(21), /* Supported bit */
  1744. BFPT_DWORD(3), 0, /* Settings */
  1745. SNOR_PROTO_1_4_4,
  1746. },
  1747. /* Fast Read 4-4-4 */
  1748. {
  1749. SNOR_HWCAPS_READ_4_4_4,
  1750. BFPT_DWORD(5), BIT(4), /* Supported bit */
  1751. BFPT_DWORD(7), 16, /* Settings */
  1752. SNOR_PROTO_4_4_4,
  1753. },
  1754. };
  1755. struct sfdp_bfpt_erase {
  1756. /*
  1757. * The half-word at offset <shift> in DWORD <dwoard> encodes the
  1758. * op code and erase sector size to be used by Sector Erase commands.
  1759. */
  1760. u32 dword;
  1761. u32 shift;
  1762. };
  1763. static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
  1764. /* Erase Type 1 in DWORD8 bits[15:0] */
  1765. {BFPT_DWORD(8), 0},
  1766. /* Erase Type 2 in DWORD8 bits[31:16] */
  1767. {BFPT_DWORD(8), 16},
  1768. /* Erase Type 3 in DWORD9 bits[15:0] */
  1769. {BFPT_DWORD(9), 0},
  1770. /* Erase Type 4 in DWORD9 bits[31:16] */
  1771. {BFPT_DWORD(9), 16},
  1772. };
  1773. static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
  1774. static int
  1775. spi_nor_post_bfpt_fixups(struct spi_nor *nor,
  1776. const struct sfdp_parameter_header *bfpt_header,
  1777. const struct sfdp_bfpt *bfpt,
  1778. struct spi_nor_flash_parameter *params)
  1779. {
  1780. if (nor->fixups && nor->fixups->post_bfpt)
  1781. return nor->fixups->post_bfpt(nor, bfpt_header, bfpt, params);
  1782. return 0;
  1783. }
  1784. /**
  1785. * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
  1786. * @nor: pointer to a 'struct spi_nor'
  1787. * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
  1788. * the Basic Flash Parameter Table length and version
  1789. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  1790. * filled
  1791. *
  1792. * The Basic Flash Parameter Table is the main and only mandatory table as
  1793. * defined by the SFDP (JESD216) specification.
  1794. * It provides us with the total size (memory density) of the data array and
  1795. * the number of address bytes for Fast Read, Page Program and Sector Erase
  1796. * commands.
  1797. * For Fast READ commands, it also gives the number of mode clock cycles and
  1798. * wait states (regrouped in the number of dummy clock cycles) for each
  1799. * supported instruction op code.
  1800. * For Page Program, the page size is now available since JESD216 rev A, however
  1801. * the supported instruction op codes are still not provided.
  1802. * For Sector Erase commands, this table stores the supported instruction op
  1803. * codes and the associated sector sizes.
  1804. * Finally, the Quad Enable Requirements (QER) are also available since JESD216
  1805. * rev A. The QER bits encode the manufacturer dependent procedure to be
  1806. * executed to set the Quad Enable (QE) bit in some internal register of the
  1807. * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
  1808. * sending any Quad SPI command to the memory. Actually, setting the QE bit
  1809. * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
  1810. * and IO3 hence enabling 4 (Quad) I/O lines.
  1811. *
  1812. * Return: 0 on success, -errno otherwise.
  1813. */
  1814. static int spi_nor_parse_bfpt(struct spi_nor *nor,
  1815. const struct sfdp_parameter_header *bfpt_header,
  1816. struct spi_nor_flash_parameter *params)
  1817. {
  1818. struct mtd_info *mtd = &nor->mtd;
  1819. struct sfdp_bfpt bfpt;
  1820. size_t len;
  1821. int i, cmd, err;
  1822. u32 addr;
  1823. u16 half;
  1824. /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
  1825. if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
  1826. return -EINVAL;
  1827. /* Read the Basic Flash Parameter Table. */
  1828. len = min_t(size_t, sizeof(bfpt),
  1829. bfpt_header->length * sizeof(u32));
  1830. addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
  1831. memset(&bfpt, 0, sizeof(bfpt));
  1832. err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
  1833. if (err < 0)
  1834. return err;
  1835. /* Fix endianness of the BFPT DWORDs. */
  1836. for (i = 0; i < BFPT_DWORD_MAX; i++)
  1837. bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
  1838. /* Number of address bytes. */
  1839. switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
  1840. case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
  1841. nor->addr_width = 3;
  1842. break;
  1843. case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
  1844. nor->addr_width = 4;
  1845. break;
  1846. default:
  1847. break;
  1848. }
  1849. /* Flash Memory Density (in bits). */
  1850. params->size = bfpt.dwords[BFPT_DWORD(2)];
  1851. if (params->size & BIT(31)) {
  1852. params->size &= ~BIT(31);
  1853. /*
  1854. * Prevent overflows on params->size. Anyway, a NOR of 2^64
  1855. * bits is unlikely to exist so this error probably means
  1856. * the BFPT we are reading is corrupted/wrong.
  1857. */
  1858. if (params->size > 63)
  1859. return -EINVAL;
  1860. params->size = 1ULL << params->size;
  1861. } else {
  1862. params->size++;
  1863. }
  1864. params->size >>= 3; /* Convert to bytes. */
  1865. /* Fast Read settings. */
  1866. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
  1867. const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
  1868. struct spi_nor_read_command *read;
  1869. if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
  1870. params->hwcaps.mask &= ~rd->hwcaps;
  1871. continue;
  1872. }
  1873. params->hwcaps.mask |= rd->hwcaps;
  1874. cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
  1875. read = &params->reads[cmd];
  1876. half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
  1877. spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
  1878. }
  1879. /* Sector Erase settings. */
  1880. for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
  1881. const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
  1882. u32 erasesize;
  1883. u8 opcode;
  1884. half = bfpt.dwords[er->dword] >> er->shift;
  1885. erasesize = half & 0xff;
  1886. /* erasesize == 0 means this Erase Type is not supported. */
  1887. if (!erasesize)
  1888. continue;
  1889. erasesize = 1U << erasesize;
  1890. opcode = (half >> 8) & 0xff;
  1891. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  1892. if (erasesize == SZ_4K) {
  1893. nor->erase_opcode = opcode;
  1894. mtd->erasesize = erasesize;
  1895. break;
  1896. }
  1897. #endif
  1898. if (!mtd->erasesize || mtd->erasesize < erasesize) {
  1899. nor->erase_opcode = opcode;
  1900. mtd->erasesize = erasesize;
  1901. }
  1902. }
  1903. /* Stop here if not JESD216 rev A or later. */
  1904. if (bfpt_header->length == BFPT_DWORD_MAX_JESD216)
  1905. return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
  1906. params);
  1907. /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
  1908. params->page_size = bfpt.dwords[BFPT_DWORD(11)];
  1909. params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
  1910. params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
  1911. params->page_size = 1U << params->page_size;
  1912. /* Quad Enable Requirements. */
  1913. switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
  1914. case BFPT_DWORD15_QER_NONE:
  1915. params->quad_enable = NULL;
  1916. break;
  1917. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1918. case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
  1919. case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
  1920. params->quad_enable = spansion_no_read_cr_quad_enable;
  1921. break;
  1922. #endif
  1923. #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
  1924. case BFPT_DWORD15_QER_SR1_BIT6:
  1925. params->quad_enable = macronix_quad_enable;
  1926. break;
  1927. #endif
  1928. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  1929. case BFPT_DWORD15_QER_SR2_BIT1:
  1930. params->quad_enable = spansion_read_cr_quad_enable;
  1931. break;
  1932. #endif
  1933. default:
  1934. dev_dbg(nor->dev, "BFPT QER reserved value used\n");
  1935. break;
  1936. }
  1937. /* Soft Reset support. */
  1938. if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST)
  1939. nor->flags |= SNOR_F_SOFT_RESET;
  1940. /* Stop here if JESD216 rev B. */
  1941. if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B)
  1942. return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
  1943. params);
  1944. /* 8D-8D-8D command extension. */
  1945. switch (bfpt.dwords[BFPT_DWORD(18)] & BFPT_DWORD18_CMD_EXT_MASK) {
  1946. case BFPT_DWORD18_CMD_EXT_REP:
  1947. nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
  1948. break;
  1949. case BFPT_DWORD18_CMD_EXT_INV:
  1950. nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
  1951. break;
  1952. case BFPT_DWORD18_CMD_EXT_RES:
  1953. return -EINVAL;
  1954. case BFPT_DWORD18_CMD_EXT_16B:
  1955. dev_err(nor->dev, "16-bit opcodes not supported\n");
  1956. return -ENOTSUPP;
  1957. }
  1958. return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
  1959. }
  1960. /**
  1961. * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
  1962. * SFDP table.
  1963. * @nor: pointer to a 'struct spi_nor'.
  1964. * @param_header: pointer to the SFDP parameter header.
  1965. *
  1966. * Return: 0 on success, -errno otherwise.
  1967. */
  1968. static int
  1969. spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
  1970. const struct sfdp_parameter_header *param_header)
  1971. {
  1972. size_t size;
  1973. u32 addr;
  1974. int ret;
  1975. size = param_header->length * sizeof(u32);
  1976. addr = SFDP_PARAM_HEADER_PTP(param_header);
  1977. nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
  1978. if (!nor->manufacturer_sfdp)
  1979. return -ENOMEM;
  1980. ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
  1981. return ret;
  1982. }
  1983. /**
  1984. * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
  1985. * @nor: pointer to a 'struct spi_nor'
  1986. * @profile1_header: pointer to the 'struct sfdp_parameter_header' describing
  1987. * the 4-Byte Address Instruction Table length and version.
  1988. * @params: pointer to the 'struct spi_nor_flash_parameter' to be.
  1989. *
  1990. * Return: 0 on success, -errno otherwise.
  1991. */
  1992. static int spi_nor_parse_profile1(struct spi_nor *nor,
  1993. const struct sfdp_parameter_header *profile1_header,
  1994. struct spi_nor_flash_parameter *params)
  1995. {
  1996. u32 *table, opcode, addr;
  1997. size_t len;
  1998. int ret, i;
  1999. u8 dummy;
  2000. len = profile1_header->length * sizeof(*table);
  2001. table = kmalloc(len, GFP_KERNEL);
  2002. if (!table)
  2003. return -ENOMEM;
  2004. addr = SFDP_PARAM_HEADER_PTP(profile1_header);
  2005. ret = spi_nor_read_sfdp(nor, addr, len, table);
  2006. if (ret)
  2007. goto out;
  2008. /* Fix endianness of the table DWORDs. */
  2009. for (i = 0; i < profile1_header->length; i++)
  2010. table[i] = le32_to_cpu(table[i]);
  2011. /* Get 8D-8D-8D fast read opcode and dummy cycles. */
  2012. opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]);
  2013. /*
  2014. * We don't know what speed the controller is running at. Find the
  2015. * dummy cycles for the fastest frequency the flash can run at to be
  2016. * sure we are never short of dummy cycles. A value of 0 means the
  2017. * frequency is not supported.
  2018. *
  2019. * Default to PROFILE1_DUMMY_DEFAULT if we don't find anything, and let
  2020. * flashes set the correct value if needed in their fixup hooks.
  2021. */
  2022. dummy = FIELD_GET(PROFILE1_DWORD4_DUMMY_200MHZ, table[3]);
  2023. if (!dummy)
  2024. dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_166MHZ, table[4]);
  2025. if (!dummy)
  2026. dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_133MHZ, table[4]);
  2027. if (!dummy)
  2028. dummy = FIELD_GET(PROFILE1_DWORD5_DUMMY_100MHZ, table[4]);
  2029. if (!dummy)
  2030. dummy = PROFILE1_DUMMY_DEFAULT;
  2031. /* Round up to an even value to avoid tripping controllers up. */
  2032. dummy = ROUND_UP_TO(dummy, 2);
  2033. /* Update the fast read settings. */
  2034. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
  2035. 0, dummy, opcode,
  2036. SNOR_PROTO_8_8_8_DTR);
  2037. /*
  2038. * Set the Read Status Register dummy cycles and dummy address bytes.
  2039. */
  2040. if (table[0] & PROFILE1_DWORD1_RDSR_DUMMY)
  2041. params->rdsr_dummy = 8;
  2042. else
  2043. params->rdsr_dummy = 4;
  2044. if (table[0] & PROFILE1_DWORD1_RDSR_ADDR_BYTES)
  2045. params->rdsr_addr_nbytes = 4;
  2046. else
  2047. params->rdsr_addr_nbytes = 0;
  2048. out:
  2049. kfree(table);
  2050. return ret;
  2051. }
  2052. /**
  2053. * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  2054. * @nor: pointer to a 'struct spi_nor'
  2055. * @params: pointer to the 'struct spi_nor_flash_parameter' to be
  2056. * filled
  2057. *
  2058. * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
  2059. * specification. This is a standard which tends to supported by almost all
  2060. * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
  2061. * runtime the main parameters needed to perform basic SPI flash operations such
  2062. * as Fast Read, Page Program or Sector Erase commands.
  2063. *
  2064. * Return: 0 on success, -errno otherwise.
  2065. */
  2066. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  2067. struct spi_nor_flash_parameter *params)
  2068. {
  2069. const struct sfdp_parameter_header *param_header, *bfpt_header;
  2070. struct sfdp_parameter_header *param_headers = NULL;
  2071. struct sfdp_header header;
  2072. size_t psize;
  2073. int i, err;
  2074. /* Get the SFDP header. */
  2075. err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
  2076. if (err < 0)
  2077. return err;
  2078. /* Check the SFDP header version. */
  2079. if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
  2080. header.major != SFDP_JESD216_MAJOR)
  2081. return -EINVAL;
  2082. /*
  2083. * Verify that the first and only mandatory parameter header is a
  2084. * Basic Flash Parameter Table header as specified in JESD216.
  2085. */
  2086. bfpt_header = &header.bfpt_header;
  2087. if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
  2088. bfpt_header->major != SFDP_JESD216_MAJOR)
  2089. return -EINVAL;
  2090. /*
  2091. * Allocate memory then read all parameter headers with a single
  2092. * Read SFDP command. These parameter headers will actually be parsed
  2093. * twice: a first time to get the latest revision of the basic flash
  2094. * parameter table, then a second time to handle the supported optional
  2095. * tables.
  2096. * Hence we read the parameter headers once for all to reduce the
  2097. * processing time. Also we use kmalloc() instead of devm_kmalloc()
  2098. * because we don't need to keep these parameter headers: the allocated
  2099. * memory is always released with kfree() before exiting this function.
  2100. */
  2101. if (header.nph) {
  2102. psize = header.nph * sizeof(*param_headers);
  2103. param_headers = kmalloc(psize, GFP_KERNEL);
  2104. if (!param_headers)
  2105. return -ENOMEM;
  2106. err = spi_nor_read_sfdp(nor, sizeof(header),
  2107. psize, param_headers);
  2108. if (err < 0) {
  2109. dev_err(nor->dev,
  2110. "failed to read SFDP parameter headers\n");
  2111. goto exit;
  2112. }
  2113. }
  2114. /*
  2115. * Check other parameter headers to get the latest revision of
  2116. * the basic flash parameter table.
  2117. */
  2118. for (i = 0; i < header.nph; i++) {
  2119. param_header = &param_headers[i];
  2120. if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
  2121. param_header->major == SFDP_JESD216_MAJOR &&
  2122. (param_header->minor > bfpt_header->minor ||
  2123. (param_header->minor == bfpt_header->minor &&
  2124. param_header->length > bfpt_header->length)))
  2125. bfpt_header = param_header;
  2126. }
  2127. err = spi_nor_parse_bfpt(nor, bfpt_header, params);
  2128. if (err)
  2129. goto exit;
  2130. /* Parse other parameter headers. */
  2131. for (i = 0; i < header.nph; i++) {
  2132. param_header = &param_headers[i];
  2133. switch (SFDP_PARAM_HEADER_ID(param_header)) {
  2134. case SFDP_SECTOR_MAP_ID:
  2135. dev_info(nor->dev,
  2136. "non-uniform erase sector maps are not supported yet.\n");
  2137. break;
  2138. case SFDP_SST_ID:
  2139. err = spi_nor_parse_microchip_sfdp(nor, param_header);
  2140. break;
  2141. case SFDP_PROFILE1_ID:
  2142. err = spi_nor_parse_profile1(nor, param_header, params);
  2143. break;
  2144. default:
  2145. break;
  2146. }
  2147. if (err) {
  2148. dev_warn(nor->dev,
  2149. "Failed to parse optional parameter table: %04x\n",
  2150. SFDP_PARAM_HEADER_ID(param_header));
  2151. /*
  2152. * Let's not drop all information we extracted so far
  2153. * if optional table parsers fail. In case of failing,
  2154. * each optional parser is responsible to roll back to
  2155. * the previously known spi_nor data.
  2156. */
  2157. err = 0;
  2158. }
  2159. }
  2160. exit:
  2161. kfree(param_headers);
  2162. return err;
  2163. }
  2164. #else
  2165. static int spi_nor_parse_sfdp(struct spi_nor *nor,
  2166. struct spi_nor_flash_parameter *params)
  2167. {
  2168. return -EINVAL;
  2169. }
  2170. #endif /* SPI_FLASH_SFDP_SUPPORT */
  2171. /**
  2172. * spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
  2173. * after SFDP has been parsed (is also called for SPI NORs that do not
  2174. * support RDSFDP).
  2175. * @nor: pointer to a 'struct spi_nor'
  2176. *
  2177. * Typically used to tweak various parameters that could not be extracted by
  2178. * other means (i.e. when information provided by the SFDP/flash_info tables
  2179. * are incomplete or wrong).
  2180. */
  2181. static void spi_nor_post_sfdp_fixups(struct spi_nor *nor,
  2182. struct spi_nor_flash_parameter *params)
  2183. {
  2184. if (nor->fixups && nor->fixups->post_sfdp)
  2185. nor->fixups->post_sfdp(nor, params);
  2186. }
  2187. static void spi_nor_default_init_fixups(struct spi_nor *nor)
  2188. {
  2189. if (nor->fixups && nor->fixups->default_init)
  2190. nor->fixups->default_init(nor);
  2191. }
  2192. static int spi_nor_init_params(struct spi_nor *nor,
  2193. const struct flash_info *info,
  2194. struct spi_nor_flash_parameter *params)
  2195. {
  2196. /* Set legacy flash parameters as default. */
  2197. memset(params, 0, sizeof(*params));
  2198. /* Set SPI NOR sizes. */
  2199. params->size = info->sector_size * info->n_sectors;
  2200. params->page_size = info->page_size;
  2201. if (!(info->flags & SPI_NOR_NO_FR)) {
  2202. /* Default to Fast Read for DT and non-DT platform devices. */
  2203. params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
  2204. /* Mask out Fast Read if not requested at DT instantiation. */
  2205. #if CONFIG_IS_ENABLED(DM_SPI)
  2206. if (!ofnode_read_bool(dev_ofnode(nor->spi->dev),
  2207. "m25p,fast-read"))
  2208. params->hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  2209. #endif
  2210. }
  2211. /* (Fast) Read settings. */
  2212. params->hwcaps.mask |= SNOR_HWCAPS_READ;
  2213. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
  2214. 0, 0, SPINOR_OP_READ,
  2215. SNOR_PROTO_1_1_1);
  2216. if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)
  2217. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
  2218. 0, 8, SPINOR_OP_READ_FAST,
  2219. SNOR_PROTO_1_1_1);
  2220. if (info->flags & SPI_NOR_DUAL_READ) {
  2221. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
  2222. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
  2223. 0, 8, SPINOR_OP_READ_1_1_2,
  2224. SNOR_PROTO_1_1_2);
  2225. }
  2226. if (info->flags & SPI_NOR_QUAD_READ) {
  2227. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
  2228. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
  2229. 0, 8, SPINOR_OP_READ_1_1_4,
  2230. SNOR_PROTO_1_1_4);
  2231. }
  2232. if (info->flags & SPI_NOR_OCTAL_READ) {
  2233. params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
  2234. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_8],
  2235. 0, 8, SPINOR_OP_READ_1_1_8,
  2236. SNOR_PROTO_1_1_8);
  2237. }
  2238. if (info->flags & SPI_NOR_OCTAL_DTR_READ) {
  2239. params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
  2240. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
  2241. 0, 20, SPINOR_OP_READ_FAST,
  2242. SNOR_PROTO_8_8_8_DTR);
  2243. }
  2244. /* Page Program settings. */
  2245. params->hwcaps.mask |= SNOR_HWCAPS_PP;
  2246. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
  2247. SPINOR_OP_PP, SNOR_PROTO_1_1_1);
  2248. /*
  2249. * Since xSPI Page Program opcode is backward compatible with
  2250. * Legacy SPI, use Legacy SPI opcode there as well.
  2251. */
  2252. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
  2253. SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
  2254. if (info->flags & SPI_NOR_QUAD_READ) {
  2255. params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
  2256. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
  2257. SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
  2258. }
  2259. /* Select the procedure to set the Quad Enable bit. */
  2260. if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
  2261. SNOR_HWCAPS_PP_QUAD)) {
  2262. switch (JEDEC_MFR(info)) {
  2263. #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
  2264. case SNOR_MFR_MACRONIX:
  2265. case SNOR_MFR_ISSI:
  2266. params->quad_enable = macronix_quad_enable;
  2267. break;
  2268. #endif
  2269. case SNOR_MFR_ST:
  2270. case SNOR_MFR_MICRON:
  2271. break;
  2272. default:
  2273. #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
  2274. /* Kept only for backward compatibility purpose. */
  2275. params->quad_enable = spansion_read_cr_quad_enable;
  2276. #endif
  2277. break;
  2278. }
  2279. }
  2280. spi_nor_default_init_fixups(nor);
  2281. /* Override the parameters with data read from SFDP tables. */
  2282. nor->addr_width = 0;
  2283. nor->mtd.erasesize = 0;
  2284. if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  2285. SPI_NOR_OCTAL_DTR_READ)) &&
  2286. !(info->flags & SPI_NOR_SKIP_SFDP)) {
  2287. struct spi_nor_flash_parameter sfdp_params;
  2288. memcpy(&sfdp_params, params, sizeof(sfdp_params));
  2289. if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
  2290. nor->addr_width = 0;
  2291. nor->mtd.erasesize = 0;
  2292. } else {
  2293. memcpy(params, &sfdp_params, sizeof(*params));
  2294. }
  2295. }
  2296. spi_nor_post_sfdp_fixups(nor, params);
  2297. return 0;
  2298. }
  2299. static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
  2300. {
  2301. size_t i;
  2302. for (i = 0; i < size; i++)
  2303. if (table[i][0] == (int)hwcaps)
  2304. return table[i][1];
  2305. return -EINVAL;
  2306. }
  2307. static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
  2308. {
  2309. static const int hwcaps_read2cmd[][2] = {
  2310. { SNOR_HWCAPS_READ, SNOR_CMD_READ },
  2311. { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },
  2312. { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },
  2313. { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },
  2314. { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },
  2315. { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },
  2316. { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },
  2317. { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },
  2318. { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },
  2319. { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },
  2320. { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },
  2321. { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },
  2322. { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },
  2323. { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },
  2324. { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },
  2325. { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },
  2326. };
  2327. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
  2328. ARRAY_SIZE(hwcaps_read2cmd));
  2329. }
  2330. static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
  2331. {
  2332. static const int hwcaps_pp2cmd[][2] = {
  2333. { SNOR_HWCAPS_PP, SNOR_CMD_PP },
  2334. { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },
  2335. { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },
  2336. { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },
  2337. { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },
  2338. { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },
  2339. { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },
  2340. { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },
  2341. };
  2342. return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
  2343. ARRAY_SIZE(hwcaps_pp2cmd));
  2344. }
  2345. #ifdef CONFIG_SPI_FLASH_SMART_HWCAPS
  2346. /**
  2347. * spi_nor_check_op - check if the operation is supported by controller
  2348. * @nor: pointer to a 'struct spi_nor'
  2349. * @op: pointer to op template to be checked
  2350. *
  2351. * Returns 0 if operation is supported, -ENOTSUPP otherwise.
  2352. */
  2353. static int spi_nor_check_op(struct spi_nor *nor,
  2354. struct spi_mem_op *op)
  2355. {
  2356. /*
  2357. * First test with 4 address bytes. The opcode itself might be a 3B
  2358. * addressing opcode but we don't care, because SPI controller
  2359. * implementation should not check the opcode, but just the sequence.
  2360. */
  2361. op->addr.nbytes = 4;
  2362. if (!spi_mem_supports_op(nor->spi, op)) {
  2363. if (nor->mtd.size > SZ_16M)
  2364. return -ENOTSUPP;
  2365. /* If flash size <= 16MB, 3 address bytes are sufficient */
  2366. op->addr.nbytes = 3;
  2367. if (!spi_mem_supports_op(nor->spi, op))
  2368. return -ENOTSUPP;
  2369. }
  2370. return 0;
  2371. }
  2372. /**
  2373. * spi_nor_check_readop - check if the read op is supported by controller
  2374. * @nor: pointer to a 'struct spi_nor'
  2375. * @read: pointer to op template to be checked
  2376. *
  2377. * Returns 0 if operation is supported, -ENOTSUPP otherwise.
  2378. */
  2379. static int spi_nor_check_readop(struct spi_nor *nor,
  2380. const struct spi_nor_read_command *read)
  2381. {
  2382. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(read->opcode, 0),
  2383. SPI_MEM_OP_ADDR(3, 0, 0),
  2384. SPI_MEM_OP_DUMMY(1, 0),
  2385. SPI_MEM_OP_DATA_IN(2, NULL, 0));
  2386. spi_nor_setup_op(nor, &op, read->proto);
  2387. op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *
  2388. op.dummy.buswidth / 8;
  2389. if (spi_nor_protocol_is_dtr(nor->read_proto))
  2390. op.dummy.nbytes *= 2;
  2391. return spi_nor_check_op(nor, &op);
  2392. }
  2393. /**
  2394. * spi_nor_check_pp - check if the page program op is supported by controller
  2395. * @nor: pointer to a 'struct spi_nor'
  2396. * @pp: pointer to op template to be checked
  2397. *
  2398. * Returns 0 if operation is supported, -ENOTSUPP otherwise.
  2399. */
  2400. static int spi_nor_check_pp(struct spi_nor *nor,
  2401. const struct spi_nor_pp_command *pp)
  2402. {
  2403. struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(pp->opcode, 0),
  2404. SPI_MEM_OP_ADDR(3, 0, 0),
  2405. SPI_MEM_OP_NO_DUMMY,
  2406. SPI_MEM_OP_DATA_OUT(2, NULL, 0));
  2407. spi_nor_setup_op(nor, &op, pp->proto);
  2408. return spi_nor_check_op(nor, &op);
  2409. }
  2410. /**
  2411. * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
  2412. * controller capabilities
  2413. * @nor: pointer to a 'struct spi_nor'
  2414. * @params: pointer to the 'struct spi_nor_flash_parameter'
  2415. * representing SPI NOR flash capabilities
  2416. * @hwcaps: pointer to resulting capabilities after adjusting
  2417. * according to controller and flash's capability
  2418. *
  2419. * Discard caps based on what the SPI controller actually supports (using
  2420. * spi_mem_supports_op()).
  2421. */
  2422. static void
  2423. spi_nor_adjust_hwcaps(struct spi_nor *nor,
  2424. const struct spi_nor_flash_parameter *params,
  2425. u32 *hwcaps)
  2426. {
  2427. unsigned int cap;
  2428. /*
  2429. * Start by assuming the controller supports every capability.
  2430. * We will mask them after checking what's really supported
  2431. * using spi_mem_supports_op().
  2432. */
  2433. *hwcaps = SNOR_HWCAPS_ALL & params->hwcaps.mask;
  2434. /* X-X-X modes are not supported yet, mask them all. */
  2435. *hwcaps &= ~SNOR_HWCAPS_X_X_X;
  2436. /*
  2437. * If the reset line is broken, we do not want to enter a stateful
  2438. * mode.
  2439. */
  2440. if (nor->flags & SNOR_F_BROKEN_RESET)
  2441. *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);
  2442. for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {
  2443. int rdidx, ppidx;
  2444. if (!(*hwcaps & BIT(cap)))
  2445. continue;
  2446. rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));
  2447. if (rdidx >= 0 &&
  2448. spi_nor_check_readop(nor, &params->reads[rdidx]))
  2449. *hwcaps &= ~BIT(cap);
  2450. ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));
  2451. if (ppidx < 0)
  2452. continue;
  2453. if (spi_nor_check_pp(nor, &params->page_programs[ppidx]))
  2454. *hwcaps &= ~BIT(cap);
  2455. }
  2456. }
  2457. #else
  2458. /**
  2459. * spi_nor_adjust_hwcaps - Find optimal Read/Write protocol based on SPI
  2460. * controller capabilities
  2461. * @nor: pointer to a 'struct spi_nor'
  2462. * @params: pointer to the 'struct spi_nor_flash_parameter'
  2463. * representing SPI NOR flash capabilities
  2464. * @hwcaps: pointer to resulting capabilities after adjusting
  2465. * according to controller and flash's capability
  2466. *
  2467. * Select caps based on what the SPI controller and SPI flash both support.
  2468. */
  2469. static void
  2470. spi_nor_adjust_hwcaps(struct spi_nor *nor,
  2471. const struct spi_nor_flash_parameter *params,
  2472. u32 *hwcaps)
  2473. {
  2474. struct spi_slave *spi = nor->spi;
  2475. u32 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
  2476. SNOR_HWCAPS_READ_4_4_4 |
  2477. SNOR_HWCAPS_READ_8_8_8 |
  2478. SNOR_HWCAPS_PP_4_4_4 |
  2479. SNOR_HWCAPS_PP_8_8_8);
  2480. u32 spi_hwcaps = (SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST |
  2481. SNOR_HWCAPS_PP);
  2482. /* Get the hardware capabilities the SPI controller supports. */
  2483. if (spi->mode & SPI_RX_OCTAL) {
  2484. spi_hwcaps |= SNOR_HWCAPS_READ_1_1_8;
  2485. if (spi->mode & SPI_TX_OCTAL)
  2486. spi_hwcaps |= (SNOR_HWCAPS_READ_1_8_8 |
  2487. SNOR_HWCAPS_PP_1_1_8 |
  2488. SNOR_HWCAPS_PP_1_8_8);
  2489. } else if (spi->mode & SPI_RX_QUAD) {
  2490. spi_hwcaps |= SNOR_HWCAPS_READ_1_1_4;
  2491. if (spi->mode & SPI_TX_QUAD)
  2492. spi_hwcaps |= (SNOR_HWCAPS_READ_1_4_4 |
  2493. SNOR_HWCAPS_PP_1_1_4 |
  2494. SNOR_HWCAPS_PP_1_4_4);
  2495. } else if (spi->mode & SPI_RX_DUAL) {
  2496. spi_hwcaps |= SNOR_HWCAPS_READ_1_1_2;
  2497. if (spi->mode & SPI_TX_DUAL)
  2498. spi_hwcaps |= SNOR_HWCAPS_READ_1_2_2;
  2499. }
  2500. /*
  2501. * Keep only the hardware capabilities supported by both the SPI
  2502. * controller and the SPI flash memory.
  2503. */
  2504. *hwcaps = spi_hwcaps & params->hwcaps.mask;
  2505. if (*hwcaps & ignored_mask) {
  2506. dev_dbg(nor->dev,
  2507. "SPI n-n-n protocols are not supported yet.\n");
  2508. *hwcaps &= ~ignored_mask;
  2509. }
  2510. }
  2511. #endif /* CONFIG_SPI_FLASH_SMART_HWCAPS */
  2512. static int spi_nor_select_read(struct spi_nor *nor,
  2513. const struct spi_nor_flash_parameter *params,
  2514. u32 shared_hwcaps)
  2515. {
  2516. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
  2517. const struct spi_nor_read_command *read;
  2518. if (best_match < 0)
  2519. return -EINVAL;
  2520. cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
  2521. if (cmd < 0)
  2522. return -EINVAL;
  2523. read = &params->reads[cmd];
  2524. nor->read_opcode = read->opcode;
  2525. nor->read_proto = read->proto;
  2526. /*
  2527. * In the spi-nor framework, we don't need to make the difference
  2528. * between mode clock cycles and wait state clock cycles.
  2529. * Indeed, the value of the mode clock cycles is used by a QSPI
  2530. * flash memory to know whether it should enter or leave its 0-4-4
  2531. * (Continuous Read / XIP) mode.
  2532. * eXecution In Place is out of the scope of the mtd sub-system.
  2533. * Hence we choose to merge both mode and wait state clock cycles
  2534. * into the so called dummy clock cycles.
  2535. */
  2536. nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
  2537. return 0;
  2538. }
  2539. static int spi_nor_select_pp(struct spi_nor *nor,
  2540. const struct spi_nor_flash_parameter *params,
  2541. u32 shared_hwcaps)
  2542. {
  2543. int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
  2544. const struct spi_nor_pp_command *pp;
  2545. if (best_match < 0)
  2546. return -EINVAL;
  2547. cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
  2548. if (cmd < 0)
  2549. return -EINVAL;
  2550. pp = &params->page_programs[cmd];
  2551. nor->program_opcode = pp->opcode;
  2552. nor->write_proto = pp->proto;
  2553. return 0;
  2554. }
  2555. static int spi_nor_select_erase(struct spi_nor *nor,
  2556. const struct flash_info *info)
  2557. {
  2558. struct mtd_info *mtd = &nor->mtd;
  2559. /* Do nothing if already configured from SFDP. */
  2560. if (mtd->erasesize)
  2561. return 0;
  2562. #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
  2563. /* prefer "small sector" erase if possible */
  2564. if (info->flags & SECT_4K) {
  2565. nor->erase_opcode = SPINOR_OP_BE_4K;
  2566. mtd->erasesize = 4096;
  2567. } else if (info->flags & SECT_4K_PMC) {
  2568. nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
  2569. mtd->erasesize = 4096;
  2570. } else
  2571. #endif
  2572. {
  2573. nor->erase_opcode = SPINOR_OP_SE;
  2574. mtd->erasesize = info->sector_size;
  2575. }
  2576. return 0;
  2577. }
  2578. static int spi_nor_default_setup(struct spi_nor *nor,
  2579. const struct flash_info *info,
  2580. const struct spi_nor_flash_parameter *params)
  2581. {
  2582. u32 shared_mask;
  2583. bool enable_quad_io;
  2584. int err;
  2585. spi_nor_adjust_hwcaps(nor, params, &shared_mask);
  2586. /* Select the (Fast) Read command. */
  2587. err = spi_nor_select_read(nor, params, shared_mask);
  2588. if (err) {
  2589. dev_dbg(nor->dev,
  2590. "can't select read settings supported by both the SPI controller and memory.\n");
  2591. return err;
  2592. }
  2593. /* Select the Page Program command. */
  2594. err = spi_nor_select_pp(nor, params, shared_mask);
  2595. if (err) {
  2596. dev_dbg(nor->dev,
  2597. "can't select write settings supported by both the SPI controller and memory.\n");
  2598. return err;
  2599. }
  2600. /* Select the Sector Erase command. */
  2601. err = spi_nor_select_erase(nor, info);
  2602. if (err) {
  2603. dev_dbg(nor->dev,
  2604. "can't select erase settings supported by both the SPI controller and memory.\n");
  2605. return err;
  2606. }
  2607. /* Enable Quad I/O if needed. */
  2608. enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
  2609. spi_nor_get_protocol_width(nor->write_proto) == 4);
  2610. if (enable_quad_io && params->quad_enable)
  2611. nor->quad_enable = params->quad_enable;
  2612. else
  2613. nor->quad_enable = NULL;
  2614. return 0;
  2615. }
  2616. static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
  2617. const struct spi_nor_flash_parameter *params)
  2618. {
  2619. if (!nor->setup)
  2620. return 0;
  2621. return nor->setup(nor, info, params);
  2622. }
  2623. #ifdef CONFIG_SPI_FLASH_SPANSION
  2624. static int s25hx_t_mdp_ready(struct spi_nor *nor)
  2625. {
  2626. u32 addr;
  2627. int ret;
  2628. for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
  2629. ret = spansion_sr_ready(nor, addr, 0);
  2630. if (!ret)
  2631. return ret;
  2632. }
  2633. return 1;
  2634. }
  2635. static int s25hx_t_quad_enable(struct spi_nor *nor)
  2636. {
  2637. u32 addr;
  2638. int ret;
  2639. for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) {
  2640. ret = spansion_quad_enable_volatile(nor, addr, 0);
  2641. if (ret)
  2642. return ret;
  2643. }
  2644. return 0;
  2645. }
  2646. static int s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
  2647. {
  2648. /* Support 32 x 4KB sectors at bottom */
  2649. return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0,
  2650. SZ_128K);
  2651. }
  2652. static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info,
  2653. const struct spi_nor_flash_parameter *params)
  2654. {
  2655. int ret;
  2656. u8 cfr3v;
  2657. #ifdef CONFIG_SPI_FLASH_BAR
  2658. return -ENOTSUPP; /* Bank Address Register is not supported */
  2659. #endif
  2660. /*
  2661. * Read CFR3V to check if uniform sector is selected. If not, assign an
  2662. * erase hook that supports non-uniform erase.
  2663. */
  2664. ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v);
  2665. if (ret)
  2666. return ret;
  2667. if (!(cfr3v & CFR3V_UNHYSA))
  2668. nor->erase = s25hx_t_erase_non_uniform;
  2669. /*
  2670. * For the multi-die package parts, the ready() hook is needed to check
  2671. * all dies' status via read any register.
  2672. */
  2673. if (nor->mtd.size > SZ_128M)
  2674. nor->ready = s25hx_t_mdp_ready;
  2675. return spi_nor_default_setup(nor, info, params);
  2676. }
  2677. static void s25hx_t_default_init(struct spi_nor *nor)
  2678. {
  2679. nor->setup = s25hx_t_setup;
  2680. }
  2681. static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
  2682. const struct sfdp_parameter_header *header,
  2683. const struct sfdp_bfpt *bfpt,
  2684. struct spi_nor_flash_parameter *params)
  2685. {
  2686. int ret;
  2687. u32 addr;
  2688. u8 cfr3v;
  2689. /* erase size in case it is set to 4K from BFPT */
  2690. nor->erase_opcode = SPINOR_OP_SE_4B;
  2691. nor->mtd.erasesize = nor->info->sector_size;
  2692. ret = set_4byte(nor, nor->info, 1);
  2693. if (ret)
  2694. return ret;
  2695. nor->addr_width = 4;
  2696. /*
  2697. * The page_size is set to 512B from BFPT, but it actually depends on
  2698. * the configuration register. Look up the CFR3V and determine the
  2699. * page_size. For multi-die package parts, use 512B only when the all
  2700. * dies are configured to 512B buffer.
  2701. */
  2702. for (addr = 0; addr < params->size; addr += SZ_128M) {
  2703. ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V,
  2704. 0, &cfr3v);
  2705. if (ret)
  2706. return ret;
  2707. if (!(cfr3v & CFR3V_PGMBUF)) {
  2708. params->page_size = 256;
  2709. return 0;
  2710. }
  2711. }
  2712. params->page_size = 512;
  2713. return 0;
  2714. }
  2715. static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor,
  2716. struct spi_nor_flash_parameter *params)
  2717. {
  2718. /* READ_FAST_4B (0Ch) requires mode cycles*/
  2719. params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
  2720. /* PP_1_1_4 is not supported */
  2721. params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
  2722. /* Use volatile register to enable quad */
  2723. params->quad_enable = s25hx_t_quad_enable;
  2724. }
  2725. static struct spi_nor_fixups s25hx_t_fixups = {
  2726. .default_init = s25hx_t_default_init,
  2727. .post_bfpt = s25hx_t_post_bfpt_fixup,
  2728. .post_sfdp = s25hx_t_post_sfdp_fixup,
  2729. };
  2730. #endif
  2731. #ifdef CONFIG_SPI_FLASH_S28HS512T
  2732. /**
  2733. * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
  2734. * @nor: pointer to a 'struct spi_nor'
  2735. *
  2736. * This also sets the memory access latency cycles to 24 to allow the flash to
  2737. * run at up to 200MHz.
  2738. *
  2739. * Return: 0 on success, -errno otherwise.
  2740. */
  2741. static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor)
  2742. {
  2743. struct spi_mem_op op;
  2744. u8 buf;
  2745. u8 addr_width = 3;
  2746. int ret;
  2747. /* Use 24 dummy cycles for memory array reads. */
  2748. ret = write_enable(nor);
  2749. if (ret)
  2750. return ret;
  2751. buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
  2752. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  2753. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR2V, 1),
  2754. SPI_MEM_OP_NO_DUMMY,
  2755. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2756. ret = spi_mem_exec_op(nor->spi, &op);
  2757. if (ret) {
  2758. dev_warn(nor->dev,
  2759. "failed to set default memory latency value: %d\n",
  2760. ret);
  2761. return ret;
  2762. }
  2763. ret = spi_nor_wait_till_ready(nor);
  2764. if (ret)
  2765. return ret;
  2766. nor->read_dummy = 24;
  2767. /* Set the octal and DTR enable bits. */
  2768. ret = write_enable(nor);
  2769. if (ret)
  2770. return ret;
  2771. buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
  2772. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
  2773. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR5V, 1),
  2774. SPI_MEM_OP_NO_DUMMY,
  2775. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2776. ret = spi_mem_exec_op(nor->spi, &op);
  2777. if (ret) {
  2778. dev_warn(nor->dev, "Failed to enable octal DTR mode\n");
  2779. return ret;
  2780. }
  2781. return 0;
  2782. }
  2783. static int s28hs512t_erase_non_uniform(struct spi_nor *nor, loff_t addr)
  2784. {
  2785. /* Factory default configuration: 32 x 4 KiB sectors at bottom. */
  2786. return spansion_erase_non_uniform(nor, addr, SPINOR_OP_S28_SE_4K,
  2787. 0, SZ_128K);
  2788. }
  2789. static int s28hs512t_setup(struct spi_nor *nor, const struct flash_info *info,
  2790. const struct spi_nor_flash_parameter *params)
  2791. {
  2792. struct spi_mem_op op;
  2793. u8 buf;
  2794. u8 addr_width = 3;
  2795. int ret;
  2796. ret = spi_nor_wait_till_ready(nor);
  2797. if (ret)
  2798. return ret;
  2799. /*
  2800. * Check CFR3V to check if non-uniform sector mode is selected. If it
  2801. * is, set the erase hook to the non-uniform erase procedure.
  2802. */
  2803. op = (struct spi_mem_op)
  2804. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
  2805. SPI_MEM_OP_ADDR(addr_width,
  2806. SPINOR_REG_CYPRESS_CFR3V, 1),
  2807. SPI_MEM_OP_NO_DUMMY,
  2808. SPI_MEM_OP_DATA_IN(1, &buf, 1));
  2809. ret = spi_mem_exec_op(nor->spi, &op);
  2810. if (ret)
  2811. return ret;
  2812. if (!(buf & SPINOR_REG_CYPRESS_CFR3V_UNISECT))
  2813. nor->erase = s28hs512t_erase_non_uniform;
  2814. return spi_nor_default_setup(nor, info, params);
  2815. }
  2816. static void s28hs512t_default_init(struct spi_nor *nor)
  2817. {
  2818. nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
  2819. nor->setup = s28hs512t_setup;
  2820. }
  2821. static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor,
  2822. struct spi_nor_flash_parameter *params)
  2823. {
  2824. /*
  2825. * On older versions of the flash the xSPI Profile 1.0 table has the
  2826. * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
  2827. */
  2828. if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
  2829. params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
  2830. SPINOR_OP_CYPRESS_RD_FAST;
  2831. params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
  2832. /* This flash is also missing the 4-byte Page Program opcode bit. */
  2833. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
  2834. SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
  2835. /*
  2836. * Since xSPI Page Program opcode is backward compatible with
  2837. * Legacy SPI, use Legacy SPI opcode there as well.
  2838. */
  2839. spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
  2840. SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
  2841. /*
  2842. * The xSPI Profile 1.0 table advertises the number of additional
  2843. * address bytes needed for Read Status Register command as 0 but the
  2844. * actual value for that is 4.
  2845. */
  2846. params->rdsr_addr_nbytes = 4;
  2847. }
  2848. static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor,
  2849. const struct sfdp_parameter_header *bfpt_header,
  2850. const struct sfdp_bfpt *bfpt,
  2851. struct spi_nor_flash_parameter *params)
  2852. {
  2853. struct spi_mem_op op;
  2854. u8 buf;
  2855. u8 addr_width = 3;
  2856. int ret;
  2857. /*
  2858. * The BFPT table advertises a 512B page size but the page size is
  2859. * actually configurable (with the default being 256B). Read from
  2860. * CFR3V[4] and set the correct size.
  2861. */
  2862. op = (struct spi_mem_op)
  2863. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1),
  2864. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_CYPRESS_CFR3V, 1),
  2865. SPI_MEM_OP_NO_DUMMY,
  2866. SPI_MEM_OP_DATA_IN(1, &buf, 1));
  2867. ret = spi_mem_exec_op(nor->spi, &op);
  2868. if (ret)
  2869. return ret;
  2870. if (buf & SPINOR_REG_CYPRESS_CFR3V_PGSZ)
  2871. params->page_size = 512;
  2872. else
  2873. params->page_size = 256;
  2874. /*
  2875. * The BFPT advertises that it supports 4k erases, and the datasheet
  2876. * says the same. But 4k erases did not work when testing. So, use 256k
  2877. * erases for now.
  2878. */
  2879. nor->erase_opcode = SPINOR_OP_SE_4B;
  2880. nor->mtd.erasesize = 0x40000;
  2881. return 0;
  2882. }
  2883. static struct spi_nor_fixups s28hs512t_fixups = {
  2884. .default_init = s28hs512t_default_init,
  2885. .post_sfdp = s28hs512t_post_sfdp_fixup,
  2886. .post_bfpt = s28hs512t_post_bfpt_fixup,
  2887. };
  2888. #endif /* CONFIG_SPI_FLASH_S28HS512T */
  2889. #ifdef CONFIG_SPI_FLASH_MT35XU
  2890. static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor)
  2891. {
  2892. struct spi_mem_op op;
  2893. u8 buf;
  2894. u8 addr_width = 3;
  2895. int ret;
  2896. /* Set dummy cycles for Fast Read to the default of 20. */
  2897. ret = write_enable(nor);
  2898. if (ret)
  2899. return ret;
  2900. buf = 20;
  2901. op = (struct spi_mem_op)
  2902. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
  2903. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1),
  2904. SPI_MEM_OP_NO_DUMMY,
  2905. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2906. ret = spi_mem_exec_op(nor->spi, &op);
  2907. if (ret)
  2908. return ret;
  2909. ret = spi_nor_wait_till_ready(nor);
  2910. if (ret)
  2911. return ret;
  2912. nor->read_dummy = 20;
  2913. ret = write_enable(nor);
  2914. if (ret)
  2915. return ret;
  2916. buf = SPINOR_MT_OCT_DTR;
  2917. op = (struct spi_mem_op)
  2918. SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
  2919. SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1),
  2920. SPI_MEM_OP_NO_DUMMY,
  2921. SPI_MEM_OP_DATA_OUT(1, &buf, 1));
  2922. ret = spi_mem_exec_op(nor->spi, &op);
  2923. if (ret) {
  2924. dev_err(nor->dev, "Failed to enable octal DTR mode\n");
  2925. return ret;
  2926. }
  2927. return 0;
  2928. }
  2929. static void mt35xu512aba_default_init(struct spi_nor *nor)
  2930. {
  2931. nor->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
  2932. }
  2933. static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor,
  2934. struct spi_nor_flash_parameter *params)
  2935. {
  2936. /* Set the Fast Read settings. */
  2937. params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
  2938. spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR],
  2939. 0, 20, SPINOR_OP_MT_DTR_RD,
  2940. SNOR_PROTO_8_8_8_DTR);
  2941. params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
  2942. nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
  2943. params->rdsr_dummy = 8;
  2944. params->rdsr_addr_nbytes = 0;
  2945. /*
  2946. * The BFPT quad enable field is set to a reserved value so the quad
  2947. * enable function is ignored by spi_nor_parse_bfpt(). Make sure we
  2948. * disable it.
  2949. */
  2950. params->quad_enable = NULL;
  2951. }
  2952. static struct spi_nor_fixups mt35xu512aba_fixups = {
  2953. .default_init = mt35xu512aba_default_init,
  2954. .post_sfdp = mt35xu512aba_post_sfdp_fixup,
  2955. };
  2956. #endif /* CONFIG_SPI_FLASH_MT35XU */
  2957. /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
  2958. * @nor: pointer to a 'struct spi_nor'
  2959. *
  2960. * Return: 0 on success, -errno otherwise.
  2961. */
  2962. static int spi_nor_octal_dtr_enable(struct spi_nor *nor)
  2963. {
  2964. int ret;
  2965. if (!nor->octal_dtr_enable)
  2966. return 0;
  2967. if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
  2968. nor->write_proto == SNOR_PROTO_8_8_8_DTR))
  2969. return 0;
  2970. ret = nor->octal_dtr_enable(nor);
  2971. if (ret)
  2972. return ret;
  2973. nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
  2974. return 0;
  2975. }
  2976. static int spi_nor_init(struct spi_nor *nor)
  2977. {
  2978. int err;
  2979. err = spi_nor_octal_dtr_enable(nor);
  2980. if (err) {
  2981. dev_dbg(nor->dev, "Octal DTR mode not supported\n");
  2982. return err;
  2983. }
  2984. /*
  2985. * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
  2986. * with the software protection bits set
  2987. */
  2988. if (IS_ENABLED(CONFIG_SPI_FLASH_UNLOCK_ALL) &&
  2989. (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
  2990. JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
  2991. JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
  2992. nor->info->flags & SPI_NOR_HAS_LOCK)) {
  2993. write_enable(nor);
  2994. write_sr(nor, 0);
  2995. spi_nor_wait_till_ready(nor);
  2996. }
  2997. if (nor->quad_enable) {
  2998. err = nor->quad_enable(nor);
  2999. if (err) {
  3000. dev_dbg(nor->dev, "quad mode not supported\n");
  3001. return err;
  3002. }
  3003. }
  3004. if (nor->addr_width == 4 &&
  3005. !(nor->info->flags & SPI_NOR_OCTAL_DTR_READ) &&
  3006. (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
  3007. !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
  3008. /*
  3009. * If the RESET# pin isn't hooked up properly, or the system
  3010. * otherwise doesn't perform a reset command in the boot
  3011. * sequence, it's impossible to 100% protect against unexpected
  3012. * reboots (e.g., crashes). Warn the user (or hopefully, system
  3013. * designer) that this is bad.
  3014. */
  3015. if (nor->flags & SNOR_F_BROKEN_RESET)
  3016. debug("enabling reset hack; may not recover from unexpected reboots\n");
  3017. set_4byte(nor, nor->info, 1);
  3018. }
  3019. return 0;
  3020. }
  3021. #ifdef CONFIG_SPI_FLASH_SOFT_RESET
  3022. /**
  3023. * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence
  3024. * @nor: the spi_nor structure
  3025. *
  3026. * This function can be used to switch from Octal DTR mode to legacy mode on a
  3027. * flash that supports it. The soft reset is executed in Octal DTR mode.
  3028. *
  3029. * Return: 0 for success, -errno for failure.
  3030. */
  3031. static int spi_nor_soft_reset(struct spi_nor *nor)
  3032. {
  3033. struct spi_mem_op op;
  3034. int ret;
  3035. enum spi_nor_cmd_ext ext;
  3036. ext = nor->cmd_ext_type;
  3037. nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
  3038. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
  3039. SPI_MEM_OP_NO_DUMMY,
  3040. SPI_MEM_OP_NO_ADDR,
  3041. SPI_MEM_OP_NO_DATA);
  3042. spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
  3043. ret = spi_mem_exec_op(nor->spi, &op);
  3044. if (ret) {
  3045. dev_warn(nor->dev, "Software reset enable failed: %d\n", ret);
  3046. goto out;
  3047. }
  3048. op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0),
  3049. SPI_MEM_OP_NO_DUMMY,
  3050. SPI_MEM_OP_NO_ADDR,
  3051. SPI_MEM_OP_NO_DATA);
  3052. spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
  3053. ret = spi_mem_exec_op(nor->spi, &op);
  3054. if (ret) {
  3055. dev_warn(nor->dev, "Software reset failed: %d\n", ret);
  3056. goto out;
  3057. }
  3058. /*
  3059. * Software Reset is not instant, and the delay varies from flash to
  3060. * flash. Looking at a few flashes, most range somewhere below 100
  3061. * microseconds. So, wait for 200ms just to be sure.
  3062. */
  3063. udelay(SPI_NOR_SRST_SLEEP_LEN);
  3064. out:
  3065. nor->cmd_ext_type = ext;
  3066. return ret;
  3067. }
  3068. #endif /* CONFIG_SPI_FLASH_SOFT_RESET */
  3069. int spi_nor_remove(struct spi_nor *nor)
  3070. {
  3071. #ifdef CONFIG_SPI_FLASH_SOFT_RESET
  3072. if (nor->info->flags & SPI_NOR_OCTAL_DTR_READ &&
  3073. nor->flags & SNOR_F_SOFT_RESET)
  3074. return spi_nor_soft_reset(nor);
  3075. #endif
  3076. return 0;
  3077. }
  3078. void spi_nor_set_fixups(struct spi_nor *nor)
  3079. {
  3080. #ifdef CONFIG_SPI_FLASH_SPANSION
  3081. if (JEDEC_MFR(nor->info) == SNOR_MFR_CYPRESS) {
  3082. switch (nor->info->id[1]) {
  3083. case 0x2a: /* S25HL (QSPI, 3.3V) */
  3084. case 0x2b: /* S25HS (QSPI, 1.8V) */
  3085. nor->fixups = &s25hx_t_fixups;
  3086. break;
  3087. default:
  3088. break;
  3089. }
  3090. }
  3091. #endif
  3092. #ifdef CONFIG_SPI_FLASH_S28HS512T
  3093. if (!strcmp(nor->info->name, "s28hs512t"))
  3094. nor->fixups = &s28hs512t_fixups;
  3095. #endif
  3096. #ifdef CONFIG_SPI_FLASH_MT35XU
  3097. if (!strcmp(nor->info->name, "mt35xu512aba"))
  3098. nor->fixups = &mt35xu512aba_fixups;
  3099. #endif
  3100. }
  3101. int spi_nor_scan(struct spi_nor *nor)
  3102. {
  3103. struct spi_nor_flash_parameter params;
  3104. const struct flash_info *info = NULL;
  3105. struct mtd_info *mtd = &nor->mtd;
  3106. struct spi_slave *spi = nor->spi;
  3107. int ret;
  3108. int cfi_mtd_nb = 0;
  3109. #ifdef CONFIG_SYS_MAX_FLASH_BANKS
  3110. cfi_mtd_nb = CONFIG_SYS_MAX_FLASH_BANKS;
  3111. #endif
  3112. /* Reset SPI protocol for all commands. */
  3113. nor->reg_proto = SNOR_PROTO_1_1_1;
  3114. nor->read_proto = SNOR_PROTO_1_1_1;
  3115. nor->write_proto = SNOR_PROTO_1_1_1;
  3116. nor->read = spi_nor_read_data;
  3117. nor->write = spi_nor_write_data;
  3118. nor->read_reg = spi_nor_read_reg;
  3119. nor->write_reg = spi_nor_write_reg;
  3120. nor->setup = spi_nor_default_setup;
  3121. #ifdef CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT
  3122. /*
  3123. * When the flash is handed to us in a stateful mode like 8D-8D-8D, it
  3124. * is difficult to detect the mode the flash is in. One option is to
  3125. * read SFDP in all modes and see which one gives the correct "SFDP"
  3126. * signature, but not all flashes support SFDP in 8D-8D-8D mode.
  3127. *
  3128. * Further, even if you detect the mode of the flash via SFDP, you
  3129. * still have the problem of actually reading the ID. The Read ID
  3130. * command is not standardized across flash vendors. Flashes can have
  3131. * different dummy cycles needed for reading the ID. Some flashes even
  3132. * expect a 4-byte dummy address with the Read ID command. All this
  3133. * information cannot be obtained from the SFDP table.
  3134. *
  3135. * So, perform a Software Reset sequence before reading the ID and
  3136. * initializing the flash. A Soft Reset will bring back the flash in
  3137. * its default protocol mode assuming no non-volatile configuration was
  3138. * set. This will let us detect the flash even if ROM hands it to us in
  3139. * Octal DTR mode.
  3140. *
  3141. * To accommodate cases where there is more than one flash on a board,
  3142. * and only one of them needs a soft reset, failure to reset is not
  3143. * made fatal, and we still try to read ID if possible.
  3144. */
  3145. spi_nor_soft_reset(nor);
  3146. #endif /* CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT */
  3147. info = spi_nor_read_id(nor);
  3148. if (IS_ERR_OR_NULL(info))
  3149. return -ENOENT;
  3150. nor->info = info;
  3151. spi_nor_set_fixups(nor);
  3152. /* Parse the Serial Flash Discoverable Parameters table. */
  3153. ret = spi_nor_init_params(nor, info, &params);
  3154. if (ret)
  3155. return ret;
  3156. if (!mtd->name) {
  3157. sprintf(nor->mtd_name, "%s%d",
  3158. MTD_DEV_TYPE(MTD_DEV_TYPE_NOR),
  3159. cfi_mtd_nb + dev_seq(nor->dev));
  3160. mtd->name = nor->mtd_name;
  3161. }
  3162. mtd->dev = nor->dev;
  3163. mtd->priv = nor;
  3164. mtd->type = MTD_NORFLASH;
  3165. mtd->writesize = 1;
  3166. mtd->flags = MTD_CAP_NORFLASH;
  3167. mtd->size = params.size;
  3168. mtd->_erase = spi_nor_erase;
  3169. mtd->_read = spi_nor_read;
  3170. mtd->_write = spi_nor_write;
  3171. #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
  3172. /* NOR protection support for STmicro/Micron chips and similar */
  3173. if (JEDEC_MFR(info) == SNOR_MFR_ST ||
  3174. JEDEC_MFR(info) == SNOR_MFR_MICRON ||
  3175. JEDEC_MFR(info) == SNOR_MFR_SST ||
  3176. info->flags & SPI_NOR_HAS_LOCK) {
  3177. nor->flash_lock = stm_lock;
  3178. nor->flash_unlock = stm_unlock;
  3179. nor->flash_is_locked = stm_is_locked;
  3180. }
  3181. #endif
  3182. #ifdef CONFIG_SPI_FLASH_SST
  3183. /*
  3184. * sst26 series block protection implementation differs from other
  3185. * series.
  3186. */
  3187. if (info->flags & SPI_NOR_HAS_SST26LOCK) {
  3188. nor->flash_lock = sst26_lock;
  3189. nor->flash_unlock = sst26_unlock;
  3190. nor->flash_is_locked = sst26_is_locked;
  3191. }
  3192. #endif
  3193. if (info->flags & USE_FSR)
  3194. nor->flags |= SNOR_F_USE_FSR;
  3195. if (info->flags & SPI_NOR_HAS_TB)
  3196. nor->flags |= SNOR_F_HAS_SR_TB;
  3197. if (info->flags & NO_CHIP_ERASE)
  3198. nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
  3199. if (info->flags & USE_CLSR)
  3200. nor->flags |= SNOR_F_USE_CLSR;
  3201. if (info->flags & SPI_NOR_NO_ERASE)
  3202. mtd->flags |= MTD_NO_ERASE;
  3203. nor->page_size = params.page_size;
  3204. mtd->writebufsize = nor->page_size;
  3205. /* Some devices cannot do fast-read, no matter what DT tells us */
  3206. if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
  3207. params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
  3208. /*
  3209. * Configure the SPI memory:
  3210. * - select op codes for (Fast) Read, Page Program and Sector Erase.
  3211. * - set the number of dummy cycles (mode cycles + wait states).
  3212. * - set the SPI protocols for register and memory accesses.
  3213. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
  3214. */
  3215. ret = spi_nor_setup(nor, info, &params);
  3216. if (ret)
  3217. return ret;
  3218. if (spi_nor_protocol_is_dtr(nor->read_proto)) {
  3219. /* Always use 4-byte addresses in DTR mode. */
  3220. nor->addr_width = 4;
  3221. } else if (nor->addr_width) {
  3222. /* already configured from SFDP */
  3223. } else if (info->addr_width) {
  3224. nor->addr_width = info->addr_width;
  3225. } else {
  3226. nor->addr_width = 3;
  3227. }
  3228. if (nor->addr_width == 3 && mtd->size > SZ_16M) {
  3229. #ifndef CONFIG_SPI_FLASH_BAR
  3230. /* enable 4-byte addressing if the device exceeds 16MiB */
  3231. nor->addr_width = 4;
  3232. if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
  3233. info->flags & SPI_NOR_4B_OPCODES)
  3234. spi_nor_set_4byte_opcodes(nor, info);
  3235. #else
  3236. /* Configure the BAR - discover bank cmds and read current bank */
  3237. nor->addr_width = 3;
  3238. ret = read_bar(nor, info);
  3239. if (ret < 0)
  3240. return ret;
  3241. #endif
  3242. }
  3243. if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
  3244. dev_dbg(nor->dev, "address width is too large: %u\n",
  3245. nor->addr_width);
  3246. return -EINVAL;
  3247. }
  3248. /* Send all the required SPI flash commands to initialize device */
  3249. ret = spi_nor_init(nor);
  3250. if (ret)
  3251. return ret;
  3252. nor->rdsr_dummy = params.rdsr_dummy;
  3253. nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes;
  3254. nor->name = info->name;
  3255. nor->size = mtd->size;
  3256. nor->erase_size = mtd->erasesize;
  3257. nor->sector_size = mtd->erasesize;
  3258. #ifndef CONFIG_SPL_BUILD
  3259. printf("SF: Detected %s with page size ", nor->name);
  3260. print_size(nor->page_size, ", erase size ");
  3261. print_size(nor->erase_size, ", total ");
  3262. print_size(nor->size, "");
  3263. puts("\n");
  3264. #endif
  3265. return 0;
  3266. }
  3267. /* U-Boot specific functions, need to extend MTD to support these */
  3268. int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
  3269. {
  3270. int sr = read_sr(nor);
  3271. if (sr < 0)
  3272. return sr;
  3273. return (sr >> 2) & 7;
  3274. }