zynqmp.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <cpu_func.h>
  9. #include <debug_uart.h>
  10. #include <dfu.h>
  11. #include <env.h>
  12. #include <env_internal.h>
  13. #include <init.h>
  14. #include <image.h>
  15. #include <lmb.h>
  16. #include <log.h>
  17. #include <net.h>
  18. #include <sata.h>
  19. #include <ahci.h>
  20. #include <scsi.h>
  21. #include <malloc.h>
  22. #include <memalign.h>
  23. #include <wdt.h>
  24. #include <asm/arch/clk.h>
  25. #include <asm/arch/hardware.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/arch/psu_init_gpl.h>
  28. #include <asm/cache.h>
  29. #include <asm/global_data.h>
  30. #include <asm/io.h>
  31. #include <asm/ptrace.h>
  32. #include <dm/device.h>
  33. #include <dm/uclass.h>
  34. #include <usb.h>
  35. #include <dwc3-uboot.h>
  36. #include <zynqmppl.h>
  37. #include <zynqmp_firmware.h>
  38. #include <g_dnl.h>
  39. #include <linux/bitops.h>
  40. #include <linux/delay.h>
  41. #include <linux/sizes.h>
  42. #include "../common/board.h"
  43. #include "pm_cfg_obj.h"
  44. #define ZYNQMP_VERSION_SIZE 7
  45. #define EFUSE_VCU_DIS_MASK 0x100
  46. #define EFUSE_VCU_DIS_SHIFT 8
  47. #define EFUSE_GPU_DIS_MASK 0x20
  48. #define EFUSE_GPU_DIS_SHIFT 5
  49. #define IDCODE2_PL_INIT_MASK 0x200
  50. #define IDCODE2_PL_INIT_SHIFT 9
  51. DECLARE_GLOBAL_DATA_PTR;
  52. #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
  53. static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  54. enum {
  55. ZYNQMP_VARIANT_EG = BIT(0U),
  56. ZYNQMP_VARIANT_EV = BIT(1U),
  57. ZYNQMP_VARIANT_CG = BIT(2U),
  58. ZYNQMP_VARIANT_DR = BIT(3U),
  59. };
  60. static const struct {
  61. u32 id;
  62. u8 device;
  63. u8 variants;
  64. } zynqmp_devices[] = {
  65. {
  66. .id = 0x04711093,
  67. .device = 2,
  68. .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  69. },
  70. {
  71. .id = 0x04710093,
  72. .device = 3,
  73. .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  74. },
  75. {
  76. .id = 0x04721093,
  77. .device = 4,
  78. .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  79. ZYNQMP_VARIANT_EV,
  80. },
  81. {
  82. .id = 0x04720093,
  83. .device = 5,
  84. .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  85. ZYNQMP_VARIANT_EV,
  86. },
  87. {
  88. .id = 0x04739093,
  89. .device = 6,
  90. .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  91. },
  92. {
  93. .id = 0x04730093,
  94. .device = 7,
  95. .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
  96. ZYNQMP_VARIANT_EV,
  97. },
  98. {
  99. .id = 0x04738093,
  100. .device = 9,
  101. .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
  102. },
  103. {
  104. .id = 0x04740093,
  105. .device = 11,
  106. .variants = ZYNQMP_VARIANT_EG,
  107. },
  108. {
  109. .id = 0x04750093,
  110. .device = 15,
  111. .variants = ZYNQMP_VARIANT_EG,
  112. },
  113. {
  114. .id = 0x04759093,
  115. .device = 17,
  116. .variants = ZYNQMP_VARIANT_EG,
  117. },
  118. {
  119. .id = 0x04758093,
  120. .device = 19,
  121. .variants = ZYNQMP_VARIANT_EG,
  122. },
  123. {
  124. .id = 0x047E1093,
  125. .device = 21,
  126. .variants = ZYNQMP_VARIANT_DR,
  127. },
  128. {
  129. .id = 0x047E3093,
  130. .device = 23,
  131. .variants = ZYNQMP_VARIANT_DR,
  132. },
  133. {
  134. .id = 0x047E5093,
  135. .device = 25,
  136. .variants = ZYNQMP_VARIANT_DR,
  137. },
  138. {
  139. .id = 0x047E4093,
  140. .device = 27,
  141. .variants = ZYNQMP_VARIANT_DR,
  142. },
  143. {
  144. .id = 0x047E0093,
  145. .device = 28,
  146. .variants = ZYNQMP_VARIANT_DR,
  147. },
  148. {
  149. .id = 0x047E2093,
  150. .device = 29,
  151. .variants = ZYNQMP_VARIANT_DR,
  152. },
  153. {
  154. .id = 0x047E6093,
  155. .device = 39,
  156. .variants = ZYNQMP_VARIANT_DR,
  157. },
  158. {
  159. .id = 0x047FD093,
  160. .device = 43,
  161. .variants = ZYNQMP_VARIANT_DR,
  162. },
  163. {
  164. .id = 0x047F8093,
  165. .device = 46,
  166. .variants = ZYNQMP_VARIANT_DR,
  167. },
  168. {
  169. .id = 0x047FF093,
  170. .device = 47,
  171. .variants = ZYNQMP_VARIANT_DR,
  172. },
  173. {
  174. .id = 0x047FB093,
  175. .device = 48,
  176. .variants = ZYNQMP_VARIANT_DR,
  177. },
  178. {
  179. .id = 0x047FE093,
  180. .device = 49,
  181. .variants = ZYNQMP_VARIANT_DR,
  182. },
  183. {
  184. .id = 0x046d0093,
  185. .device = 67,
  186. .variants = ZYNQMP_VARIANT_DR,
  187. },
  188. };
  189. static const struct {
  190. u32 id;
  191. char *name;
  192. } zynqmp_svd_devices[] = {
  193. {
  194. .id = 0x04714093,
  195. .name = "xck24"
  196. },
  197. {
  198. .id = 0x04724093,
  199. .name = "xck26",
  200. },
  201. };
  202. static char *zynqmp_detect_svd_name(u32 idcode)
  203. {
  204. u32 i;
  205. for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
  206. if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF))
  207. return zynqmp_svd_devices[i].name;
  208. }
  209. return "unknown";
  210. }
  211. static char *zynqmp_get_silicon_idcode_name(void)
  212. {
  213. u32 i;
  214. u32 idcode, idcode2;
  215. char name[ZYNQMP_VERSION_SIZE];
  216. u32 ret_payload[PAYLOAD_ARG_CNT];
  217. int ret;
  218. ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
  219. if (ret) {
  220. debug("%s: Getting chipid failed\n", __func__);
  221. return "unknown";
  222. }
  223. /*
  224. * Firmware returns:
  225. * payload[0][31:0] = status of the operation
  226. * payload[1]] = IDCODE
  227. * payload[2][19:0] = Version
  228. * payload[2][28:20] = EXTENDED_IDCODE
  229. * payload[2][29] = PL_INIT
  230. */
  231. idcode = ret_payload[1];
  232. idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
  233. debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
  234. idcode2);
  235. for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
  236. if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
  237. break;
  238. }
  239. if (i >= ARRAY_SIZE(zynqmp_devices))
  240. return zynqmp_detect_svd_name(idcode);
  241. /* Add device prefix to the name */
  242. ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
  243. zynqmp_devices[i].device);
  244. if (ret < 0)
  245. return "unknown";
  246. if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
  247. /* Devices with EV variant might be EG/CG/EV family */
  248. if (idcode2 & IDCODE2_PL_INIT_MASK) {
  249. u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
  250. EFUSE_VCU_DIS_SHIFT) << 1 |
  251. ((idcode2 & EFUSE_GPU_DIS_MASK) >>
  252. EFUSE_GPU_DIS_SHIFT);
  253. /*
  254. * Get family name based on extended idcode values as
  255. * determined on UG1087, EXTENDED_IDCODE register
  256. * description
  257. */
  258. switch (family) {
  259. case 0x00:
  260. strncat(name, "ev", 2);
  261. break;
  262. case 0x10:
  263. strncat(name, "eg", 2);
  264. break;
  265. case 0x11:
  266. strncat(name, "cg", 2);
  267. break;
  268. default:
  269. /* Do not append family name*/
  270. break;
  271. }
  272. } else {
  273. /*
  274. * When PL powered down the VCU Disable efuse cannot be
  275. * read. So, ignore the bit and just findout if it is CG
  276. * or EG/EV variant.
  277. */
  278. strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
  279. "e", 2);
  280. }
  281. } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
  282. /* Devices with CG variant might be EG or CG family */
  283. strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
  284. } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
  285. strncat(name, "eg", 2);
  286. } else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
  287. strncat(name, "dr", 2);
  288. } else {
  289. debug("Variant not identified\n");
  290. }
  291. return strdup(name);
  292. }
  293. #endif
  294. int board_early_init_f(void)
  295. {
  296. #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
  297. int ret;
  298. ret = psu_init();
  299. if (ret)
  300. return ret;
  301. /*
  302. * PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
  303. * supply sense channel to SysMon supply registers inside the IP.
  304. * This register must be programmed to complete SysMon IP
  305. * configuration. The default register configuration after
  306. * power-up is incorrect. Hence, fix this by writing the
  307. * correct value - 0x3210.
  308. */
  309. writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
  310. ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
  311. /* Delay is required for clocks to be propagated */
  312. udelay(1000000);
  313. #endif
  314. #ifdef CONFIG_DEBUG_UART
  315. /* Uart debug for sure */
  316. debug_uart_init();
  317. puts("Debug uart enabled\n"); /* or printch() */
  318. #endif
  319. return 0;
  320. }
  321. static int multi_boot(void)
  322. {
  323. u32 multiboot = 0;
  324. int ret;
  325. ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot);
  326. if (ret)
  327. return -EINVAL;
  328. return multiboot;
  329. }
  330. #define PS_SYSMON_ANALOG_BUS_VAL 0x3210
  331. #define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
  332. int board_init(void)
  333. {
  334. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  335. struct udevice *dev;
  336. uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
  337. if (!dev)
  338. panic("PMU Firmware device not found - Enable it");
  339. #endif
  340. #if defined(CONFIG_SPL_BUILD)
  341. /* Check *at build time* if the filename is an non-empty string */
  342. if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
  343. zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
  344. zynqmp_pm_cfg_obj_size);
  345. printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
  346. #else
  347. if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
  348. xilinx_read_eeprom();
  349. #endif
  350. printf("EL Level:\tEL%d\n", current_el());
  351. /* Bug in ROM sets wrong value in this register */
  352. writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
  353. #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
  354. zynqmppl.name = zynqmp_get_silicon_idcode_name();
  355. printf("Chip ID:\t%s\n", zynqmppl.name);
  356. fpga_init();
  357. fpga_add(fpga_xilinx, &zynqmppl);
  358. #endif
  359. if (current_el() == 3)
  360. printf("Multiboot:\t%d\n", multi_boot());
  361. return 0;
  362. }
  363. int board_early_init_r(void)
  364. {
  365. u32 val;
  366. if (current_el() != 3)
  367. return 0;
  368. val = readl(&crlapb_base->timestamp_ref_ctrl);
  369. val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  370. if (!val) {
  371. val = readl(&crlapb_base->timestamp_ref_ctrl);
  372. val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  373. writel(val, &crlapb_base->timestamp_ref_ctrl);
  374. /* Program freq register in System counter */
  375. writel(zynqmp_get_system_timer_freq(),
  376. &iou_scntr_secure->base_frequency_id_register);
  377. /* And enable system counter */
  378. writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  379. &iou_scntr_secure->counter_control_register);
  380. }
  381. return 0;
  382. }
  383. unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
  384. char *const argv[])
  385. {
  386. int ret = 0;
  387. if (current_el() > 1) {
  388. smp_kick_all_cpus();
  389. dcache_disable();
  390. armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
  391. ES_TO_AARCH64);
  392. } else {
  393. printf("FAIL: current EL is not above EL1\n");
  394. ret = EINVAL;
  395. }
  396. return ret;
  397. }
  398. #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
  399. int dram_init_banksize(void)
  400. {
  401. int ret;
  402. ret = fdtdec_setup_memory_banksize();
  403. if (ret)
  404. return ret;
  405. mem_map_fill();
  406. return 0;
  407. }
  408. int dram_init(void)
  409. {
  410. if (fdtdec_setup_mem_size_base() != 0)
  411. return -EINVAL;
  412. return 0;
  413. }
  414. ulong board_get_usable_ram_top(ulong total_size)
  415. {
  416. phys_size_t size;
  417. phys_addr_t reg;
  418. struct lmb lmb;
  419. if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
  420. panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
  421. /* found enough not-reserved memory to relocated U-Boot */
  422. lmb_init(&lmb);
  423. lmb_add(&lmb, gd->ram_base, gd->ram_size);
  424. boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
  425. size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
  426. reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
  427. if (!reg)
  428. reg = gd->ram_top - size;
  429. return reg + size;
  430. }
  431. #else
  432. int dram_init_banksize(void)
  433. {
  434. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  435. gd->bd->bi_dram[0].size = get_effective_memsize();
  436. mem_map_fill();
  437. return 0;
  438. }
  439. int dram_init(void)
  440. {
  441. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  442. CONFIG_SYS_SDRAM_SIZE);
  443. return 0;
  444. }
  445. #endif
  446. #if !CONFIG_IS_ENABLED(SYSRESET)
  447. void reset_cpu(void)
  448. {
  449. }
  450. #endif
  451. static u8 __maybe_unused zynqmp_get_bootmode(void)
  452. {
  453. u8 bootmode;
  454. u32 reg = 0;
  455. int ret;
  456. ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
  457. if (ret)
  458. return -EINVAL;
  459. debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK);
  460. debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT);
  461. if (reg >> BOOT_MODE_ALT_SHIFT)
  462. reg >>= BOOT_MODE_ALT_SHIFT;
  463. bootmode = reg & BOOT_MODES_MASK;
  464. return bootmode;
  465. }
  466. #if defined(CONFIG_BOARD_LATE_INIT)
  467. static const struct {
  468. u32 bit;
  469. const char *name;
  470. } reset_reasons[] = {
  471. { RESET_REASON_DEBUG_SYS, "DEBUG" },
  472. { RESET_REASON_SOFT, "SOFT" },
  473. { RESET_REASON_SRST, "SRST" },
  474. { RESET_REASON_PSONLY, "PS-ONLY" },
  475. { RESET_REASON_PMU, "PMU" },
  476. { RESET_REASON_INTERNAL, "INTERNAL" },
  477. { RESET_REASON_EXTERNAL, "EXTERNAL" },
  478. {}
  479. };
  480. static int reset_reason(void)
  481. {
  482. u32 reg;
  483. int i, ret;
  484. const char *reason = NULL;
  485. ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
  486. if (ret)
  487. return -EINVAL;
  488. puts("Reset reason:\t");
  489. for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
  490. if (reg & reset_reasons[i].bit) {
  491. reason = reset_reasons[i].name;
  492. printf("%s ", reset_reasons[i].name);
  493. break;
  494. }
  495. }
  496. puts("\n");
  497. env_set("reset_reason", reason);
  498. return 0;
  499. }
  500. static int set_fdtfile(void)
  501. {
  502. char *compatible, *fdtfile;
  503. const char *suffix = ".dtb";
  504. const char *vendor = "xilinx/";
  505. int fdt_compat_len;
  506. if (env_get("fdtfile"))
  507. return 0;
  508. compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
  509. &fdt_compat_len);
  510. if (compatible && fdt_compat_len) {
  511. char *name;
  512. debug("Compatible: %s\n", compatible);
  513. name = strchr(compatible, ',');
  514. if (!name)
  515. return -EINVAL;
  516. name++;
  517. fdtfile = calloc(1, strlen(vendor) + strlen(name) +
  518. strlen(suffix) + 1);
  519. if (!fdtfile)
  520. return -ENOMEM;
  521. sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
  522. env_set("fdtfile", fdtfile);
  523. free(fdtfile);
  524. }
  525. return 0;
  526. }
  527. int board_late_init(void)
  528. {
  529. u8 bootmode;
  530. struct udevice *dev;
  531. int bootseq = -1;
  532. int bootseq_len = 0;
  533. int env_targets_len = 0;
  534. const char *mode;
  535. char *new_targets;
  536. char *env_targets;
  537. int ret;
  538. #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
  539. usb_ether_init();
  540. #endif
  541. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  542. debug("Saved variables - Skipping\n");
  543. return 0;
  544. }
  545. if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
  546. return 0;
  547. ret = set_fdtfile();
  548. if (ret)
  549. return ret;
  550. bootmode = zynqmp_get_bootmode();
  551. puts("Bootmode: ");
  552. switch (bootmode) {
  553. case USB_MODE:
  554. puts("USB_MODE\n");
  555. mode = "usb_dfu0 usb_dfu1";
  556. env_set("modeboot", "usb_dfu_spl");
  557. break;
  558. case JTAG_MODE:
  559. puts("JTAG_MODE\n");
  560. mode = "jtag pxe dhcp";
  561. env_set("modeboot", "jtagboot");
  562. break;
  563. case QSPI_MODE_24BIT:
  564. case QSPI_MODE_32BIT:
  565. mode = "qspi0";
  566. puts("QSPI_MODE\n");
  567. env_set("modeboot", "qspiboot");
  568. break;
  569. case EMMC_MODE:
  570. puts("EMMC_MODE\n");
  571. if (uclass_get_device_by_name(UCLASS_MMC,
  572. "mmc@ff160000", &dev) &&
  573. uclass_get_device_by_name(UCLASS_MMC,
  574. "sdhci@ff160000", &dev)) {
  575. puts("Boot from EMMC but without SD0 enabled!\n");
  576. return -1;
  577. }
  578. debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
  579. mode = "mmc";
  580. bootseq = dev_seq(dev);
  581. env_set("modeboot", "emmcboot");
  582. break;
  583. case SD_MODE:
  584. puts("SD_MODE\n");
  585. if (uclass_get_device_by_name(UCLASS_MMC,
  586. "mmc@ff160000", &dev) &&
  587. uclass_get_device_by_name(UCLASS_MMC,
  588. "sdhci@ff160000", &dev)) {
  589. puts("Boot from SD0 but without SD0 enabled!\n");
  590. return -1;
  591. }
  592. debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
  593. mode = "mmc";
  594. bootseq = dev_seq(dev);
  595. env_set("modeboot", "sdboot");
  596. break;
  597. case SD1_LSHFT_MODE:
  598. puts("LVL_SHFT_");
  599. /* fall through */
  600. case SD_MODE1:
  601. puts("SD_MODE1\n");
  602. if (uclass_get_device_by_name(UCLASS_MMC,
  603. "mmc@ff170000", &dev) &&
  604. uclass_get_device_by_name(UCLASS_MMC,
  605. "sdhci@ff170000", &dev)) {
  606. puts("Boot from SD1 but without SD1 enabled!\n");
  607. return -1;
  608. }
  609. debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
  610. mode = "mmc";
  611. bootseq = dev_seq(dev);
  612. env_set("modeboot", "sdboot");
  613. break;
  614. case NAND_MODE:
  615. puts("NAND_MODE\n");
  616. mode = "nand0";
  617. env_set("modeboot", "nandboot");
  618. break;
  619. default:
  620. mode = "";
  621. printf("Invalid Boot Mode:0x%x\n", bootmode);
  622. break;
  623. }
  624. if (bootseq >= 0) {
  625. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  626. debug("Bootseq len: %x\n", bootseq_len);
  627. env_set_hex("bootseq", bootseq);
  628. }
  629. /*
  630. * One terminating char + one byte for space between mode
  631. * and default boot_targets
  632. */
  633. env_targets = env_get("boot_targets");
  634. if (env_targets)
  635. env_targets_len = strlen(env_targets);
  636. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  637. bootseq_len);
  638. if (!new_targets)
  639. return -ENOMEM;
  640. if (bootseq >= 0)
  641. sprintf(new_targets, "%s%x %s", mode, bootseq,
  642. env_targets ? env_targets : "");
  643. else
  644. sprintf(new_targets, "%s %s", mode,
  645. env_targets ? env_targets : "");
  646. env_set("boot_targets", new_targets);
  647. free(new_targets);
  648. reset_reason();
  649. return board_late_init_xilinx();
  650. }
  651. #endif
  652. int checkboard(void)
  653. {
  654. puts("Board: Xilinx ZynqMP\n");
  655. return 0;
  656. }
  657. int mmc_get_env_dev(void)
  658. {
  659. struct udevice *dev;
  660. int bootseq = 0;
  661. switch (zynqmp_get_bootmode()) {
  662. case EMMC_MODE:
  663. case SD_MODE:
  664. if (uclass_get_device_by_name(UCLASS_MMC,
  665. "mmc@ff160000", &dev) &&
  666. uclass_get_device_by_name(UCLASS_MMC,
  667. "sdhci@ff160000", &dev)) {
  668. return -1;
  669. }
  670. bootseq = dev_seq(dev);
  671. break;
  672. case SD1_LSHFT_MODE:
  673. case SD_MODE1:
  674. if (uclass_get_device_by_name(UCLASS_MMC,
  675. "mmc@ff170000", &dev) &&
  676. uclass_get_device_by_name(UCLASS_MMC,
  677. "sdhci@ff170000", &dev)) {
  678. return -1;
  679. }
  680. bootseq = dev_seq(dev);
  681. break;
  682. default:
  683. break;
  684. }
  685. debug("bootseq %d\n", bootseq);
  686. return bootseq;
  687. }
  688. enum env_location env_get_location(enum env_operation op, int prio)
  689. {
  690. u32 bootmode = zynqmp_get_bootmode();
  691. if (prio)
  692. return ENVL_UNKNOWN;
  693. switch (bootmode) {
  694. case EMMC_MODE:
  695. case SD_MODE:
  696. case SD1_LSHFT_MODE:
  697. case SD_MODE1:
  698. if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
  699. return ENVL_FAT;
  700. if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
  701. return ENVL_EXT4;
  702. return ENVL_NOWHERE;
  703. case NAND_MODE:
  704. if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
  705. return ENVL_NAND;
  706. if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
  707. return ENVL_UBI;
  708. return ENVL_NOWHERE;
  709. case QSPI_MODE_24BIT:
  710. case QSPI_MODE_32BIT:
  711. if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
  712. return ENVL_SPI_FLASH;
  713. return ENVL_NOWHERE;
  714. case JTAG_MODE:
  715. default:
  716. return ENVL_NOWHERE;
  717. }
  718. }
  719. #if defined(CONFIG_SET_DFU_ALT_INFO)
  720. #define DFU_ALT_BUF_LEN SZ_1K
  721. void set_dfu_alt_info(char *interface, char *devstr)
  722. {
  723. u8 multiboot;
  724. int bootseq = 0;
  725. ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
  726. if (env_get("dfu_alt_info"))
  727. return;
  728. memset(buf, 0, sizeof(buf));
  729. multiboot = multi_boot();
  730. debug("Multiboot: %d\n", multiboot);
  731. switch (zynqmp_get_bootmode()) {
  732. case EMMC_MODE:
  733. case SD_MODE:
  734. case SD1_LSHFT_MODE:
  735. case SD_MODE1:
  736. bootseq = mmc_get_env_dev();
  737. if (!multiboot)
  738. snprintf(buf, DFU_ALT_BUF_LEN,
  739. "mmc %d:1=boot.bin fat %d 1;"
  740. "u-boot.itb fat %d 1",
  741. bootseq, bootseq, bootseq);
  742. else
  743. snprintf(buf, DFU_ALT_BUF_LEN,
  744. "mmc %d:1=boot%04d.bin fat %d 1;"
  745. "u-boot.itb fat %d 1",
  746. bootseq, multiboot, bootseq, bootseq);
  747. break;
  748. case QSPI_MODE_24BIT:
  749. case QSPI_MODE_32BIT:
  750. snprintf(buf, DFU_ALT_BUF_LEN,
  751. "sf 0:0=boot.bin raw %x 0x1500000;"
  752. "u-boot.itb raw 0x%x 0x500000",
  753. multiboot * SZ_32K, CONFIG_SYS_SPI_U_BOOT_OFFS);
  754. break;
  755. default:
  756. return;
  757. }
  758. env_set("dfu_alt_info", buf);
  759. puts("DFU alt info setting: done\n");
  760. }
  761. #endif