zynqmp-zc1751-xm016-dc2.dts 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * dts file for Xilinx ZynqMP zc1751-xm016-dc2
  4. *
  5. * (C) Copyright 2015 - 2021, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  14. / {
  15. model = "ZynqMP zc1751-xm016-dc2 RevA";
  16. compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
  17. aliases {
  18. ethernet0 = &gem2;
  19. i2c0 = &i2c0;
  20. rtc0 = &rtc;
  21. serial0 = &uart0;
  22. serial1 = &uart1;
  23. spi0 = &spi0;
  24. spi1 = &spi1;
  25. usb0 = &usb1;
  26. };
  27. chosen {
  28. bootargs = "earlycon";
  29. stdout-path = "serial0:115200n8";
  30. };
  31. memory@0 {
  32. device_type = "memory";
  33. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  34. };
  35. };
  36. &can0 {
  37. status = "okay";
  38. pinctrl-names = "default";
  39. pinctrl-0 = <&pinctrl_can0_default>;
  40. };
  41. &can1 {
  42. status = "okay";
  43. pinctrl-names = "default";
  44. pinctrl-0 = <&pinctrl_can1_default>;
  45. };
  46. &fpd_dma_chan1 {
  47. status = "okay";
  48. };
  49. &fpd_dma_chan2 {
  50. status = "okay";
  51. };
  52. &fpd_dma_chan3 {
  53. status = "okay";
  54. };
  55. &fpd_dma_chan4 {
  56. status = "okay";
  57. };
  58. &fpd_dma_chan5 {
  59. status = "okay";
  60. };
  61. &fpd_dma_chan6 {
  62. status = "okay";
  63. };
  64. &fpd_dma_chan7 {
  65. status = "okay";
  66. };
  67. &fpd_dma_chan8 {
  68. status = "okay";
  69. };
  70. &gem2 {
  71. status = "okay";
  72. phy-handle = <&phy0>;
  73. phy-mode = "rgmii-id";
  74. pinctrl-names = "default";
  75. pinctrl-0 = <&pinctrl_gem2_default>;
  76. phy0: ethernet-phy@5 {
  77. reg = <5>;
  78. ti,rx-internal-delay = <0x8>;
  79. ti,tx-internal-delay = <0xa>;
  80. ti,fifo-depth = <0x1>;
  81. ti,dp83867-rxctrl-strap-quirk;
  82. };
  83. };
  84. &gpio {
  85. status = "okay";
  86. };
  87. &i2c0 {
  88. status = "okay";
  89. clock-frequency = <400000>;
  90. pinctrl-names = "default", "gpio";
  91. pinctrl-0 = <&pinctrl_i2c0_default>;
  92. pinctrl-1 = <&pinctrl_i2c0_gpio>;
  93. scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
  94. sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
  95. tca6416_u26: gpio@20 {
  96. compatible = "ti,tca6416";
  97. reg = <0x20>;
  98. gpio-controller;
  99. #gpio-cells = <2>;
  100. /* IRQ not connected */
  101. };
  102. rtc@68 {
  103. compatible = "dallas,ds1339";
  104. reg = <0x68>;
  105. };
  106. };
  107. &nand0 {
  108. status = "okay";
  109. pinctrl-names = "default";
  110. pinctrl-0 = <&pinctrl_nand0_default>;
  111. arasan,has-mdma;
  112. nand@0 {
  113. reg = <0x0>;
  114. #address-cells = <0x2>;
  115. #size-cells = <0x1>;
  116. nand-ecc-mode = "soft";
  117. nand-ecc-algo = "bch";
  118. nand-rb = <0>;
  119. label = "main-storage-0";
  120. nand-ecc-step-size = <1024>;
  121. nand-ecc-strength = <24>;
  122. partition@0 { /* for testing purpose */
  123. label = "nand-fsbl-uboot";
  124. reg = <0x0 0x0 0x400000>;
  125. };
  126. partition@1 { /* for testing purpose */
  127. label = "nand-linux";
  128. reg = <0x0 0x400000 0x1400000>;
  129. };
  130. partition@2 { /* for testing purpose */
  131. label = "nand-device-tree";
  132. reg = <0x0 0x1800000 0x400000>;
  133. };
  134. partition@3 { /* for testing purpose */
  135. label = "nand-rootfs";
  136. reg = <0x0 0x1c00000 0x1400000>;
  137. };
  138. partition@4 { /* for testing purpose */
  139. label = "nand-bitstream";
  140. reg = <0x0 0x3000000 0x400000>;
  141. };
  142. partition@5 { /* for testing purpose */
  143. label = "nand-misc";
  144. reg = <0x0 0x3400000 0xfcc00000>;
  145. };
  146. };
  147. nand@1 {
  148. reg = <0x1>;
  149. #address-cells = <0x2>;
  150. #size-cells = <0x1>;
  151. nand-ecc-mode = "soft";
  152. nand-ecc-algo = "bch";
  153. nand-rb = <0>;
  154. label = "main-storage-1";
  155. nand-ecc-step-size = <1024>;
  156. nand-ecc-strength = <24>;
  157. partition@0 { /* for testing purpose */
  158. label = "nand1-fsbl-uboot";
  159. reg = <0x0 0x0 0x400000>;
  160. };
  161. partition@1 { /* for testing purpose */
  162. label = "nand1-linux";
  163. reg = <0x0 0x400000 0x1400000>;
  164. };
  165. partition@2 { /* for testing purpose */
  166. label = "nand1-device-tree";
  167. reg = <0x0 0x1800000 0x400000>;
  168. };
  169. partition@3 { /* for testing purpose */
  170. label = "nand1-rootfs";
  171. reg = <0x0 0x1c00000 0x1400000>;
  172. };
  173. partition@4 { /* for testing purpose */
  174. label = "nand1-bitstream";
  175. reg = <0x0 0x3000000 0x400000>;
  176. };
  177. partition@5 { /* for testing purpose */
  178. label = "nand1-misc";
  179. reg = <0x0 0x3400000 0xfcc00000>;
  180. };
  181. };
  182. };
  183. &pinctrl0 {
  184. status = "okay";
  185. pinctrl_can0_default: can0-default {
  186. mux {
  187. function = "can0";
  188. groups = "can0_9_grp";
  189. };
  190. conf {
  191. groups = "can0_9_grp";
  192. slew-rate = <SLEW_RATE_SLOW>;
  193. power-source = <IO_STANDARD_LVCMOS18>;
  194. };
  195. conf-rx {
  196. pins = "MIO38";
  197. bias-high-impedance;
  198. };
  199. conf-tx {
  200. pins = "MIO39";
  201. bias-disable;
  202. };
  203. };
  204. pinctrl_can1_default: can1-default {
  205. mux {
  206. function = "can1";
  207. groups = "can1_8_grp";
  208. };
  209. conf {
  210. groups = "can1_8_grp";
  211. slew-rate = <SLEW_RATE_SLOW>;
  212. power-source = <IO_STANDARD_LVCMOS18>;
  213. };
  214. conf-rx {
  215. pins = "MIO33";
  216. bias-high-impedance;
  217. };
  218. conf-tx {
  219. pins = "MIO32";
  220. bias-disable;
  221. };
  222. };
  223. pinctrl_i2c0_default: i2c0-default {
  224. mux {
  225. groups = "i2c0_1_grp";
  226. function = "i2c0";
  227. };
  228. conf {
  229. groups = "i2c0_1_grp";
  230. bias-pull-up;
  231. slew-rate = <SLEW_RATE_SLOW>;
  232. power-source = <IO_STANDARD_LVCMOS18>;
  233. };
  234. };
  235. pinctrl_i2c0_gpio: i2c0-gpio {
  236. mux {
  237. groups = "gpio0_6_grp", "gpio0_7_grp";
  238. function = "gpio0";
  239. };
  240. conf {
  241. groups = "gpio0_6_grp", "gpio0_7_grp";
  242. slew-rate = <SLEW_RATE_SLOW>;
  243. power-source = <IO_STANDARD_LVCMOS18>;
  244. };
  245. };
  246. pinctrl_uart0_default: uart0-default {
  247. mux {
  248. groups = "uart0_10_grp";
  249. function = "uart0";
  250. };
  251. conf {
  252. groups = "uart0_10_grp";
  253. slew-rate = <SLEW_RATE_SLOW>;
  254. power-source = <IO_STANDARD_LVCMOS18>;
  255. };
  256. conf-rx {
  257. pins = "MIO42";
  258. bias-high-impedance;
  259. };
  260. conf-tx {
  261. pins = "MIO43";
  262. bias-disable;
  263. };
  264. };
  265. pinctrl_uart1_default: uart1-default {
  266. mux {
  267. groups = "uart1_10_grp";
  268. function = "uart1";
  269. };
  270. conf {
  271. groups = "uart1_10_grp";
  272. slew-rate = <SLEW_RATE_SLOW>;
  273. power-source = <IO_STANDARD_LVCMOS18>;
  274. };
  275. conf-rx {
  276. pins = "MIO41";
  277. bias-high-impedance;
  278. };
  279. conf-tx {
  280. pins = "MIO40";
  281. bias-disable;
  282. };
  283. };
  284. pinctrl_usb1_default: usb1-default {
  285. mux {
  286. groups = "usb1_0_grp";
  287. function = "usb1";
  288. };
  289. conf {
  290. groups = "usb1_0_grp";
  291. slew-rate = <SLEW_RATE_SLOW>;
  292. power-source = <IO_STANDARD_LVCMOS18>;
  293. };
  294. conf-rx {
  295. pins = "MIO64", "MIO65", "MIO67";
  296. bias-high-impedance;
  297. };
  298. conf-tx {
  299. pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
  300. "MIO72", "MIO73", "MIO74", "MIO75";
  301. bias-disable;
  302. };
  303. };
  304. pinctrl_gem2_default: gem2-default {
  305. mux {
  306. function = "ethernet2";
  307. groups = "ethernet2_0_grp";
  308. };
  309. conf {
  310. groups = "ethernet2_0_grp";
  311. slew-rate = <SLEW_RATE_SLOW>;
  312. power-source = <IO_STANDARD_LVCMOS18>;
  313. };
  314. conf-rx {
  315. pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
  316. "MIO63";
  317. bias-high-impedance;
  318. low-power-disable;
  319. };
  320. conf-tx {
  321. pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
  322. "MIO57";
  323. bias-disable;
  324. low-power-enable;
  325. };
  326. mux-mdio {
  327. function = "mdio2";
  328. groups = "mdio2_0_grp";
  329. };
  330. conf-mdio {
  331. groups = "mdio2_0_grp";
  332. slew-rate = <SLEW_RATE_SLOW>;
  333. power-source = <IO_STANDARD_LVCMOS18>;
  334. bias-disable;
  335. };
  336. };
  337. pinctrl_nand0_default: nand0-default {
  338. mux {
  339. groups = "nand0_0_grp";
  340. function = "nand0";
  341. };
  342. conf {
  343. groups = "nand0_0_grp";
  344. bias-pull-up;
  345. };
  346. mux-ce {
  347. groups = "nand0_ce_0_grp";
  348. function = "nand0_ce";
  349. };
  350. conf-ce {
  351. groups = "nand0_ce_0_grp";
  352. bias-pull-up;
  353. };
  354. mux-rb {
  355. groups = "nand0_rb_0_grp";
  356. function = "nand0_rb";
  357. };
  358. conf-rb {
  359. groups = "nand0_rb_0_grp";
  360. bias-pull-up;
  361. };
  362. mux-dqs {
  363. groups = "nand0_dqs_0_grp";
  364. function = "nand0_dqs";
  365. };
  366. conf-dqs {
  367. groups = "nand0_dqs_0_grp";
  368. bias-pull-up;
  369. };
  370. };
  371. pinctrl_spi0_default: spi0-default {
  372. mux {
  373. groups = "spi0_0_grp";
  374. function = "spi0";
  375. };
  376. conf {
  377. groups = "spi0_0_grp";
  378. bias-disable;
  379. slew-rate = <SLEW_RATE_SLOW>;
  380. power-source = <IO_STANDARD_LVCMOS18>;
  381. };
  382. mux-cs {
  383. groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
  384. "spi0_ss_2_grp";
  385. function = "spi0_ss";
  386. };
  387. conf-cs {
  388. groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
  389. "spi0_ss_2_grp";
  390. bias-disable;
  391. };
  392. };
  393. pinctrl_spi1_default: spi1-default {
  394. mux {
  395. groups = "spi1_3_grp";
  396. function = "spi1";
  397. };
  398. conf {
  399. groups = "spi1_3_grp";
  400. bias-disable;
  401. slew-rate = <SLEW_RATE_SLOW>;
  402. power-source = <IO_STANDARD_LVCMOS18>;
  403. };
  404. mux-cs {
  405. groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
  406. "spi1_ss_11_grp";
  407. function = "spi1_ss";
  408. };
  409. conf-cs {
  410. groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
  411. "spi1_ss_11_grp";
  412. bias-disable;
  413. };
  414. };
  415. };
  416. &rtc {
  417. status = "okay";
  418. };
  419. &spi0 {
  420. status = "okay";
  421. num-cs = <1>;
  422. pinctrl-names = "default";
  423. pinctrl-0 = <&pinctrl_spi0_default>;
  424. spi0_flash0: flash@0 {
  425. #address-cells = <1>;
  426. #size-cells = <1>;
  427. compatible = "sst,sst25wf080", "jedec,spi-nor";
  428. spi-max-frequency = <50000000>;
  429. reg = <0>;
  430. partition@0 {
  431. label = "spi0-data";
  432. reg = <0x0 0x100000>;
  433. };
  434. };
  435. };
  436. &spi1 {
  437. status = "okay";
  438. num-cs = <1>;
  439. pinctrl-names = "default";
  440. pinctrl-0 = <&pinctrl_spi1_default>;
  441. spi1_flash0: flash@0 {
  442. #address-cells = <1>;
  443. #size-cells = <1>;
  444. compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
  445. spi-max-frequency = <20000000>;
  446. reg = <0>;
  447. partition@0 {
  448. label = "spi1-data";
  449. reg = <0x0 0x84000>;
  450. };
  451. };
  452. };
  453. /* ULPI SMSC USB3320 */
  454. &usb1 {
  455. status = "okay";
  456. pinctrl-names = "default";
  457. pinctrl-0 = <&pinctrl_usb1_default>;
  458. };
  459. &dwc3_1 {
  460. status = "okay";
  461. dr_mode = "host";
  462. };
  463. &uart0 {
  464. status = "okay";
  465. pinctrl-names = "default";
  466. pinctrl-0 = <&pinctrl_uart0_default>;
  467. };
  468. &uart1 {
  469. status = "okay";
  470. pinctrl-names = "default";
  471. pinctrl-0 = <&pinctrl_uart1_default>;
  472. };