zynqmp-e-a2197-00-revA.dts 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * dts file for Xilinx Versal a2197 RevA System Controller
  4. *
  5. * (C) Copyright 2019 - 2021, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/phy/phy.h>
  14. / {
  15. model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
  16. compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
  17. "xlnx,zynqmp-a2197", "xlnx,zynqmp";
  18. aliases {
  19. ethernet0 = &gem0;
  20. i2c0 = &i2c0;
  21. i2c1 = &i2c1;
  22. mmc0 = &sdhci1;
  23. nvmem0 = &eeprom;
  24. nvmem1 = &eeprom_ebm;
  25. nvmem2 = &eeprom_fmc1;
  26. nvmem3 = &eeprom_fmc2;
  27. rtc0 = &rtc;
  28. serial0 = &uart0;
  29. serial1 = &dcc;
  30. };
  31. chosen {
  32. bootargs = "earlycon";
  33. stdout-path = "serial0:115200n8";
  34. };
  35. memory@0 {
  36. device_type = "memory";
  37. reg = <0x0 0x0 0x0 0x80000000>;
  38. };
  39. ina226-vccint {
  40. compatible = "iio-hwmon";
  41. io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
  42. };
  43. ina226-vcc-soc {
  44. compatible = "iio-hwmon";
  45. io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
  46. };
  47. ina226-vcc-pmc {
  48. compatible = "iio-hwmon";
  49. io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
  50. };
  51. ina226-vcc-ram {
  52. compatible = "iio-hwmon";
  53. io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
  54. };
  55. ina226-vcc-pslp {
  56. compatible = "iio-hwmon";
  57. io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
  58. };
  59. ina226-vcc-psfp {
  60. compatible = "iio-hwmon";
  61. io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
  62. };
  63. ina226-vccaux {
  64. compatible = "iio-hwmon";
  65. io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
  66. };
  67. ina226-vccaux-pmc {
  68. compatible = "iio-hwmon";
  69. io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
  70. };
  71. ina226-vcco-500 {
  72. compatible = "iio-hwmon";
  73. io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
  74. };
  75. ina226-vcco-501 {
  76. compatible = "iio-hwmon";
  77. io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
  78. };
  79. ina226-vcco-502 {
  80. compatible = "iio-hwmon";
  81. io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
  82. };
  83. ina226-vcco-503 {
  84. compatible = "iio-hwmon";
  85. io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
  86. };
  87. ina226-vcc-1v8 {
  88. compatible = "iio-hwmon";
  89. io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
  90. };
  91. ina226-vcc-3v3 {
  92. compatible = "iio-hwmon";
  93. io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
  94. };
  95. ina226-vcc-1v2-ddr4 {
  96. compatible = "iio-hwmon";
  97. io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
  98. };
  99. ina226-vcc-1v1-lp4 {
  100. compatible = "iio-hwmon";
  101. io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
  102. };
  103. ina226-vadj-fmc {
  104. compatible = "iio-hwmon";
  105. io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
  106. };
  107. ina226-mgtyavcc {
  108. compatible = "iio-hwmon";
  109. io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
  110. };
  111. ina226-mgtyavtt {
  112. compatible = "iio-hwmon";
  113. io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
  114. };
  115. ina226-mgtyvccaux {
  116. compatible = "iio-hwmon";
  117. io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
  118. };
  119. };
  120. &uart0 { /* uart0 MIO38-39 */
  121. status = "okay";
  122. };
  123. &sdhci1 { /* sd1 MIO45-51 cd in place */
  124. status = "okay";
  125. no-1-8-v;
  126. disable-wp;
  127. xlnx,mio-bank = <1>;
  128. };
  129. &gem0 {
  130. status = "okay";
  131. phy-handle = <&phy0>;
  132. phy-mode = "sgmii";
  133. is-internal-pcspma;
  134. phy0: ethernet-phy@0 { /* u131 M88E1512 */
  135. reg = <0>;
  136. };
  137. };
  138. &gpio {
  139. status = "okay";
  140. gpio-line-names = "", "", "", "", "", /* 0 - 4 */
  141. "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
  142. "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
  143. "", "", "", "", "", /* 15 - 19 */
  144. "", "", "", "", "", /* 20 - 24 */
  145. "", "", "", "", "", /* 25 - 29 */
  146. "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
  147. "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
  148. "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
  149. "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
  150. "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
  151. "", "", "", "", "", /* 55 - 59 */
  152. "", "", "", "", "", /* 60 - 64 */
  153. "", "", "", "", "", /* 65 - 69 */
  154. "", "", "", "", "", /* 70 - 74 */
  155. "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
  156. "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
  157. "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
  158. "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
  159. "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
  160. "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
  161. "", "", "", "", "", /* 100 - 104 */
  162. "", "", "", "", "", /* 105 - 109 */
  163. "", "", "", "", "", /* 110 - 114 */
  164. "", "", "", "", "", /* 115 - 119 */
  165. "", "", "", "", "", /* 120 - 124 */
  166. "", "", "", "", "", /* 125 - 129 */
  167. "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
  168. "", "", "", "", "", /* 135 - 139 */
  169. "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
  170. "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
  171. "", "", "", "", "", /* 150 - 154 */
  172. "", "", "", "", "", /* 155 - 159 */
  173. "", "", "", "", "", /* 160 - 164 */
  174. "", "", "", "", "", /* 165 - 169 */
  175. "", "", "", ""; /* 170 - 174 */
  176. };
  177. &i2c0 { /* MIO 34-35 - can't stay here */
  178. status = "okay";
  179. clock-frequency = <400000>;
  180. i2c-mux@74 { /* u33 */
  181. compatible = "nxp,pca9548";
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. reg = <0x74>;
  185. /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
  186. i2c@0 { /* PMBUS */
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. reg = <0>;
  190. /* u152 IR35215 0x16/0x46 vcc_soc */
  191. /* u179 ir38164 0x19/0x49 vcco_500 */
  192. /* u181 ir38164 0x1a/0x4a vcco_501 */
  193. /* u183 ir38164 0x1b/0x4b vcco_502 */
  194. /* u185 ir38164 0x1e/0x4e vadj_fmc */
  195. /* u187 ir38164 0x1F/0x4f mgtyavcc */
  196. /* u189 ir38164 0x20/0x50 mgtyavtt */
  197. /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
  198. /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
  199. irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
  200. compatible = "infineon,irps5401";
  201. reg = <0x47>; /* pmbus / i2c 0x17 */
  202. };
  203. irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
  204. compatible = "infineon,irps5401";
  205. reg = <0x4c>; /* pmbus / i2c 0x1c */
  206. };
  207. irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
  208. compatible = "infineon,irps5401";
  209. reg = <0x4d>; /* pmbus / i2c 0x1d */
  210. };
  211. };
  212. i2c@1 { /* PMBUS1_INA226 */
  213. #address-cells = <1>;
  214. #size-cells = <0>;
  215. reg = <1>;
  216. /* FIXME check alerts coming to SC */
  217. vccint: ina226@40 { /* u65 */
  218. compatible = "ti,ina226";
  219. #io-channel-cells = <1>;
  220. label = "ina226-vccint";
  221. reg = <0x40>;
  222. shunt-resistor = <500>; /* R440 */
  223. /* 0.80V @ 32A 1 of 6 Phases*/
  224. };
  225. vcc_soc: ina226@41 { /* u161 */
  226. compatible = "ti,ina226";
  227. #io-channel-cells = <1>;
  228. label = "ina226-vcc-soc";
  229. reg = <0x41>;
  230. shunt-resistor = <500>; /* R1702 */
  231. /* 0.80V @ 18A */
  232. };
  233. vcc_pmc: ina226@42 { /* u163 */
  234. compatible = "ti,ina226";
  235. #io-channel-cells = <1>;
  236. label = "ina226-vcc-pmc";
  237. reg = <0x42>;
  238. shunt-resistor = <5000>; /* R1214 */
  239. /* 0.78V @ 500mA */
  240. };
  241. vcc_ram: ina226@43 { /* u162 */
  242. compatible = "ti,ina226";
  243. #io-channel-cells = <1>;
  244. label = "ina226-vcc-ram";
  245. reg = <0x43>;
  246. shunt-resistor = <5000>; /* r1221 */
  247. /* 0.78V @ 4A */
  248. };
  249. vcc_pslp: ina226@44 { /* u165 */
  250. compatible = "ti,ina226";
  251. #io-channel-cells = <1>;
  252. label = "ina226-vcc-pslp";
  253. reg = <0x44>;
  254. shunt-resistor = <5000>; /* R1216 */
  255. /* 0.78V @ 1A */
  256. };
  257. vcc_psfp: ina226@45 { /* u164 */
  258. compatible = "ti,ina226";
  259. #io-channel-cells = <1>;
  260. label = "ina226-vcc-psfp";
  261. reg = <0x45>;
  262. shunt-resistor = <5000>; /* R1219 */
  263. /* 0.78V @ 2A */
  264. };
  265. };
  266. i2c@2 { /* PCIE_CLK */
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. reg = <2>;
  270. clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
  271. #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
  272. compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
  273. reg = <0xd8>;
  274. /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
  275. /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
  276. };
  277. };
  278. i2c@3 { /* PMBUS2_INA226 */
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. reg = <3>;
  282. /* FIXME check alerts coming to SC */
  283. vccaux: ina226@40 { /* u166 */
  284. compatible = "ti,ina226";
  285. #io-channel-cells = <1>;
  286. label = "ina226-vccaux";
  287. reg = <0x40>;
  288. shunt-resistor = <5000>; /* R382 */
  289. /* 1.5V @ 3A */
  290. };
  291. vccaux_pmc: ina226@41 { /* u168 */
  292. compatible = "ti,ina226";
  293. #io-channel-cells = <1>;
  294. label = "ina226-vccaux-pmc";
  295. reg = <0x41>;
  296. shunt-resistor = <5000>; /* R1246 */
  297. /* 1.5V @ 500mA */
  298. };
  299. vcco_500: ina226@42 { /* u178 */
  300. compatible = "ti,ina226";
  301. #io-channel-cells = <1>;
  302. label = "ina226-vcco-500";
  303. reg = <0x42>;
  304. shunt-resistor = <2000>; /* R1300 */
  305. /* 3.3V @ 5A */
  306. };
  307. vcco_501: ina226@43 { /* u180 */
  308. compatible = "ti,ina226";
  309. #io-channel-cells = <1>;
  310. label = "ina226-vcco-501";
  311. reg = <0x43>;
  312. shunt-resistor = <2000>; /* R1313 */
  313. /* 3.3V @ 5A */
  314. };
  315. vcco_502: ina226@44 { /* u182 */
  316. compatible = "ti,ina226";
  317. #io-channel-cells = <1>;
  318. label = "ina226-vcco-502";
  319. reg = <0x44>;
  320. shunt-resistor = <2000>; /* R1330 */
  321. /* 3.3V @ 5A */
  322. };
  323. vcco_503: ina226@45 { /* u172 */
  324. compatible = "ti,ina226";
  325. #io-channel-cells = <1>;
  326. label = "ina226-vcco-503";
  327. reg = <0x45>;
  328. shunt-resistor = <5000>; /* R1229 */
  329. /* 1.8V @ 2A */
  330. };
  331. vcc_1v8: ina226@46 { /* u173 */
  332. compatible = "ti,ina226";
  333. #io-channel-cells = <1>;
  334. label = "ina226-vcc-1v8";
  335. reg = <0x46>;
  336. shunt-resistor = <5000>; /* R400 */
  337. /* 1.8V @ 6A */
  338. };
  339. vcc_3v3: ina226@47 { /* u174 */
  340. compatible = "ti,ina226";
  341. #io-channel-cells = <1>;
  342. label = "ina226-vcc-3v3";
  343. reg = <0x47>;
  344. shunt-resistor = <5000>; /* R1232 */
  345. /* 3.3V @ 500mA */
  346. };
  347. vcc_1v2_ddr4: ina226@48 { /* u176 */
  348. compatible = "ti,ina226";
  349. #io-channel-cells = <1>;
  350. label = "ina226-vcc-1v2-ddr4";
  351. reg = <0x48>;
  352. shunt-resistor = <5000>; /* R1275 */
  353. /* 1.2V @ 4A */
  354. };
  355. vcc1v1_lp4: ina226@49 { /* u177 */
  356. compatible = "ti,ina226";
  357. #io-channel-cells = <1>;
  358. label = "ina226-vcc1v1-lp4";
  359. reg = <0x49>;
  360. shunt-resistor = <5000>; /* R1286 */
  361. /* 1.1V @ 4A */
  362. };
  363. vadj_fmc: ina226@4a { /* u184 */
  364. compatible = "ti,ina226";
  365. #io-channel-cells = <1>;
  366. label = "ina226-vadj-fmc";
  367. reg = <0x4a>;
  368. shunt-resistor = <2000>; /* R1350 */
  369. /* 1.5V @ 10A */
  370. };
  371. mgtyavcc: ina226@4b { /* u186 */
  372. compatible = "ti,ina226";
  373. #io-channel-cells = <1>;
  374. label = "ina226-mgtyavcc";
  375. reg = <0x4b>;
  376. shunt-resistor = <2000>; /* R1367 */
  377. /* 0.88V @ 6A */
  378. };
  379. mgtyavtt: ina226@4c { /* u188 */
  380. compatible = "ti,ina226";
  381. #io-channel-cells = <1>;
  382. label = "ina226-mgtyavtt";
  383. reg = <0x4c>;
  384. shunt-resistor = <2000>; /* R1384 */
  385. /* 1.2V @ 10A */
  386. };
  387. mgtyvccaux: ina226@4d { /* u234 */
  388. compatible = "ti,ina226";
  389. #io-channel-cells = <1>;
  390. label = "ina226-mgtyvccaux";
  391. reg = <0x4d>;
  392. shunt-resistor = <5000>; /* r1679 */
  393. /* 1.5V @ 500mA */
  394. };
  395. };
  396. i2c@4 { /* LP_I2C_SM */
  397. #address-cells = <1>;
  398. #size-cells = <0>;
  399. reg = <4>;
  400. /* FIXME wires ready but chip is missing */
  401. };
  402. i2c@5 { /* zSFP_SI570 */
  403. #address-cells = <1>;
  404. #size-cells = <0>;
  405. reg = <5>;
  406. si570_zsfp: clock-generator@5d { /* u192 */
  407. #clock-cells = <0>;
  408. compatible = "silabs,si570";
  409. reg = <0x5d>;
  410. temperature-stability = <50>;
  411. factory-fout = <156250000>;
  412. clock-frequency = <156250000>;
  413. clock-output-names = "si570_zsfp_clk";
  414. };
  415. };
  416. i2c@6 { /* USER_SI570_1 */
  417. #address-cells = <1>;
  418. #size-cells = <0>;
  419. reg = <6>;
  420. si570_user1: clock-generator@5d { /* u205 */
  421. #clock-cells = <0>;
  422. compatible = "silabs,si570";
  423. reg = <0x5f>;
  424. temperature-stability = <50>;
  425. factory-fout = <100000000>;
  426. clock-frequency = <100000000>;
  427. clock-output-names = "si570_user1";
  428. };
  429. };
  430. i2c@7 { /* USER_SI570_2 */
  431. #address-cells = <1>;
  432. #size-cells = <0>;
  433. reg = <7>;
  434. /* FIXME wires ready but chip is missing */
  435. };
  436. };
  437. };
  438. &i2c1 { /* i2c1 MIO 36-37 */
  439. status = "okay";
  440. clock-frequency = <400000>;
  441. i2c-mux@74 { /* u35 */
  442. compatible = "nxp,pca9548";
  443. #address-cells = <1>;
  444. #size-cells = <0>;
  445. reg = <0x74>;
  446. i2c-mux-idle-disconnect;
  447. /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
  448. dc_i2c: i2c@0 { /* DC_I2C */
  449. #address-cells = <1>;
  450. #size-cells = <0>;
  451. reg = <0>;
  452. /* Use for storing information about SC board */
  453. eeprom: eeprom@54 { /* u34 - m24128 16kB */
  454. compatible = "st,24c128", "atmel,24c128";
  455. reg = <0x54>; /* 0x5c too */
  456. };
  457. si570_ref_clk: clock-generator@5d { /* u32 */
  458. #clock-cells = <0>;
  459. compatible = "silabs,si570";
  460. reg = <0x5d>;
  461. temperature-stability = <50>;
  462. factory-fout = <33333333>;
  463. clock-frequency = <33333333>;
  464. clock-output-names = "ref_clk";
  465. silabs,skip-recall;
  466. };
  467. /* and connector J212D */
  468. eeprom_ebm: eeprom@52 { /* x-ebm module */
  469. compatible = "st,24c128", "atmel,24c128";
  470. reg = <0x52>;
  471. };
  472. };
  473. fmc1: i2c@1 { /* FMCP1_IIC */
  474. #address-cells = <1>;
  475. #size-cells = <0>;
  476. reg = <1>;
  477. /* FIXME connection to Samtec J51C */
  478. /* expected eeprom 0x50 FMC cards */
  479. eeprom_fmc1: eeprom@50 {
  480. compatible = "st,24c128", "atmel,24c128";
  481. reg = <0x50>;
  482. };
  483. };
  484. fmc2: i2c@2 { /* FMCP2_IIC */
  485. #address-cells = <1>;
  486. #size-cells = <0>;
  487. reg = <2>;
  488. /* FIXME connection to Samtec J53C */
  489. /* expected eeprom 0x50 FMC cards */
  490. eeprom_fmc2: eeprom@50 {
  491. compatible = "st,24c128", "atmel,24c128";
  492. reg = <0x50>;
  493. };
  494. };
  495. i2c@3 { /* DDR4_DIMM1 */
  496. #address-cells = <1>;
  497. #size-cells = <0>;
  498. reg = <3>;
  499. si570_ddr_dimm1: clock-generator@60 { /* u2 */
  500. #clock-cells = <0>;
  501. compatible = "silabs,si570";
  502. reg = <0x60>;
  503. temperature-stability = <50>;
  504. factory-fout = <200000000>;
  505. clock-frequency = <200000000>;
  506. clock-output-names = "si570_ddrdimm1_clk";
  507. silabs,skip-recall;
  508. };
  509. };
  510. i2c@4 { /* LPDDR4_SI570_CLK2 */
  511. #address-cells = <1>;
  512. #size-cells = <0>;
  513. reg = <4>;
  514. si570_lpddr4clk2: clock-generator@60 { /* u3 */
  515. #clock-cells = <0>;
  516. compatible = "silabs,si570";
  517. reg = <0x60>;
  518. temperature-stability = <50>;
  519. factory-fout = <200000000>;
  520. clock-frequency = <200000000>;
  521. clock-output-names = "si570_lpddr4_clk2";
  522. };
  523. };
  524. i2c@5 { /* LPDDR4_SI570_CLK1 */
  525. #address-cells = <1>;
  526. #size-cells = <0>;
  527. reg = <5>;
  528. si570_lpddr4clk1: clock-generator@60 { /* u4 */
  529. #clock-cells = <0>;
  530. compatible = "silabs,si570";
  531. reg = <0x60>;
  532. temperature-stability = <50>;
  533. factory-fout = <200000000>;
  534. clock-frequency = <200000000>;
  535. clock-output-names = "si570_lpddr4_clk1";
  536. };
  537. };
  538. i2c@6 { /* HSDP_SI570 */
  539. #address-cells = <1>;
  540. #size-cells = <0>;
  541. reg = <6>;
  542. si570_hsdp: clock-generator@5d { /* u5 */
  543. #clock-cells = <0>;
  544. compatible = "silabs,si570";
  545. reg = <0x5d>;
  546. temperature-stability = <50>;
  547. factory-fout = <156250000>;
  548. clock-frequency = <156250000>;
  549. clock-output-names = "si570_hsdp_clk";
  550. };
  551. };
  552. i2c@7 { /* 8A34001 - U219B and J310 connector */
  553. #address-cells = <1>;
  554. #size-cells = <0>;
  555. reg = <7>;
  556. };
  557. };
  558. i2c-mux@75 { /* u214 */
  559. compatible = "nxp,pca9548";
  560. #address-cells = <1>;
  561. #size-cells = <0>;
  562. reg = <0x75>;
  563. i2c-mux-idle-disconnect;
  564. i2c@0 { /* SFP0_IIC */
  565. #address-cells = <1>;
  566. #size-cells = <0>;
  567. reg = <0>;
  568. /* SFP0 */
  569. };
  570. i2c@1 { /* SFP1_IIC */
  571. #address-cells = <1>;
  572. #size-cells = <0>;
  573. reg = <1>;
  574. /* SFP1 */
  575. };
  576. i2c@2 { /* QSFP1_I2C */
  577. #address-cells = <1>;
  578. #size-cells = <0>;
  579. reg = <2>;
  580. /* QSFP1 */
  581. };
  582. /* 3 - 7 unused */
  583. };
  584. };
  585. &xilinx_ams {
  586. status = "okay";
  587. };
  588. &ams_ps {
  589. status = "okay";
  590. };
  591. &ams_pl {
  592. status = "okay";
  593. };