imx7d-sdb.dts 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. */
  5. /dts-v1/;
  6. #include "imx7d.dtsi"
  7. / {
  8. model = "Freescale i.MX7 SabreSD Board";
  9. compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  10. chosen {
  11. stdout-path = &uart1;
  12. };
  13. memory@80000000 {
  14. device_type = "memory";
  15. reg = <0x80000000 0x80000000>;
  16. };
  17. gpio-keys {
  18. compatible = "gpio-keys";
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&pinctrl_gpio_keys>;
  21. volume-up {
  22. label = "Volume Up";
  23. gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
  24. linux,code = <KEY_VOLUMEUP>;
  25. wakeup-source;
  26. };
  27. volume-down {
  28. label = "Volume Down";
  29. gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
  30. linux,code = <KEY_VOLUMEDOWN>;
  31. wakeup-source;
  32. };
  33. };
  34. spi4 {
  35. compatible = "spi-gpio";
  36. pinctrl-names = "default";
  37. pinctrl-0 = <&pinctrl_spi4>;
  38. gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  39. gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  40. cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  41. num-chipselects = <1>;
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. extended_io: gpio-expander@0 {
  45. compatible = "fairchild,74hc595";
  46. gpio-controller;
  47. #gpio-cells = <2>;
  48. reg = <0>;
  49. registers-number = <1>;
  50. spi-max-frequency = <100000>;
  51. };
  52. };
  53. reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  54. compatible = "regulator-fixed";
  55. regulator-name = "usb_otg1_vbus";
  56. regulator-min-microvolt = <5000000>;
  57. regulator-max-microvolt = <5000000>;
  58. gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  59. enable-active-high;
  60. };
  61. reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  62. compatible = "regulator-fixed";
  63. regulator-name = "usb_otg2_vbus";
  64. pinctrl-names = "default";
  65. pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
  66. regulator-min-microvolt = <5000000>;
  67. regulator-max-microvolt = <5000000>;
  68. gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  69. enable-active-high;
  70. };
  71. reg_vref_1v8: regulator-vref-1v8 {
  72. compatible = "regulator-fixed";
  73. regulator-name = "vref-1v8";
  74. regulator-min-microvolt = <1800000>;
  75. regulator-max-microvolt = <1800000>;
  76. };
  77. reg_brcm: regulator-brcm {
  78. compatible = "regulator-fixed";
  79. gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  80. enable-active-high;
  81. regulator-name = "brcm_reg";
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&pinctrl_brcm_reg>;
  84. regulator-min-microvolt = <3300000>;
  85. regulator-max-microvolt = <3300000>;
  86. startup-delay-us = <200000>;
  87. };
  88. reg_lcd_3v3: regulator-lcd-3v3 {
  89. compatible = "regulator-fixed";
  90. regulator-name = "lcd-3v3";
  91. regulator-min-microvolt = <3300000>;
  92. regulator-max-microvolt = <3300000>;
  93. gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
  94. };
  95. reg_can2_3v3: regulator-can2-3v3 {
  96. compatible = "regulator-fixed";
  97. regulator-name = "can2-3v3";
  98. pinctrl-names = "default";
  99. pinctrl-0 = <&pinctrl_flexcan2_reg>;
  100. regulator-min-microvolt = <3300000>;
  101. regulator-max-microvolt = <3300000>;
  102. gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
  103. };
  104. reg_fec2_3v3: regulator-fec2-3v3 {
  105. compatible = "regulator-fixed";
  106. regulator-name = "fec2-3v3";
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&pinctrl_enet2_reg>;
  109. regulator-min-microvolt = <3300000>;
  110. regulator-max-microvolt = <3300000>;
  111. gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
  112. };
  113. backlight: backlight {
  114. compatible = "pwm-backlight";
  115. pwms = <&pwm1 0 5000000 0>;
  116. brightness-levels = <0 4 8 16 32 64 128 255>;
  117. default-brightness-level = <6>;
  118. status = "okay";
  119. };
  120. panel {
  121. compatible = "innolux,at043tn24";
  122. backlight = <&backlight>;
  123. power-supply = <&reg_lcd_3v3>;
  124. port {
  125. panel_in: endpoint {
  126. remote-endpoint = <&display_out>;
  127. };
  128. };
  129. };
  130. };
  131. &adc1 {
  132. vref-supply = <&reg_vref_1v8>;
  133. status = "okay";
  134. };
  135. &adc2 {
  136. vref-supply = <&reg_vref_1v8>;
  137. status = "okay";
  138. };
  139. &cpu0 {
  140. cpu-supply = <&sw1a_reg>;
  141. };
  142. &ecspi3 {
  143. pinctrl-names = "default";
  144. pinctrl-0 = <&pinctrl_ecspi3>;
  145. cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
  146. status = "okay";
  147. tsc2046@0 {
  148. compatible = "ti,tsc2046";
  149. reg = <0>;
  150. spi-max-frequency = <1000000>;
  151. pinctrl-names ="default";
  152. pinctrl-0 = <&pinctrl_tsc2046_pendown>;
  153. interrupt-parent = <&gpio2>;
  154. interrupts = <29 0>;
  155. pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
  156. ti,x-min = /bits/ 16 <0>;
  157. ti,x-max = /bits/ 16 <0>;
  158. ti,y-min = /bits/ 16 <0>;
  159. ti,y-max = /bits/ 16 <0>;
  160. ti,pressure-max = /bits/ 16 <0>;
  161. ti,x-plate-ohms = /bits/ 16 <400>;
  162. wakeup-source;
  163. };
  164. };
  165. &fec1 {
  166. pinctrl-names = "default";
  167. pinctrl-0 = <&pinctrl_enet1>;
  168. assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
  169. <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
  170. assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  171. assigned-clock-rates = <0>, <100000000>;
  172. phy-mode = "rgmii";
  173. phy-handle = <&ethphy0>;
  174. fsl,magic-packet;
  175. phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
  176. status = "okay";
  177. mdio {
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. ethphy0: ethernet-phy@0 {
  181. reg = <0>;
  182. };
  183. ethphy1: ethernet-phy@1 {
  184. reg = <1>;
  185. };
  186. };
  187. };
  188. &fec2 {
  189. pinctrl-names = "default";
  190. pinctrl-0 = <&pinctrl_enet2>;
  191. assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
  192. <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
  193. assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
  194. assigned-clock-rates = <0>, <100000000>;
  195. phy-mode = "rgmii";
  196. phy-handle = <&ethphy1>;
  197. phy-supply = <&reg_fec2_3v3>;
  198. fsl,magic-packet;
  199. status = "okay";
  200. };
  201. &flexcan2 {
  202. pinctrl-names = "default";
  203. pinctrl-0 = <&pinctrl_flexcan2>;
  204. xceiver-supply = <&reg_can2_3v3>;
  205. status = "okay";
  206. };
  207. &i2c1 {
  208. pinctrl-names = "default";
  209. pinctrl-0 = <&pinctrl_i2c1>;
  210. status = "okay";
  211. pmic: pfuze3000@8 {
  212. compatible = "fsl,pfuze3000";
  213. reg = <0x08>;
  214. regulators {
  215. sw1a_reg: sw1a {
  216. regulator-min-microvolt = <700000>;
  217. regulator-max-microvolt = <1475000>;
  218. regulator-boot-on;
  219. regulator-always-on;
  220. regulator-ramp-delay = <6250>;
  221. };
  222. /* use sw1c_reg to align with pfuze100/pfuze200 */
  223. sw1c_reg: sw1b {
  224. regulator-min-microvolt = <700000>;
  225. regulator-max-microvolt = <1475000>;
  226. regulator-boot-on;
  227. regulator-always-on;
  228. regulator-ramp-delay = <6250>;
  229. };
  230. sw2_reg: sw2 {
  231. regulator-min-microvolt = <1800000>;
  232. regulator-max-microvolt = <1800000>;
  233. regulator-boot-on;
  234. regulator-always-on;
  235. };
  236. sw3a_reg: sw3 {
  237. regulator-min-microvolt = <900000>;
  238. regulator-max-microvolt = <1650000>;
  239. regulator-boot-on;
  240. regulator-always-on;
  241. };
  242. swbst_reg: swbst {
  243. regulator-min-microvolt = <5000000>;
  244. regulator-max-microvolt = <5150000>;
  245. };
  246. snvs_reg: vsnvs {
  247. regulator-min-microvolt = <1000000>;
  248. regulator-max-microvolt = <3000000>;
  249. regulator-boot-on;
  250. regulator-always-on;
  251. };
  252. vref_reg: vrefddr {
  253. regulator-boot-on;
  254. regulator-always-on;
  255. };
  256. vgen1_reg: vldo1 {
  257. regulator-min-microvolt = <1800000>;
  258. regulator-max-microvolt = <3300000>;
  259. regulator-always-on;
  260. };
  261. vgen2_reg: vldo2 {
  262. regulator-min-microvolt = <800000>;
  263. regulator-max-microvolt = <1550000>;
  264. };
  265. vgen3_reg: vccsd {
  266. regulator-min-microvolt = <2850000>;
  267. regulator-max-microvolt = <3300000>;
  268. regulator-always-on;
  269. };
  270. vgen4_reg: v33 {
  271. regulator-min-microvolt = <2850000>;
  272. regulator-max-microvolt = <3300000>;
  273. regulator-always-on;
  274. };
  275. vgen5_reg: vldo3 {
  276. regulator-min-microvolt = <1800000>;
  277. regulator-max-microvolt = <3300000>;
  278. regulator-always-on;
  279. };
  280. vgen6_reg: vldo4 {
  281. regulator-min-microvolt = <2800000>;
  282. regulator-max-microvolt = <2800000>;
  283. regulator-always-on;
  284. };
  285. };
  286. };
  287. };
  288. &i2c2 {
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&pinctrl_i2c2>;
  291. status = "okay";
  292. mpl3115@60 {
  293. compatible = "fsl,mpl3115";
  294. reg = <0x60>;
  295. };
  296. };
  297. &i2c3 {
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_i2c3>;
  300. status = "okay";
  301. };
  302. &i2c4 {
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_i2c4>;
  305. status = "okay";
  306. codec: wm8960@1a {
  307. compatible = "wlf,wm8960";
  308. reg = <0x1a>;
  309. clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  310. clock-names = "mclk";
  311. wlf,shared-lrclk;
  312. };
  313. };
  314. &lcdif {
  315. pinctrl-names = "default";
  316. pinctrl-0 = <&pinctrl_lcdif>;
  317. status = "okay";
  318. port {
  319. display_out: endpoint {
  320. remote-endpoint = <&panel_in>;
  321. };
  322. };
  323. };
  324. &snvs_pwrkey {
  325. status = "okay";
  326. };
  327. &uart1 {
  328. pinctrl-names = "default";
  329. pinctrl-0 = <&pinctrl_uart1>;
  330. assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
  331. assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  332. status = "okay";
  333. };
  334. &uart6 {
  335. pinctrl-names = "default";
  336. pinctrl-0 = <&pinctrl_uart6>;
  337. assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
  338. assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
  339. uart-has-rtscts;
  340. status = "okay";
  341. };
  342. &usbotg1 {
  343. vbus-supply = <&reg_usb_otg1_vbus>;
  344. status = "okay";
  345. };
  346. &usbotg2 {
  347. vbus-supply = <&reg_usb_otg2_vbus>;
  348. dr_mode = "host";
  349. status = "okay";
  350. };
  351. &usdhc1 {
  352. pinctrl-names = "default";
  353. pinctrl-0 = <&pinctrl_usdhc1>;
  354. cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
  355. wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  356. wakeup-source;
  357. keep-power-in-suspend;
  358. status = "okay";
  359. };
  360. &usdhc2 {
  361. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  362. pinctrl-0 = <&pinctrl_usdhc2>;
  363. pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
  364. pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
  365. wakeup-source;
  366. keep-power-in-suspend;
  367. non-removable;
  368. vmmc-supply = <&reg_brcm>;
  369. fsl,tuning-step = <2>;
  370. status = "okay";
  371. };
  372. &usdhc3 {
  373. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  374. pinctrl-0 = <&pinctrl_usdhc3>;
  375. pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  376. pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  377. assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
  378. assigned-clock-rates = <400000000>;
  379. bus-width = <8>;
  380. fsl,tuning-step = <2>;
  381. non-removable;
  382. status = "okay";
  383. };
  384. &wdog1 {
  385. pinctrl-names = "default";
  386. pinctrl-0 = <&pinctrl_wdog>;
  387. fsl,ext-reset-output;
  388. };
  389. &iomuxc {
  390. pinctrl-names = "default";
  391. pinctrl-0 = <&pinctrl_hog>;
  392. imx7d-sdb {
  393. pinctrl_brcm_reg: brcmreggrp {
  394. fsl,pins = <
  395. MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14
  396. >;
  397. };
  398. pinctrl_ecspi3: ecspi3grp {
  399. fsl,pins = <
  400. MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2
  401. MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2
  402. MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2
  403. MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59
  404. >;
  405. };
  406. pinctrl_enet1: enet1grp {
  407. fsl,pins = <
  408. MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
  409. MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
  410. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
  411. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
  412. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
  413. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
  414. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
  415. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
  416. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
  417. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
  418. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
  419. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
  420. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
  421. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
  422. >;
  423. };
  424. pinctrl_enet2: enet2grp {
  425. fsl,pins = <
  426. MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
  427. MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
  428. MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
  429. MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
  430. MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
  431. MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
  432. MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
  433. MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
  434. MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
  435. MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
  436. MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
  437. MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
  438. >;
  439. };
  440. pinctrl_enet2_reg: enet2reggrp {
  441. fsl,pins = <
  442. MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14
  443. >;
  444. };
  445. pinctrl_flexcan2: flexcan2grp {
  446. fsl,pins = <
  447. MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
  448. MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
  449. >;
  450. };
  451. pinctrl_flexcan2_reg: flexcan2reggrp {
  452. fsl,pins = <
  453. MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */
  454. >;
  455. };
  456. pinctrl_gpio_keys: gpio_keysgrp {
  457. fsl,pins = <
  458. MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59
  459. MX7D_PAD_SD2_WP__GPIO5_IO10 0x59
  460. >;
  461. };
  462. pinctrl_hog: hoggrp {
  463. fsl,pins = <
  464. MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */
  465. >;
  466. };
  467. pinctrl_i2c1: i2c1grp {
  468. fsl,pins = <
  469. MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
  470. MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
  471. >;
  472. };
  473. pinctrl_i2c2: i2c2grp {
  474. fsl,pins = <
  475. MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
  476. MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
  477. >;
  478. };
  479. pinctrl_i2c3: i2c3grp {
  480. fsl,pins = <
  481. MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
  482. MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
  483. >;
  484. };
  485. pinctrl_i2c4: i2c4grp {
  486. fsl,pins = <
  487. MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
  488. MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
  489. >;
  490. };
  491. pinctrl_lcdif: lcdifgrp {
  492. fsl,pins = <
  493. MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
  494. MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
  495. MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
  496. MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
  497. MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
  498. MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
  499. MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
  500. MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
  501. MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
  502. MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
  503. MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
  504. MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
  505. MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
  506. MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
  507. MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
  508. MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
  509. MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
  510. MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
  511. MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
  512. MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
  513. MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
  514. MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
  515. MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
  516. MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
  517. MX7D_PAD_LCD_CLK__LCD_CLK 0x79
  518. MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
  519. MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
  520. MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
  521. MX7D_PAD_LCD_RESET__LCD_RESET 0x79
  522. >;
  523. };
  524. pinctrl_spi4: spi4grp {
  525. fsl,pins = <
  526. MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
  527. MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
  528. MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
  529. >;
  530. };
  531. pinctrl_tsc2046_pendown: tsc2046_pendown {
  532. fsl,pins = <
  533. MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
  534. >;
  535. };
  536. pinctrl_uart1: uart1grp {
  537. fsl,pins = <
  538. MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
  539. MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
  540. >;
  541. };
  542. pinctrl_uart5: uart5grp {
  543. fsl,pins = <
  544. MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79
  545. MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79
  546. MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79
  547. MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79
  548. >;
  549. };
  550. pinctrl_uart6: uart6grp {
  551. fsl,pins = <
  552. MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
  553. MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
  554. MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
  555. MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
  556. >;
  557. };
  558. pinctrl_usdhc1: usdhc1grp {
  559. fsl,pins = <
  560. MX7D_PAD_SD1_CMD__SD1_CMD 0x59
  561. MX7D_PAD_SD1_CLK__SD1_CLK 0x19
  562. MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
  563. MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
  564. MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
  565. MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
  566. MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */
  567. MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */
  568. MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */
  569. >;
  570. };
  571. pinctrl_usdhc2: usdhc2grp {
  572. fsl,pins = <
  573. MX7D_PAD_SD2_CMD__SD2_CMD 0x59
  574. MX7D_PAD_SD2_CLK__SD2_CLK 0x19
  575. MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
  576. MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
  577. MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
  578. MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
  579. >;
  580. };
  581. pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
  582. fsl,pins = <
  583. MX7D_PAD_SD2_CMD__SD2_CMD 0x5a
  584. MX7D_PAD_SD2_CLK__SD2_CLK 0x1a
  585. MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
  586. MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
  587. MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
  588. MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
  589. >;
  590. };
  591. pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
  592. fsl,pins = <
  593. MX7D_PAD_SD2_CMD__SD2_CMD 0x5b
  594. MX7D_PAD_SD2_CLK__SD2_CLK 0x1b
  595. MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
  596. MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
  597. MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
  598. MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
  599. >;
  600. };
  601. pinctrl_usdhc3: usdhc3grp {
  602. fsl,pins = <
  603. MX7D_PAD_SD3_CMD__SD3_CMD 0x59
  604. MX7D_PAD_SD3_CLK__SD3_CLK 0x19
  605. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
  606. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
  607. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
  608. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
  609. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
  610. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
  611. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
  612. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
  613. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
  614. >;
  615. };
  616. pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
  617. fsl,pins = <
  618. MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
  619. MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
  620. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
  621. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
  622. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
  623. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
  624. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
  625. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
  626. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
  627. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
  628. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
  629. >;
  630. };
  631. pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
  632. fsl,pins = <
  633. MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
  634. MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
  635. MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
  636. MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
  637. MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
  638. MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
  639. MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
  640. MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
  641. MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
  642. MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
  643. MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
  644. >;
  645. };
  646. };
  647. };
  648. &pwm1 {
  649. pinctrl-names = "default";
  650. pinctrl-0 = <&pinctrl_pwm1>;
  651. status = "okay";
  652. };
  653. &iomuxc_lpsr {
  654. pinctrl_wdog: wdoggrp {
  655. fsl,pins = <
  656. MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
  657. >;
  658. };
  659. pinctrl_pwm1: pwm1grp {
  660. fsl,pins = <
  661. MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30
  662. >;
  663. };
  664. pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
  665. fsl,pins = <
  666. MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
  667. >;
  668. };
  669. };