xilinx_wwdt.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xilinx window watchdog timer driver.
  4. *
  5. * Author(s): Michal Simek <michal.simek@xilinx.com>
  6. * Ashok Reddy Soma <ashokred@xilinx.com>
  7. *
  8. * Copyright (c) 2020, Xilinx Inc.
  9. */
  10. #include <clk.h>
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <wdt.h>
  15. #include <linux/compat.h>
  16. #include <linux/io.h>
  17. /* Refresh Register Masks */
  18. #define XWT_WWREF_GWRR_MASK BIT(0) /* Refresh and start new period */
  19. /* Generic Control/Status Register Masks */
  20. #define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */
  21. /* Register offsets for the Wdt device */
  22. #define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */
  23. #define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */
  24. #define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */
  25. #define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */
  26. #define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */
  27. #define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */
  28. struct xlnx_wwdt_priv {
  29. bool enable_once;
  30. struct regmap *regs;
  31. struct clk clk;
  32. };
  33. struct xlnx_wwdt_plat {
  34. bool enable_once;
  35. };
  36. static int xlnx_wwdt_reset(struct udevice *dev)
  37. {
  38. struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
  39. regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK);
  40. return 0;
  41. }
  42. static int xlnx_wwdt_stop(struct udevice *dev)
  43. {
  44. u32 csr;
  45. struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
  46. if (wdt->enable_once) {
  47. dev_warn(dev, "Can't stop Xilinx watchdog.\n");
  48. return -EBUSY;
  49. }
  50. /* Disable the generic watchdog timer */
  51. regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
  52. csr &= ~(XWT_WWCSR_GWEN_MASK);
  53. regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
  54. clk_disable(&wdt->clk);
  55. dev_dbg(dev, "Watchdog disabled!\n");
  56. return 0;
  57. }
  58. static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
  59. {
  60. int ret;
  61. u32 csr;
  62. u64 count;
  63. unsigned long clock_f;
  64. struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
  65. clock_f = clk_get_rate(&wdt->clk);
  66. if (IS_ERR_VALUE(clock_f)) {
  67. dev_err(dev, "failed to get rate\n");
  68. return clock_f;
  69. }
  70. dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
  71. /* Calculate timeout count */
  72. count = timeout * clock_f;
  73. /* clk_enable will return -ENOSYS when it is not implemented */
  74. ret = clk_enable(&wdt->clk);
  75. if (ret && ret != -ENOSYS) {
  76. dev_err(dev, "failed to enable clock\n");
  77. return ret;
  78. }
  79. /*
  80. * Timeout count is half as there are two windows
  81. * first window overflow is ignored (interrupt),
  82. * reset is only generated at second window overflow
  83. */
  84. count = count >> 1;
  85. /* Disable the generic watchdog timer */
  86. regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
  87. csr &= ~(XWT_WWCSR_GWEN_MASK);
  88. regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
  89. /* Set compare and offset registers for generic watchdog timeout */
  90. regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count);
  91. regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0);
  92. regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count);
  93. /* Enable the generic watchdog timer */
  94. regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
  95. csr |= (XWT_WWCSR_GWEN_MASK);
  96. regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
  97. return 0;
  98. }
  99. static int xlnx_wwdt_probe(struct udevice *dev)
  100. {
  101. int ret;
  102. struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
  103. struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
  104. dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev_seq(dev));
  105. ret = regmap_init_mem(dev_ofnode(dev), &wdt->regs);
  106. if (ret) {
  107. dev_dbg(dev, "failed to get regbase of wwdt\n");
  108. return ret;
  109. }
  110. wdt->enable_once = plat->enable_once;
  111. ret = clk_get_by_index(dev, 0, &wdt->clk);
  112. if (ret < 0)
  113. dev_err(dev, "failed to get clock\n");
  114. return ret;
  115. }
  116. static int xlnx_wwdt_of_to_plat(struct udevice *dev)
  117. {
  118. struct xlnx_wwdt_plat *plat = dev_get_plat(dev);
  119. plat->enable_once = dev_read_u32_default(dev, "xlnx,wdt-enable-once",
  120. 0);
  121. dev_dbg(dev, "wdt-enable-once %d\n", plat->enable_once);
  122. return 0;
  123. }
  124. static const struct wdt_ops xlnx_wwdt_ops = {
  125. .start = xlnx_wwdt_start,
  126. .reset = xlnx_wwdt_reset,
  127. .stop = xlnx_wwdt_stop,
  128. };
  129. static const struct udevice_id xlnx_wwdt_ids[] = {
  130. { .compatible = "xlnx,versal-wwdt-1.0", },
  131. {},
  132. };
  133. U_BOOT_DRIVER(xlnx_wwdt) = {
  134. .name = "xlnx_wwdt",
  135. .id = UCLASS_WDT,
  136. .of_match = xlnx_wwdt_ids,
  137. .probe = xlnx_wwdt_probe,
  138. .priv_auto = sizeof(struct xlnx_wwdt_priv),
  139. .plat_auto = sizeof(struct xlnx_wwdt_plat),
  140. .of_to_plat = xlnx_wwdt_of_to_plat,
  141. .ops = &xlnx_wwdt_ops,
  142. };