sp805_wdt.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Watchdog driver for SP805 on some Layerscape SoC
  4. *
  5. * Copyright 2019 NXP
  6. */
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm/device.h>
  12. #include <dm/fdtaddr.h>
  13. #include <dm/read.h>
  14. #include <linux/bitops.h>
  15. #include <watchdog.h>
  16. #include <wdt.h>
  17. #include <linux/err.h>
  18. #define WDTLOAD 0x000
  19. #define WDTCONTROL 0x008
  20. #define WDTINTCLR 0x00C
  21. #define WDTLOCK 0xC00
  22. #define TIME_OUT_MIN_MSECS 1
  23. #define TIME_OUT_MAX_MSECS 120000
  24. #define SYS_FSL_WDT_CLK_DIV 16
  25. #define INT_ENABLE BIT(0)
  26. #define RESET_ENABLE BIT(1)
  27. #define DISABLE 0
  28. #define UNLOCK 0x1ACCE551
  29. #define LOCK 0x00000001
  30. #define INT_MASK BIT(0)
  31. DECLARE_GLOBAL_DATA_PTR;
  32. struct sp805_wdt_priv {
  33. void __iomem *reg;
  34. unsigned long clk_rate;
  35. };
  36. static int sp805_wdt_reset(struct udevice *dev)
  37. {
  38. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  39. writel(UNLOCK, priv->reg + WDTLOCK);
  40. writel(INT_MASK, priv->reg + WDTINTCLR);
  41. writel(LOCK, priv->reg + WDTLOCK);
  42. readl(priv->reg + WDTLOCK);
  43. return 0;
  44. }
  45. static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  46. {
  47. u32 load_value;
  48. u32 load_time;
  49. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  50. load_time = (u32)timeout;
  51. if (timeout < TIME_OUT_MIN_MSECS)
  52. load_time = TIME_OUT_MIN_MSECS;
  53. else if (timeout > TIME_OUT_MAX_MSECS)
  54. load_time = TIME_OUT_MAX_MSECS;
  55. /* sp805 runs counter with given value twice, so when the max timeout is
  56. * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
  57. * not overflow.
  58. */
  59. if (gd->bus_clk) {
  60. load_value = (gd->bus_clk) /
  61. (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
  62. } else {
  63. /* platform provide clk */
  64. load_value = (timeout / 2) * (priv->clk_rate / 1000);
  65. }
  66. writel(UNLOCK, priv->reg + WDTLOCK);
  67. writel(load_value, priv->reg + WDTLOAD);
  68. writel(INT_MASK, priv->reg + WDTINTCLR);
  69. writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
  70. writel(LOCK, priv->reg + WDTLOCK);
  71. readl(priv->reg + WDTLOCK);
  72. return 0;
  73. }
  74. static int sp805_wdt_stop(struct udevice *dev)
  75. {
  76. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  77. writel(UNLOCK, priv->reg + WDTLOCK);
  78. writel(DISABLE, priv->reg + WDTCONTROL);
  79. writel(LOCK, priv->reg + WDTLOCK);
  80. readl(priv->reg + WDTLOCK);
  81. return 0;
  82. }
  83. static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
  84. {
  85. sp805_wdt_start(dev, 0, flags);
  86. return 0;
  87. }
  88. static int sp805_wdt_probe(struct udevice *dev)
  89. {
  90. debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev_seq(dev));
  91. return 0;
  92. }
  93. static int sp805_wdt_of_to_plat(struct udevice *dev)
  94. {
  95. struct sp805_wdt_priv *priv = dev_get_priv(dev);
  96. struct clk clk;
  97. priv->reg = (void __iomem *)dev_read_addr(dev);
  98. if (IS_ERR(priv->reg))
  99. return PTR_ERR(priv->reg);
  100. if (!clk_get_by_index(dev, 0, &clk))
  101. priv->clk_rate = clk_get_rate(&clk);
  102. return 0;
  103. }
  104. static const struct wdt_ops sp805_wdt_ops = {
  105. .start = sp805_wdt_start,
  106. .reset = sp805_wdt_reset,
  107. .stop = sp805_wdt_stop,
  108. .expire_now = sp805_wdt_expire_now,
  109. };
  110. static const struct udevice_id sp805_wdt_ids[] = {
  111. { .compatible = "arm,sp805-wdt" },
  112. {}
  113. };
  114. U_BOOT_DRIVER(sp805_wdt) = {
  115. .name = "sp805_wdt",
  116. .id = UCLASS_WDT,
  117. .of_match = sp805_wdt_ids,
  118. .probe = sp805_wdt_probe,
  119. .priv_auto = sizeof(struct sp805_wdt_priv),
  120. .of_to_plat = sp805_wdt_of_to_plat,
  121. .ops = &sp805_wdt_ops,
  122. };