orion_wdt.c 4.2 KB

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  1. /*
  2. * drivers/watchdog/orion_wdt.c
  3. *
  4. * Watchdog driver for Orion/Kirkwood processors
  5. *
  6. * Authors: Tomas Hlavacek <tmshlvck@gmail.com>
  7. * Sylver Bruneau <sylver.bruneau@googlemail.com>
  8. * Marek Behun <marek.behun@nic.cz>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. */
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <clk.h>
  17. #include <log.h>
  18. #include <wdt.h>
  19. #include <linux/bitops.h>
  20. #include <linux/kernel.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/cpu.h>
  23. #include <asm/arch/soc.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. struct orion_wdt_priv {
  26. void __iomem *reg;
  27. int wdt_counter_offset;
  28. void __iomem *rstout;
  29. void __iomem *rstout_mask;
  30. u32 timeout;
  31. unsigned long clk_rate;
  32. struct clk clk;
  33. };
  34. #define RSTOUT_ENABLE_BIT BIT(8)
  35. #define RSTOUT_MASK_BIT BIT(10)
  36. #define WDT_ENABLE_BIT BIT(8)
  37. #define TIMER_CTRL 0x0000
  38. #define TIMER_A370_STATUS 0x04
  39. #define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
  40. #define WDT_A370_EXPIRED BIT(31)
  41. static int orion_wdt_reset(struct udevice *dev)
  42. {
  43. struct orion_wdt_priv *priv = dev_get_priv(dev);
  44. /* Reload watchdog duration */
  45. writel(priv->clk_rate * priv->timeout,
  46. priv->reg + priv->wdt_counter_offset);
  47. return 0;
  48. }
  49. static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
  50. {
  51. struct orion_wdt_priv *priv = dev_get_priv(dev);
  52. u32 reg;
  53. priv->timeout = DIV_ROUND_UP(timeout_ms, 1000);
  54. /* Enable the fixed watchdog clock input */
  55. reg = readl(priv->reg + TIMER_CTRL);
  56. reg |= WDT_AXP_FIXED_ENABLE_BIT;
  57. writel(reg, priv->reg + TIMER_CTRL);
  58. /* Set watchdog duration */
  59. writel(priv->clk_rate * priv->timeout,
  60. priv->reg + priv->wdt_counter_offset);
  61. /* Clear the watchdog expiration bit */
  62. reg = readl(priv->reg + TIMER_A370_STATUS);
  63. reg &= ~WDT_A370_EXPIRED;
  64. writel(reg, priv->reg + TIMER_A370_STATUS);
  65. /* Enable watchdog timer */
  66. reg = readl(priv->reg + TIMER_CTRL);
  67. reg |= WDT_ENABLE_BIT;
  68. writel(reg, priv->reg + TIMER_CTRL);
  69. /* Enable reset on watchdog */
  70. reg = readl(priv->rstout);
  71. reg |= RSTOUT_ENABLE_BIT;
  72. writel(reg, priv->rstout);
  73. reg = readl(priv->rstout_mask);
  74. reg &= ~RSTOUT_MASK_BIT;
  75. writel(reg, priv->rstout_mask);
  76. return 0;
  77. }
  78. static int orion_wdt_stop(struct udevice *dev)
  79. {
  80. struct orion_wdt_priv *priv = dev_get_priv(dev);
  81. u32 reg;
  82. /* Disable reset on watchdog */
  83. reg = readl(priv->rstout_mask);
  84. reg |= RSTOUT_MASK_BIT;
  85. writel(reg, priv->rstout_mask);
  86. reg = readl(priv->rstout);
  87. reg &= ~RSTOUT_ENABLE_BIT;
  88. writel(reg, priv->rstout);
  89. /* Disable watchdog timer */
  90. reg = readl(priv->reg + TIMER_CTRL);
  91. reg &= ~WDT_ENABLE_BIT;
  92. writel(reg, priv->reg + TIMER_CTRL);
  93. return 0;
  94. }
  95. static inline bool save_reg_from_ofdata(struct udevice *dev, int index,
  96. void __iomem **reg, int *offset)
  97. {
  98. fdt_addr_t addr;
  99. fdt_size_t off;
  100. addr = devfdt_get_addr_size_index(dev, index, &off);
  101. if (addr == FDT_ADDR_T_NONE)
  102. return false;
  103. *reg = (void __iomem *) addr;
  104. if (offset)
  105. *offset = off;
  106. return true;
  107. }
  108. static int orion_wdt_of_to_plat(struct udevice *dev)
  109. {
  110. struct orion_wdt_priv *priv = dev_get_priv(dev);
  111. if (!save_reg_from_ofdata(dev, 0, &priv->reg,
  112. &priv->wdt_counter_offset))
  113. goto err;
  114. if (!save_reg_from_ofdata(dev, 1, &priv->rstout, NULL))
  115. goto err;
  116. if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL))
  117. goto err;
  118. return 0;
  119. err:
  120. debug("%s: Could not determine Orion wdt IO addresses\n", __func__);
  121. return -ENXIO;
  122. }
  123. static int orion_wdt_probe(struct udevice *dev)
  124. {
  125. struct orion_wdt_priv *priv = dev_get_priv(dev);
  126. int ret;
  127. debug("%s: Probing wdt%u\n", __func__, dev_seq(dev));
  128. orion_wdt_stop(dev);
  129. ret = clk_get_by_name(dev, "fixed", &priv->clk);
  130. if (!ret)
  131. priv->clk_rate = clk_get_rate(&priv->clk);
  132. else
  133. priv->clk_rate = 25000000;
  134. return 0;
  135. }
  136. static const struct wdt_ops orion_wdt_ops = {
  137. .start = orion_wdt_start,
  138. .reset = orion_wdt_reset,
  139. .stop = orion_wdt_stop,
  140. };
  141. static const struct udevice_id orion_wdt_ids[] = {
  142. { .compatible = "marvell,armada-380-wdt" },
  143. {}
  144. };
  145. U_BOOT_DRIVER(orion_wdt) = {
  146. .name = "orion_wdt",
  147. .id = UCLASS_WDT,
  148. .of_match = orion_wdt_ids,
  149. .probe = orion_wdt_probe,
  150. .priv_auto = sizeof(struct orion_wdt_priv),
  151. .of_to_plat = orion_wdt_of_to_plat,
  152. .ops = &orion_wdt_ops,
  153. };