ehci-vf.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Sanchayan Maity <sanchayan.maity@toradex.com>
  4. * Copyright (C) 2015 Toradex AG
  5. *
  6. * Based on ehci-mx6 driver
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <usb.h>
  12. #include <errno.h>
  13. #include <linux/compiler.h>
  14. #include <asm/io.h>
  15. #include <asm-generic/gpio.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/regs-usbphy.h>
  21. #include <linux/delay.h>
  22. #include <usb/ehci-ci.h>
  23. #include <linux/libfdt.h>
  24. #include <fdtdec.h>
  25. #include "ehci.h"
  26. #define USB_NC_REG_OFFSET 0x00000800
  27. #define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6)
  28. #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
  29. #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
  30. /* USBCMD */
  31. #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
  32. #define UCMD_RESET (1 << 1) /* controller reset */
  33. DECLARE_GLOBAL_DATA_PTR;
  34. static const unsigned phy_bases[] = {
  35. USB_PHY0_BASE_ADDR,
  36. USB_PHY1_BASE_ADDR,
  37. };
  38. static const unsigned nc_reg_bases[] = {
  39. USBC0_BASE_ADDR,
  40. USBC1_BASE_ADDR,
  41. };
  42. static void usb_internal_phy_clock_gate(int index)
  43. {
  44. void __iomem *phy_reg;
  45. phy_reg = (void __iomem *)phy_bases[index];
  46. clrbits_le32(phy_reg + USBPHY_CTRL, USBPHY_CTRL_CLKGATE);
  47. }
  48. static void usb_power_config(int index)
  49. {
  50. struct anadig_reg __iomem *anadig =
  51. (struct anadig_reg __iomem *)ANADIG_BASE_ADDR;
  52. void __iomem *pll_ctrl;
  53. switch (index) {
  54. case 0:
  55. pll_ctrl = &anadig->pll3_ctrl;
  56. clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS);
  57. setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE
  58. | ANADIG_PLL3_CTRL_POWERDOWN
  59. | ANADIG_PLL_CTRL_EN_USB_CLKS);
  60. break;
  61. case 1:
  62. pll_ctrl = &anadig->pll7_ctrl;
  63. clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS);
  64. setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE
  65. | ANADIG_PLL7_CTRL_POWERDOWN
  66. | ANADIG_PLL_CTRL_EN_USB_CLKS);
  67. break;
  68. default:
  69. return;
  70. }
  71. }
  72. static void usb_phy_enable(int index, struct usb_ehci *ehci)
  73. {
  74. void __iomem *phy_reg;
  75. void __iomem *phy_ctrl;
  76. void __iomem *usb_cmd;
  77. phy_reg = (void __iomem *)phy_bases[index];
  78. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  79. usb_cmd = (void __iomem *)&ehci->usbcmd;
  80. /* Stop then Reset */
  81. clrbits_le32(usb_cmd, UCMD_RUN_STOP);
  82. while (readl(usb_cmd) & UCMD_RUN_STOP)
  83. ;
  84. setbits_le32(usb_cmd, UCMD_RESET);
  85. while (readl(usb_cmd) & UCMD_RESET)
  86. ;
  87. /* Reset USBPHY module */
  88. setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
  89. udelay(10);
  90. /* Remove CLKGATE and SFTRST */
  91. clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
  92. udelay(10);
  93. /* Power up the PHY */
  94. writel(0, phy_reg + USBPHY_PWD);
  95. /* Enable FS/LS device */
  96. setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
  97. USBPHY_CTRL_ENUTMILEVEL3);
  98. }
  99. static void usb_oc_config(int index)
  100. {
  101. void __iomem *ctrl;
  102. ctrl = (void __iomem *)(nc_reg_bases[index] + USB_NC_REG_OFFSET);
  103. setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  104. setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
  105. }
  106. int __weak board_usb_phy_mode(int port)
  107. {
  108. return 0;
  109. }
  110. int __weak board_ehci_hcd_init(int port)
  111. {
  112. return 0;
  113. }
  114. int ehci_vf_common_init(struct usb_ehci *ehci, int index)
  115. {
  116. int ret;
  117. /* Do board specific initialisation */
  118. ret = board_ehci_hcd_init(index);
  119. if (ret)
  120. return ret;
  121. usb_power_config(index);
  122. usb_oc_config(index);
  123. usb_internal_phy_clock_gate(index);
  124. usb_phy_enable(index, ehci);
  125. return 0;
  126. }
  127. #if !CONFIG_IS_ENABLED(DM_USB)
  128. int ehci_hcd_init(int index, enum usb_init_type init,
  129. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  130. {
  131. struct usb_ehci *ehci;
  132. enum usb_init_type type;
  133. int ret;
  134. if (index >= ARRAY_SIZE(nc_reg_bases))
  135. return -EINVAL;
  136. ehci = (struct usb_ehci *)nc_reg_bases[index];
  137. ret = ehci_vf_common_init(index);
  138. if (ret)
  139. return ret;
  140. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  141. *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
  142. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  143. type = board_usb_phy_mode(index);
  144. if (type != init)
  145. return -ENODEV;
  146. if (init == USB_INIT_DEVICE) {
  147. setbits_le32(&ehci->usbmode, CM_DEVICE);
  148. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  149. setbits_le32(&ehci->portsc, USB_EN);
  150. } else if (init == USB_INIT_HOST) {
  151. setbits_le32(&ehci->usbmode, CM_HOST);
  152. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  153. setbits_le32(&ehci->portsc, USB_EN);
  154. }
  155. return 0;
  156. }
  157. int ehci_hcd_stop(int index)
  158. {
  159. return 0;
  160. }
  161. #else
  162. /* Possible port types (dual role mode) */
  163. enum dr_mode {
  164. DR_MODE_NONE = 0,
  165. DR_MODE_HOST, /* supports host operation */
  166. DR_MODE_DEVICE, /* supports device operation */
  167. DR_MODE_OTG, /* supports both */
  168. };
  169. struct ehci_vf_priv_data {
  170. struct ehci_ctrl ctrl;
  171. struct usb_ehci *ehci;
  172. struct gpio_desc cdet_gpio;
  173. enum usb_init_type init_type;
  174. enum dr_mode dr_mode;
  175. u32 portnr;
  176. };
  177. static int vf_usb_of_to_plat(struct udevice *dev)
  178. {
  179. struct ehci_vf_priv_data *priv = dev_get_priv(dev);
  180. const void *dt_blob = gd->fdt_blob;
  181. int node = dev_of_offset(dev);
  182. const char *mode;
  183. priv->portnr = dev_seq(dev);
  184. priv->ehci = dev_read_addr_ptr(dev);
  185. mode = fdt_getprop(dt_blob, node, "dr_mode", NULL);
  186. if (mode) {
  187. if (0 == strcmp(mode, "host")) {
  188. priv->dr_mode = DR_MODE_HOST;
  189. priv->init_type = USB_INIT_HOST;
  190. } else if (0 == strcmp(mode, "peripheral")) {
  191. priv->dr_mode = DR_MODE_DEVICE;
  192. priv->init_type = USB_INIT_DEVICE;
  193. } else if (0 == strcmp(mode, "otg")) {
  194. priv->dr_mode = DR_MODE_OTG;
  195. /*
  196. * We set init_type to device by default when OTG
  197. * mode is requested. If a valid gpio is provided
  198. * we will switch the init_type based on the state
  199. * of the gpio pin.
  200. */
  201. priv->init_type = USB_INIT_DEVICE;
  202. } else {
  203. debug("%s: Cannot decode dr_mode '%s'\n",
  204. __func__, mode);
  205. return -EINVAL;
  206. }
  207. } else {
  208. priv->dr_mode = DR_MODE_HOST;
  209. priv->init_type = USB_INIT_HOST;
  210. }
  211. if (priv->dr_mode == DR_MODE_OTG) {
  212. gpio_request_by_name_nodev(offset_to_ofnode(node),
  213. "fsl,cdet-gpio", 0, &priv->cdet_gpio,
  214. GPIOD_IS_IN);
  215. if (dm_gpio_is_valid(&priv->cdet_gpio)) {
  216. if (dm_gpio_get_value(&priv->cdet_gpio))
  217. priv->init_type = USB_INIT_DEVICE;
  218. else
  219. priv->init_type = USB_INIT_HOST;
  220. }
  221. }
  222. return 0;
  223. }
  224. static int vf_init_after_reset(struct ehci_ctrl *dev)
  225. {
  226. struct ehci_vf_priv_data *priv = dev->priv;
  227. enum usb_init_type type = priv->init_type;
  228. struct usb_ehci *ehci = priv->ehci;
  229. int ret;
  230. ret = ehci_vf_common_init(priv->ehci, priv->portnr);
  231. if (ret)
  232. return ret;
  233. if (type == USB_INIT_DEVICE)
  234. return 0;
  235. setbits_le32(&ehci->usbmode, CM_HOST);
  236. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  237. setbits_le32(&ehci->portsc, USB_EN);
  238. mdelay(10);
  239. return 0;
  240. }
  241. static const struct ehci_ops vf_ehci_ops = {
  242. .init_after_reset = vf_init_after_reset
  243. };
  244. static int vf_usb_bind(struct udevice *dev)
  245. {
  246. static int num_controllers;
  247. /*
  248. * Without this hack, if we return ENODEV for USB Controller 0, on
  249. * probe for the next controller, USB Controller 1 will be given a
  250. * sequence number of 0. This conflicts with our requirement of
  251. * sequence numbers while initialising the peripherals.
  252. */
  253. dev->req_seq = num_controllers;
  254. num_controllers++;
  255. return 0;
  256. }
  257. static int ehci_usb_probe(struct udevice *dev)
  258. {
  259. struct usb_plat *plat = dev_get_plat(dev);
  260. struct ehci_vf_priv_data *priv = dev_get_priv(dev);
  261. struct usb_ehci *ehci = priv->ehci;
  262. struct ehci_hccr *hccr;
  263. struct ehci_hcor *hcor;
  264. int ret;
  265. ret = ehci_vf_common_init(ehci, priv->portnr);
  266. if (ret)
  267. return ret;
  268. if (priv->init_type != plat->init_type)
  269. return -ENODEV;
  270. if (priv->init_type == USB_INIT_HOST) {
  271. setbits_le32(&ehci->usbmode, CM_HOST);
  272. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  273. setbits_le32(&ehci->portsc, USB_EN);
  274. }
  275. mdelay(10);
  276. hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  277. hcor = (struct ehci_hcor *)((uint32_t)hccr +
  278. HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  279. return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, priv->init_type);
  280. }
  281. static const struct udevice_id vf_usb_ids[] = {
  282. { .compatible = "fsl,vf610-usb" },
  283. { }
  284. };
  285. U_BOOT_DRIVER(usb_ehci) = {
  286. .name = "ehci_vf",
  287. .id = UCLASS_USB,
  288. .of_match = vf_usb_ids,
  289. .bind = vf_usb_bind,
  290. .probe = ehci_usb_probe,
  291. .remove = ehci_deregister,
  292. .ops = &ehci_usb_ops,
  293. .of_to_plat = vf_usb_of_to_plat,
  294. .plat_auto = sizeof(struct usb_plat),
  295. .priv_auto = sizeof(struct ehci_vf_priv_data),
  296. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  297. };
  298. #endif