ehci-omap.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
  4. * (C) Copyright 2004-2008
  5. * Texas Instruments, <www.ti.com>
  6. *
  7. * Derived from Beagle Board code by
  8. * Sunil Kumar <sunilsaini05@gmail.com>
  9. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  10. *
  11. */
  12. #include <common.h>
  13. #include <log.h>
  14. #include <usb.h>
  15. #include <linux/delay.h>
  16. #include <usb/ulpi.h>
  17. #include <errno.h>
  18. #include <asm/io.h>
  19. #include <asm/gpio.h>
  20. #include <asm/arch/ehci.h>
  21. #include <asm/ehci-omap.h>
  22. #include <dm.h>
  23. #include <dm/device-internal.h>
  24. #include <dm/lists.h>
  25. #include <power/regulator.h>
  26. #include "ehci.h"
  27. static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
  28. static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
  29. static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
  30. static int omap_uhh_reset(void)
  31. {
  32. int timeout = 0;
  33. u32 rev;
  34. rev = readl(&uhh->rev);
  35. /* Soft RESET */
  36. writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
  37. switch (rev) {
  38. case OMAP_USBHS_REV1:
  39. /* Wait for soft RESET to complete */
  40. while (!(readl(&uhh->syss) & 0x1)) {
  41. if (timeout > 100) {
  42. printf("%s: RESET timeout\n", __func__);
  43. return -1;
  44. }
  45. udelay(10);
  46. timeout++;
  47. }
  48. /* Set No-Idle, No-Standby */
  49. writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
  50. break;
  51. default: /* Rev. 2 onwards */
  52. udelay(2); /* Need to wait before accessing SYSCONFIG back */
  53. /* Wait for soft RESET to complete */
  54. while ((readl(&uhh->sysc) & 0x1)) {
  55. if (timeout > 100) {
  56. printf("%s: RESET timeout\n", __func__);
  57. return -1;
  58. }
  59. udelay(10);
  60. timeout++;
  61. }
  62. writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
  63. break;
  64. }
  65. return 0;
  66. }
  67. static int omap_ehci_tll_reset(void)
  68. {
  69. unsigned long init = get_timer(0);
  70. /* perform TLL soft reset, and wait until reset is complete */
  71. writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
  72. /* Wait for TLL reset to complete */
  73. while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
  74. if (get_timer(init) > CONFIG_SYS_HZ) {
  75. debug("OMAP EHCI error: timeout resetting TLL\n");
  76. return -EL3RST;
  77. }
  78. return 0;
  79. }
  80. static void omap_usbhs_hsic_init(int port)
  81. {
  82. unsigned int reg;
  83. /* Enable channels now */
  84. reg = readl(&usbtll->channel_conf + port);
  85. setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
  86. | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
  87. | OMAP_TLL_CHANNEL_CONF_DRVVBUS
  88. | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
  89. | OMAP_TLL_CHANNEL_CONF_CHANEN));
  90. writel(reg, &usbtll->channel_conf + port);
  91. }
  92. #ifdef CONFIG_USB_ULPI
  93. static void omap_ehci_soft_phy_reset(int port)
  94. {
  95. struct ulpi_viewport ulpi_vp;
  96. ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
  97. ulpi_vp.port_num = port;
  98. ulpi_reset(&ulpi_vp);
  99. }
  100. #else
  101. static void omap_ehci_soft_phy_reset(int port)
  102. {
  103. return;
  104. }
  105. #endif
  106. #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
  107. defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
  108. defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
  109. /* controls PHY(s) reset signal(s) */
  110. static inline void omap_ehci_phy_reset(int on, int delay)
  111. {
  112. /*
  113. * Refer ISSUE1:
  114. * Hold the PHY in RESET for enough time till
  115. * PHY is settled and ready
  116. */
  117. if (delay && !on)
  118. udelay(delay);
  119. #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
  120. gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
  121. gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
  122. #endif
  123. #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
  124. gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
  125. gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
  126. #endif
  127. #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
  128. gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
  129. gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
  130. #endif
  131. /* Hold the PHY in RESET for enough time till DIR is high */
  132. /* Refer: ISSUE1 */
  133. if (delay && on)
  134. udelay(delay);
  135. }
  136. #else
  137. #define omap_ehci_phy_reset(on, delay) do {} while (0)
  138. #endif
  139. /* Reset is needed otherwise the kernel-driver will throw an error. */
  140. int omap_ehci_hcd_stop(void)
  141. {
  142. debug("Resetting OMAP EHCI\n");
  143. omap_ehci_phy_reset(1, 0);
  144. if (omap_uhh_reset() < 0)
  145. return -1;
  146. if (omap_ehci_tll_reset() < 0)
  147. return -1;
  148. return 0;
  149. }
  150. /*
  151. * Initialize the OMAP EHCI controller and PHY.
  152. * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
  153. * See there for additional Copyrights.
  154. */
  155. #if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)
  156. int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
  157. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  158. {
  159. *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
  160. *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
  161. #else
  162. int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata)
  163. {
  164. #endif
  165. int ret;
  166. unsigned int i, reg = 0, rev = 0;
  167. debug("Initializing OMAP EHCI\n");
  168. ret = board_usb_init(index, USB_INIT_HOST);
  169. if (ret < 0)
  170. return ret;
  171. /* Put the PHY in RESET */
  172. omap_ehci_phy_reset(1, 10);
  173. ret = omap_uhh_reset();
  174. if (ret < 0)
  175. return ret;
  176. ret = omap_ehci_tll_reset();
  177. if (ret)
  178. return ret;
  179. writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
  180. OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
  181. OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
  182. /* Put UHH in NoIdle/NoStandby mode */
  183. writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
  184. /* setup ULPI bypass and burst configurations */
  185. clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
  186. (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
  187. OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
  188. OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
  189. rev = readl(&uhh->rev);
  190. if (rev == OMAP_USBHS_REV1) {
  191. if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
  192. clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
  193. else
  194. setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
  195. if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
  196. clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
  197. else
  198. setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
  199. if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
  200. clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
  201. else
  202. setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
  203. } else if (rev == OMAP_USBHS_REV2) {
  204. clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
  205. OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
  206. /* Clear port mode fields for PHY mode */
  207. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
  208. setbits_le32(&reg, OMAP_P1_MODE_HSIC);
  209. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
  210. setbits_le32(&reg, OMAP_P2_MODE_HSIC);
  211. } else if (rev == OMAP_USBHS_REV2_1) {
  212. clrsetbits_le32(&reg,
  213. (OMAP_P1_MODE_CLEAR |
  214. OMAP_P2_MODE_CLEAR |
  215. OMAP_P3_MODE_CLEAR),
  216. OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
  217. /* Clear port mode fields for PHY mode */
  218. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
  219. setbits_le32(&reg, OMAP_P1_MODE_HSIC);
  220. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
  221. setbits_le32(&reg, OMAP_P2_MODE_HSIC);
  222. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
  223. setbits_le32(&reg, OMAP_P3_MODE_HSIC);
  224. }
  225. debug("OMAP UHH_REVISION 0x%x\n", rev);
  226. writel(reg, &uhh->hostconfig);
  227. for (i = 0; i < OMAP_HS_USB_PORTS; i++)
  228. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
  229. omap_usbhs_hsic_init(i);
  230. omap_ehci_phy_reset(0, 10);
  231. /*
  232. * An undocumented "feature" in the OMAP3 EHCI controller,
  233. * causes suspended ports to be taken out of suspend when
  234. * the USBCMD.Run/Stop bit is cleared (for example when
  235. * we do ehci_bus_suspend).
  236. * This breaks suspend-resume if the root-hub is allowed
  237. * to suspend. Writing 1 to this undocumented register bit
  238. * disables this feature and restores normal behavior.
  239. */
  240. writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
  241. for (i = 0; i < OMAP_HS_USB_PORTS; i++)
  242. if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
  243. omap_ehci_soft_phy_reset(i);
  244. debug("OMAP EHCI init done\n");
  245. return 0;
  246. }
  247. #if CONFIG_IS_ENABLED(DM_USB)
  248. static struct omap_usbhs_board_data usbhs_bdata = {
  249. .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
  250. .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
  251. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  252. };
  253. static void omap_usbhs_set_mode(u8 index, const char *mode)
  254. {
  255. if (!strcmp(mode, "ehci-phy"))
  256. usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_PHY;
  257. else if (!strcmp(mode, "ehci-tll"))
  258. usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_TLL;
  259. else if (!strcmp(mode, "ehci-hsic"))
  260. usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_HSIC;
  261. }
  262. static int omap_usbhs_probe(struct udevice *dev)
  263. {
  264. u8 i;
  265. const char *mode;
  266. char prop[11];
  267. /* Go through each port portX-mode to determing phy mode */
  268. for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
  269. snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
  270. mode = dev_read_string(dev, prop);
  271. /* If the portX-mode exists, set the mode */
  272. if (mode)
  273. omap_usbhs_set_mode(i, mode);
  274. }
  275. return omap_ehci_hcd_init(0, &usbhs_bdata);
  276. }
  277. static const struct udevice_id omap_usbhs_dt_ids[] = {
  278. { .compatible = "ti,usbhs-host" },
  279. { }
  280. };
  281. U_BOOT_DRIVER(usb_omaphs_host) = {
  282. .name = "usbhs-host",
  283. .id = UCLASS_SIMPLE_BUS,
  284. .of_match = omap_usbhs_dt_ids,
  285. .probe = omap_usbhs_probe,
  286. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  287. };
  288. struct ehci_omap_priv_data {
  289. struct ehci_ctrl ctrl;
  290. struct omap_ehci *ehci;
  291. #ifdef CONFIG_DM_REGULATOR
  292. struct udevice *vbus_supply;
  293. #endif
  294. enum usb_init_type init_type;
  295. int portnr;
  296. struct phy phy[OMAP_HS_USB_PORTS];
  297. int nports;
  298. };
  299. static int ehci_usb_of_to_plat(struct udevice *dev)
  300. {
  301. struct usb_plat *plat = dev_get_plat(dev);
  302. plat->init_type = USB_INIT_HOST;
  303. return 0;
  304. }
  305. static int omap_ehci_probe(struct udevice *dev)
  306. {
  307. struct usb_plat *plat = dev_get_plat(dev);
  308. struct ehci_omap_priv_data *priv = dev_get_priv(dev);
  309. struct ehci_hccr *hccr;
  310. struct ehci_hcor *hcor;
  311. priv->ehci = dev_read_addr_ptr(dev);
  312. priv->portnr = dev_seq(dev);
  313. priv->init_type = plat->init_type;
  314. hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
  315. hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;
  316. return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
  317. }
  318. static const struct udevice_id omap_ehci_dt_ids[] = {
  319. { .compatible = "ti,ehci-omap" },
  320. { }
  321. };
  322. U_BOOT_DRIVER(usb_omap_ehci) = {
  323. .name = "omap-ehci",
  324. .id = UCLASS_USB,
  325. .of_match = omap_ehci_dt_ids,
  326. .probe = omap_ehci_probe,
  327. .of_to_plat = ehci_usb_of_to_plat,
  328. .plat_auto = sizeof(struct usb_plat),
  329. .priv_auto = sizeof(struct ehci_omap_priv_data),
  330. .remove = ehci_deregister,
  331. .ops = &ehci_usb_ops,
  332. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  333. };
  334. #endif