ehci-mx5.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  4. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <usb.h>
  9. #include <errno.h>
  10. #include <linux/compiler.h>
  11. #include <linux/delay.h>
  12. #include <usb/ehci-ci.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/clock.h>
  16. #include <dm.h>
  17. #include <power/regulator.h>
  18. #include "ehci.h"
  19. #define MX5_USBOTHER_REGS_OFFSET 0x800
  20. #define MXC_OTG_OFFSET 0
  21. #define MXC_H1_OFFSET 0x200
  22. #define MXC_H2_OFFSET 0x400
  23. #define MXC_H3_OFFSET 0x600
  24. #define MXC_USBCTRL_OFFSET 0
  25. #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
  26. #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
  27. #define MXC_USB_CTRL_1_OFFSET 0x10
  28. #define MXC_USBH2CTRL_OFFSET 0x14
  29. #define MXC_USBH3CTRL_OFFSET 0x18
  30. /* USB_CTRL */
  31. /* OTG wakeup intr enable */
  32. #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
  33. /* OTG power mask */
  34. #define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
  35. /* OTG power pin polarity */
  36. #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
  37. /* Host1 ULPI interrupt enable */
  38. #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
  39. /* HOST1 wakeup intr enable */
  40. #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
  41. /* HOST1 power mask */
  42. #define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
  43. /* HOST1 power pin polarity */
  44. #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
  45. /* USB_PHY_CTRL_FUNC */
  46. /* OTG Polarity of Overcurrent */
  47. #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
  48. /* OTG Disable Overcurrent Event */
  49. #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
  50. /* UH1 Polarity of Overcurrent */
  51. #define MXC_H1_OC_POL_BIT (1 << 6)
  52. /* UH1 Disable Overcurrent Event */
  53. #define MXC_H1_OC_DIS_BIT (1 << 5)
  54. /* OTG Power Pin Polarity */
  55. #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
  56. /* USBH2CTRL */
  57. #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
  58. #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
  59. #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
  60. #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
  61. #define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
  62. #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
  63. /* USBH3CTRL */
  64. #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
  65. #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
  66. #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
  67. #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
  68. #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
  69. /* USB_CTRL_1 */
  70. #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
  71. int mxc_set_usbcontrol(int port, unsigned int flags)
  72. {
  73. unsigned int v;
  74. void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
  75. void __iomem *usbother_base;
  76. int ret = 0;
  77. usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
  78. switch (port) {
  79. case 0: /* OTG port */
  80. if (flags & MXC_EHCI_INTERNAL_PHY) {
  81. v = __raw_readl(usbother_base +
  82. MXC_USB_PHY_CTR_FUNC_OFFSET);
  83. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  84. v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
  85. else
  86. v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
  87. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  88. /* OC/USBPWR is used */
  89. v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
  90. else
  91. /* OC/USBPWR is not used */
  92. v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
  93. #ifdef CONFIG_MX51
  94. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  95. v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
  96. else
  97. v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
  98. #endif
  99. __raw_writel(v, usbother_base +
  100. MXC_USB_PHY_CTR_FUNC_OFFSET);
  101. v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
  102. #ifdef CONFIG_MX51
  103. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  104. v &= ~MXC_OTG_UCTRL_OPM_BIT;
  105. else
  106. v |= MXC_OTG_UCTRL_OPM_BIT;
  107. #endif
  108. #ifdef CONFIG_MX53
  109. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  110. v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
  111. else
  112. v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
  113. #endif
  114. __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
  115. }
  116. break;
  117. case 1: /* Host 1 ULPI */
  118. #ifdef CONFIG_MX51
  119. /* The clock for the USBH1 ULPI port will come externally
  120. from the PHY. */
  121. v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
  122. __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
  123. MXC_USB_CTRL_1_OFFSET);
  124. #endif
  125. v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
  126. #ifdef CONFIG_MX51
  127. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  128. v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
  129. else
  130. v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
  131. #endif
  132. #ifdef CONFIG_MX53
  133. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  134. v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
  135. else
  136. v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
  137. #endif
  138. __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
  139. v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
  140. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  141. v |= MXC_H1_OC_POL_BIT;
  142. else
  143. v &= ~MXC_H1_OC_POL_BIT;
  144. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  145. v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
  146. else
  147. v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
  148. __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
  149. break;
  150. case 2: /* Host 2 ULPI */
  151. v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
  152. #ifdef CONFIG_MX51
  153. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  154. v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
  155. else
  156. v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
  157. #endif
  158. #ifdef CONFIG_MX53
  159. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  160. v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
  161. else
  162. v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
  163. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  164. v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
  165. else
  166. v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
  167. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  168. v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
  169. else
  170. v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
  171. #endif
  172. __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
  173. break;
  174. #ifdef CONFIG_MX53
  175. case 3: /* Host 3 ULPI */
  176. v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
  177. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  178. v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
  179. else
  180. v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
  181. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  182. v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
  183. else
  184. v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
  185. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  186. v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
  187. else
  188. v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
  189. __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
  190. break;
  191. #endif
  192. }
  193. return ret;
  194. }
  195. int __weak board_ehci_hcd_init(int port)
  196. {
  197. return 0;
  198. }
  199. void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
  200. {
  201. }
  202. __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
  203. uint32_t *reg)
  204. {
  205. mdelay(50);
  206. }
  207. #if !CONFIG_IS_ENABLED(DM_USB)
  208. static const struct ehci_ops mx5_ehci_ops = {
  209. .powerup_fixup = mx5_ehci_powerup_fixup,
  210. };
  211. int ehci_hcd_init(int index, enum usb_init_type init,
  212. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  213. {
  214. struct usb_ehci *ehci;
  215. /* The only user for this is efikamx-usb */
  216. ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
  217. set_usboh3_clk();
  218. enable_usboh3_clk(true);
  219. set_usb_phy_clk();
  220. enable_usb_phy1_clk(true);
  221. enable_usb_phy2_clk(true);
  222. mdelay(1);
  223. /* Do board specific initialization */
  224. board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
  225. ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
  226. (0x200 * CONFIG_MXC_USB_PORT));
  227. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  228. *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
  229. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  230. setbits_le32(&ehci->usbmode, CM_HOST);
  231. __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  232. setbits_le32(&ehci->portsc, USB_EN);
  233. mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
  234. mdelay(10);
  235. /* Do board specific post-initialization */
  236. board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
  237. return 0;
  238. }
  239. int ehci_hcd_stop(int index)
  240. {
  241. return 0;
  242. }
  243. #else /* CONFIG_IS_ENABLED(DM_USB) */
  244. struct ehci_mx5_priv_data {
  245. struct ehci_ctrl ctrl;
  246. struct usb_ehci *ehci;
  247. struct udevice *vbus_supply;
  248. enum usb_init_type init_type;
  249. int portnr;
  250. };
  251. static const struct ehci_ops mx5_ehci_ops = {
  252. .powerup_fixup = mx5_ehci_powerup_fixup,
  253. };
  254. static int ehci_usb_of_to_plat(struct udevice *dev)
  255. {
  256. struct usb_plat *plat = dev_get_plat(dev);
  257. const char *mode;
  258. mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
  259. if (mode) {
  260. if (strcmp(mode, "peripheral") == 0)
  261. plat->init_type = USB_INIT_DEVICE;
  262. else if (strcmp(mode, "host") == 0)
  263. plat->init_type = USB_INIT_HOST;
  264. else
  265. return -EINVAL;
  266. }
  267. return 0;
  268. }
  269. static int ehci_usb_probe(struct udevice *dev)
  270. {
  271. struct usb_plat *plat = dev_get_plat(dev);
  272. struct usb_ehci *ehci = dev_read_addr_ptr(dev);
  273. struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
  274. enum usb_init_type type = plat->init_type;
  275. struct ehci_hccr *hccr;
  276. struct ehci_hcor *hcor;
  277. int ret;
  278. set_usboh3_clk();
  279. enable_usboh3_clk(true);
  280. set_usb_phy_clk();
  281. enable_usb_phy1_clk(true);
  282. enable_usb_phy2_clk(true);
  283. mdelay(1);
  284. priv->ehci = ehci;
  285. priv->portnr = dev_seq(dev);
  286. priv->init_type = type;
  287. ret = device_get_supply_regulator(dev, "vbus-supply",
  288. &priv->vbus_supply);
  289. if (ret)
  290. debug("%s: No vbus supply\n", dev->name);
  291. if (!ret && priv->vbus_supply) {
  292. ret = regulator_set_enable(priv->vbus_supply,
  293. (type == USB_INIT_DEVICE) ?
  294. false : true);
  295. if (ret) {
  296. puts("Error enabling VBUS supply\n");
  297. return ret;
  298. }
  299. }
  300. hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  301. hcor = (struct ehci_hcor *)((uint32_t)hccr +
  302. HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
  303. setbits_le32(&ehci->usbmode, CM_HOST);
  304. __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  305. setbits_le32(&ehci->portsc, USB_EN);
  306. mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
  307. mdelay(10);
  308. return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
  309. priv->init_type);
  310. }
  311. static const struct udevice_id mx5_usb_ids[] = {
  312. { .compatible = "fsl,imx53-usb" },
  313. { }
  314. };
  315. U_BOOT_DRIVER(usb_mx5) = {
  316. .name = "ehci_mx5",
  317. .id = UCLASS_USB,
  318. .of_match = mx5_usb_ids,
  319. .of_to_plat = ehci_usb_of_to_plat,
  320. .probe = ehci_usb_probe,
  321. .remove = ehci_deregister,
  322. .ops = &ehci_usb_ops,
  323. .plat_auto = sizeof(struct usb_plat),
  324. .priv_auto = sizeof(struct ehci_mx5_priv_data),
  325. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  326. };
  327. #endif /* !CONFIG_IS_ENABLED(DM_USB) */