zynq_qspi.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Xilinx, Inc.
  4. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  5. *
  6. * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
  7. */
  8. #include <clk.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <dm/device_compat.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <spi.h>
  15. #include <asm/io.h>
  16. #include <linux/bitops.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
  19. #define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
  20. #define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
  21. #define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
  22. #define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
  23. #define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
  24. #define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
  25. #define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
  26. #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
  27. #define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
  28. #define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
  29. #define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
  30. #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
  31. #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
  32. #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
  33. #define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
  34. /* zynq qspi Transmit Data Register */
  35. #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
  36. #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
  37. #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
  38. #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
  39. #define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
  40. #define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
  41. #define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
  42. #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
  43. #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
  44. #define ZYNQ_QSPI_FIFO_DEPTH 63
  45. #define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
  46. /* zynq qspi register set */
  47. struct zynq_qspi_regs {
  48. u32 cr; /* 0x00 */
  49. u32 isr; /* 0x04 */
  50. u32 ier; /* 0x08 */
  51. u32 idr; /* 0x0C */
  52. u32 imr; /* 0x10 */
  53. u32 enr; /* 0x14 */
  54. u32 dr; /* 0x18 */
  55. u32 txd0r; /* 0x1C */
  56. u32 drxr; /* 0x20 */
  57. u32 sicr; /* 0x24 */
  58. u32 txftr; /* 0x28 */
  59. u32 rxftr; /* 0x2C */
  60. u32 gpior; /* 0x30 */
  61. u32 reserved0[19];
  62. u32 txd1r; /* 0x80 */
  63. u32 txd2r; /* 0x84 */
  64. u32 txd3r; /* 0x88 */
  65. u32 reserved1[5];
  66. u32 lqspicfg; /* 0xA0 */
  67. u32 lqspists; /* 0xA4 */
  68. };
  69. /* zynq qspi platform data */
  70. struct zynq_qspi_plat {
  71. struct zynq_qspi_regs *regs;
  72. u32 frequency; /* input frequency */
  73. u32 speed_hz;
  74. };
  75. /* zynq qspi priv */
  76. struct zynq_qspi_priv {
  77. struct zynq_qspi_regs *regs;
  78. u8 cs;
  79. u8 mode;
  80. u8 fifo_depth;
  81. u32 freq; /* required frequency */
  82. const void *tx_buf;
  83. void *rx_buf;
  84. unsigned len;
  85. int bytes_to_transfer;
  86. int bytes_to_receive;
  87. unsigned int is_inst;
  88. unsigned cs_change:1;
  89. };
  90. static int zynq_qspi_of_to_plat(struct udevice *bus)
  91. {
  92. struct zynq_qspi_plat *plat = bus->plat;
  93. const void *blob = gd->fdt_blob;
  94. int node = dev_of_offset(bus);
  95. plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
  96. node, "reg");
  97. return 0;
  98. }
  99. /**
  100. * zynq_qspi_init_hw - Initialize the hardware
  101. * @priv: Pointer to the zynq_qspi_priv structure
  102. *
  103. * The default settings of the QSPI controller's configurable parameters on
  104. * reset are
  105. * - Master mode
  106. * - Baud rate divisor is set to 2
  107. * - Threshold value for TX FIFO not full interrupt is set to 1
  108. * - Flash memory interface mode enabled
  109. * - Size of the word to be transferred as 8 bit
  110. * This function performs the following actions
  111. * - Disable and clear all the interrupts
  112. * - Enable manual slave select
  113. * - Enable auto start
  114. * - Deselect all the chip select lines
  115. * - Set the size of the word to be transferred as 32 bit
  116. * - Set the little endian mode of TX FIFO and
  117. * - Enable the QSPI controller
  118. */
  119. static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
  120. {
  121. struct zynq_qspi_regs *regs = priv->regs;
  122. u32 confr;
  123. /* Disable QSPI */
  124. writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  125. /* Disable Interrupts */
  126. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
  127. /* Clear the TX and RX threshold reg */
  128. writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
  129. writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
  130. /* Clear the RX FIFO */
  131. while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
  132. readl(&regs->drxr);
  133. /* Clear Interrupts */
  134. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
  135. /* Manual slave select and Auto start */
  136. confr = readl(&regs->cr);
  137. confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
  138. confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
  139. ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
  140. ZYNQ_QSPI_CR_MSTREN_MASK;
  141. writel(confr, &regs->cr);
  142. /* Disable the LQSPI feature */
  143. confr = readl(&regs->lqspicfg);
  144. confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
  145. writel(confr, &regs->lqspicfg);
  146. /* Enable SPI */
  147. writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  148. }
  149. static int zynq_qspi_probe(struct udevice *bus)
  150. {
  151. struct zynq_qspi_plat *plat = dev_get_plat(bus);
  152. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  153. struct clk clk;
  154. unsigned long clock;
  155. int ret;
  156. priv->regs = plat->regs;
  157. priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
  158. ret = clk_get_by_name(bus, "ref_clk", &clk);
  159. if (ret < 0) {
  160. dev_err(bus, "failed to get clock\n");
  161. return ret;
  162. }
  163. clock = clk_get_rate(&clk);
  164. if (IS_ERR_VALUE(clock)) {
  165. dev_err(bus, "failed to get rate\n");
  166. return clock;
  167. }
  168. ret = clk_enable(&clk);
  169. if (ret && ret != -ENOSYS) {
  170. dev_err(bus, "failed to enable clock\n");
  171. return ret;
  172. }
  173. /* init the zynq spi hw */
  174. zynq_qspi_init_hw(priv);
  175. plat->frequency = clock;
  176. plat->speed_hz = plat->frequency / 2;
  177. debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
  178. return 0;
  179. }
  180. /**
  181. * zynq_qspi_read_data - Copy data to RX buffer
  182. * @priv: Pointer to the zynq_qspi_priv structure
  183. * @data: The 32 bit variable where data is stored
  184. * @size: Number of bytes to be copied from data to RX buffer
  185. */
  186. static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
  187. {
  188. u8 byte3;
  189. debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
  190. data, (unsigned)(priv->rx_buf), size);
  191. if (priv->rx_buf) {
  192. switch (size) {
  193. case 1:
  194. *((u8 *)priv->rx_buf) = data;
  195. priv->rx_buf += 1;
  196. break;
  197. case 2:
  198. *((u16 *)priv->rx_buf) = data;
  199. priv->rx_buf += 2;
  200. break;
  201. case 3:
  202. *((u16 *)priv->rx_buf) = data;
  203. priv->rx_buf += 2;
  204. byte3 = (u8)(data >> 16);
  205. *((u8 *)priv->rx_buf) = byte3;
  206. priv->rx_buf += 1;
  207. break;
  208. case 4:
  209. /* Can not assume word aligned buffer */
  210. memcpy(priv->rx_buf, &data, size);
  211. priv->rx_buf += 4;
  212. break;
  213. default:
  214. /* This will never execute */
  215. break;
  216. }
  217. }
  218. priv->bytes_to_receive -= size;
  219. if (priv->bytes_to_receive < 0)
  220. priv->bytes_to_receive = 0;
  221. }
  222. /**
  223. * zynq_qspi_write_data - Copy data from TX buffer
  224. * @priv: Pointer to the zynq_qspi_priv structure
  225. * @data: Pointer to the 32 bit variable where data is to be copied
  226. * @size: Number of bytes to be copied from TX buffer to data
  227. */
  228. static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
  229. u32 *data, u8 size)
  230. {
  231. if (priv->tx_buf) {
  232. switch (size) {
  233. case 1:
  234. *data = *((u8 *)priv->tx_buf);
  235. priv->tx_buf += 1;
  236. *data |= 0xFFFFFF00;
  237. break;
  238. case 2:
  239. *data = *((u16 *)priv->tx_buf);
  240. priv->tx_buf += 2;
  241. *data |= 0xFFFF0000;
  242. break;
  243. case 3:
  244. *data = *((u16 *)priv->tx_buf);
  245. priv->tx_buf += 2;
  246. *data |= (*((u8 *)priv->tx_buf) << 16);
  247. priv->tx_buf += 1;
  248. *data |= 0xFF000000;
  249. break;
  250. case 4:
  251. /* Can not assume word aligned buffer */
  252. memcpy(data, priv->tx_buf, size);
  253. priv->tx_buf += 4;
  254. break;
  255. default:
  256. /* This will never execute */
  257. break;
  258. }
  259. } else {
  260. *data = 0;
  261. }
  262. debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
  263. *data, (u32)priv->tx_buf, size);
  264. priv->bytes_to_transfer -= size;
  265. if (priv->bytes_to_transfer < 0)
  266. priv->bytes_to_transfer = 0;
  267. }
  268. /**
  269. * zynq_qspi_chipselect - Select or deselect the chip select line
  270. * @priv: Pointer to the zynq_qspi_priv structure
  271. * @is_on: Select(1) or deselect (0) the chip select line
  272. */
  273. static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
  274. {
  275. u32 confr;
  276. struct zynq_qspi_regs *regs = priv->regs;
  277. confr = readl(&regs->cr);
  278. if (is_on) {
  279. /* Select the slave */
  280. confr &= ~ZYNQ_QSPI_CR_SS_MASK;
  281. confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
  282. ZYNQ_QSPI_CR_SS_MASK;
  283. } else
  284. /* Deselect the slave */
  285. confr |= ZYNQ_QSPI_CR_SS_MASK;
  286. writel(confr, &regs->cr);
  287. }
  288. /**
  289. * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
  290. * @priv: Pointer to the zynq_qspi_priv structure
  291. * @size: Number of bytes to be copied to fifo
  292. */
  293. static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
  294. {
  295. u32 data = 0;
  296. u32 fifocount = 0;
  297. unsigned len, offset;
  298. struct zynq_qspi_regs *regs = priv->regs;
  299. static const unsigned offsets[4] = {
  300. ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
  301. ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
  302. while ((fifocount < size) &&
  303. (priv->bytes_to_transfer > 0)) {
  304. if (priv->bytes_to_transfer >= 4) {
  305. if (priv->tx_buf) {
  306. memcpy(&data, priv->tx_buf, 4);
  307. priv->tx_buf += 4;
  308. } else {
  309. data = 0;
  310. }
  311. writel(data, &regs->txd0r);
  312. priv->bytes_to_transfer -= 4;
  313. fifocount++;
  314. } else {
  315. /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
  316. if (!(readl(&regs->isr)
  317. & ZYNQ_QSPI_IXR_TXOW_MASK) &&
  318. !priv->rx_buf)
  319. return;
  320. len = priv->bytes_to_transfer;
  321. zynq_qspi_write_data(priv, &data, len);
  322. offset = (priv->rx_buf) ? offsets[0] : offsets[len];
  323. writel(data, &regs->cr + (offset / 4));
  324. }
  325. }
  326. }
  327. /**
  328. * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
  329. * @priv: Pointer to the zynq_qspi structure
  330. *
  331. * This function handles TX empty and Mode Fault interrupts only.
  332. * On TX empty interrupt this function reads the received data from RX FIFO and
  333. * fills the TX FIFO if there is any data remaining to be transferred.
  334. * On Mode Fault interrupt this function indicates that transfer is completed,
  335. * the SPI subsystem will identify the error as the remaining bytes to be
  336. * transferred is non-zero.
  337. *
  338. * returns: 0 for poll timeout
  339. * 1 transfer operation complete
  340. */
  341. static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
  342. {
  343. struct zynq_qspi_regs *regs = priv->regs;
  344. u32 rxindex = 0;
  345. u32 rxcount;
  346. u32 status, timeout;
  347. /* Poll until any of the interrupt status bits are set */
  348. timeout = get_timer(0);
  349. do {
  350. status = readl(&regs->isr);
  351. } while ((status == 0) &&
  352. (get_timer(timeout) < ZYNQ_QSPI_WAIT));
  353. if (status == 0) {
  354. printf("zynq_qspi_irq_poll: Timeout!\n");
  355. return -ETIMEDOUT;
  356. }
  357. writel(status, &regs->isr);
  358. /* Disable all interrupts */
  359. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
  360. if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
  361. (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
  362. /*
  363. * This bit is set when Tx FIFO has < THRESHOLD entries. We have
  364. * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
  365. * is empty
  366. */
  367. rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
  368. rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
  369. while ((rxindex < rxcount) &&
  370. (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
  371. /* Read out the data from the RX FIFO */
  372. u32 data;
  373. data = readl(&regs->drxr);
  374. if (priv->bytes_to_receive >= 4) {
  375. if (priv->rx_buf) {
  376. memcpy(priv->rx_buf, &data, 4);
  377. priv->rx_buf += 4;
  378. }
  379. priv->bytes_to_receive -= 4;
  380. } else {
  381. zynq_qspi_read_data(priv, data,
  382. priv->bytes_to_receive);
  383. }
  384. rxindex++;
  385. }
  386. if (priv->bytes_to_transfer) {
  387. /* There is more data to send */
  388. zynq_qspi_fill_tx_fifo(priv,
  389. ZYNQ_QSPI_RXFIFO_THRESHOLD);
  390. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
  391. } else {
  392. /*
  393. * If transfer and receive is completed then only send
  394. * complete signal
  395. */
  396. if (!priv->bytes_to_receive) {
  397. /* return operation complete */
  398. writel(ZYNQ_QSPI_IXR_ALL_MASK,
  399. &regs->idr);
  400. return 1;
  401. }
  402. }
  403. }
  404. return 0;
  405. }
  406. /**
  407. * zynq_qspi_start_transfer - Initiates the QSPI transfer
  408. * @priv: Pointer to the zynq_qspi_priv structure
  409. *
  410. * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
  411. * transfer to be completed.
  412. *
  413. * returns: Number of bytes transferred in the last transfer
  414. */
  415. static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
  416. {
  417. u32 data = 0;
  418. struct zynq_qspi_regs *regs = priv->regs;
  419. debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
  420. (u32)priv, (u32)priv, priv->len);
  421. priv->bytes_to_transfer = priv->len;
  422. priv->bytes_to_receive = priv->len;
  423. if (priv->len < 4)
  424. zynq_qspi_fill_tx_fifo(priv, priv->len);
  425. else
  426. zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
  427. writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
  428. /* wait for completion */
  429. do {
  430. data = zynq_qspi_irq_poll(priv);
  431. } while (data == 0);
  432. return (priv->len) - (priv->bytes_to_transfer);
  433. }
  434. static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
  435. {
  436. unsigned cs_change = 1;
  437. int status = 0;
  438. while (1) {
  439. /* Select the chip if required */
  440. if (cs_change)
  441. zynq_qspi_chipselect(priv, 1);
  442. cs_change = priv->cs_change;
  443. if (!priv->tx_buf && !priv->rx_buf && priv->len) {
  444. status = -1;
  445. break;
  446. }
  447. /* Request the transfer */
  448. if (priv->len) {
  449. status = zynq_qspi_start_transfer(priv);
  450. priv->is_inst = 0;
  451. }
  452. if (status != priv->len) {
  453. if (status > 0)
  454. status = -EMSGSIZE;
  455. debug("zynq_qspi_transfer:%d len:%d\n",
  456. status, priv->len);
  457. break;
  458. }
  459. status = 0;
  460. if (cs_change)
  461. /* Deselect the chip */
  462. zynq_qspi_chipselect(priv, 0);
  463. break;
  464. }
  465. return status;
  466. }
  467. static int zynq_qspi_claim_bus(struct udevice *dev)
  468. {
  469. struct udevice *bus = dev->parent;
  470. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  471. struct zynq_qspi_regs *regs = priv->regs;
  472. writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  473. return 0;
  474. }
  475. static int zynq_qspi_release_bus(struct udevice *dev)
  476. {
  477. struct udevice *bus = dev->parent;
  478. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  479. struct zynq_qspi_regs *regs = priv->regs;
  480. writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
  481. return 0;
  482. }
  483. static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  484. const void *dout, void *din, unsigned long flags)
  485. {
  486. struct udevice *bus = dev->parent;
  487. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  488. struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
  489. priv->cs = slave_plat->cs;
  490. priv->tx_buf = dout;
  491. priv->rx_buf = din;
  492. priv->len = bitlen / 8;
  493. debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
  494. dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
  495. /*
  496. * Festering sore.
  497. * Assume that the beginning of a transfer with bits to
  498. * transmit must contain a device command.
  499. */
  500. if (dout && flags & SPI_XFER_BEGIN)
  501. priv->is_inst = 1;
  502. else
  503. priv->is_inst = 0;
  504. if (flags & SPI_XFER_END)
  505. priv->cs_change = 1;
  506. else
  507. priv->cs_change = 0;
  508. zynq_qspi_transfer(priv);
  509. return 0;
  510. }
  511. static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
  512. {
  513. struct zynq_qspi_plat *plat = bus->plat;
  514. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  515. struct zynq_qspi_regs *regs = priv->regs;
  516. uint32_t confr;
  517. u8 baud_rate_val = 0;
  518. if (speed > plat->frequency)
  519. speed = plat->frequency;
  520. /* Set the clock frequency */
  521. confr = readl(&regs->cr);
  522. if (speed == 0) {
  523. /* Set baudrate x8, if the freq is 0 */
  524. baud_rate_val = 0x2;
  525. } else if (plat->speed_hz != speed) {
  526. while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
  527. ((plat->frequency /
  528. (2 << baud_rate_val)) > speed))
  529. baud_rate_val++;
  530. plat->speed_hz = speed / (2 << baud_rate_val);
  531. }
  532. confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
  533. confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
  534. writel(confr, &regs->cr);
  535. priv->freq = speed;
  536. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  537. return 0;
  538. }
  539. static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
  540. {
  541. struct zynq_qspi_priv *priv = dev_get_priv(bus);
  542. struct zynq_qspi_regs *regs = priv->regs;
  543. uint32_t confr;
  544. /* Set the SPI Clock phase and polarities */
  545. confr = readl(&regs->cr);
  546. confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
  547. if (mode & SPI_CPHA)
  548. confr |= ZYNQ_QSPI_CR_CPHA_MASK;
  549. if (mode & SPI_CPOL)
  550. confr |= ZYNQ_QSPI_CR_CPOL_MASK;
  551. writel(confr, &regs->cr);
  552. priv->mode = mode;
  553. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  554. return 0;
  555. }
  556. static const struct dm_spi_ops zynq_qspi_ops = {
  557. .claim_bus = zynq_qspi_claim_bus,
  558. .release_bus = zynq_qspi_release_bus,
  559. .xfer = zynq_qspi_xfer,
  560. .set_speed = zynq_qspi_set_speed,
  561. .set_mode = zynq_qspi_set_mode,
  562. };
  563. static const struct udevice_id zynq_qspi_ids[] = {
  564. { .compatible = "xlnx,zynq-qspi-1.0" },
  565. { }
  566. };
  567. U_BOOT_DRIVER(zynq_qspi) = {
  568. .name = "zynq_qspi",
  569. .id = UCLASS_SPI,
  570. .of_match = zynq_qspi_ids,
  571. .ops = &zynq_qspi_ops,
  572. .of_to_plat = zynq_qspi_of_to_plat,
  573. .plat_auto = sizeof(struct zynq_qspi_plat),
  574. .priv_auto = sizeof(struct zynq_qspi_priv),
  575. .probe = zynq_qspi_probe,
  576. };