tegra210_qspi.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NVIDIA Tegra210 QSPI controller driver
  4. *
  5. * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
  6. *
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <spi.h>
  16. #include <fdtdec.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include "tegra_spi.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /* COMMAND1 */
  22. #define QSPI_CMD1_GO BIT(31)
  23. #define QSPI_CMD1_M_S BIT(30)
  24. #define QSPI_CMD1_MODE_MASK GENMASK(1,0)
  25. #define QSPI_CMD1_MODE_SHIFT 28
  26. #define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
  27. #define QSPI_CMD1_CS_SEL_SHIFT 26
  28. #define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
  29. #define QSPI_CMD1_CS_SW_HW BIT(21)
  30. #define QSPI_CMD1_CS_SW_VAL BIT(20)
  31. #define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
  32. #define QSPI_CMD1_IDLE_SDA_SHIFT 18
  33. #define QSPI_CMD1_BIDIR BIT(17)
  34. #define QSPI_CMD1_LSBI_FE BIT(16)
  35. #define QSPI_CMD1_LSBY_FE BIT(15)
  36. #define QSPI_CMD1_BOTH_EN_BIT BIT(14)
  37. #define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
  38. #define QSPI_CMD1_RX_EN BIT(12)
  39. #define QSPI_CMD1_TX_EN BIT(11)
  40. #define QSPI_CMD1_PACKED BIT(5)
  41. #define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
  42. #define QSPI_CMD1_BITLEN_SHIFT 0
  43. /* COMMAND2 */
  44. #define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
  45. #define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
  46. #define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
  47. #define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
  48. /* TRANSFER STATUS */
  49. #define QSPI_XFER_STS_RDY BIT(30)
  50. /* FIFO STATUS */
  51. #define QSPI_FIFO_STS_CS_INACTIVE BIT(31)
  52. #define QSPI_FIFO_STS_FRAME_END BIT(30)
  53. #define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
  54. #define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
  55. #define QSPI_FIFO_STS_ERR BIT(8)
  56. #define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7)
  57. #define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6)
  58. #define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5)
  59. #define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4)
  60. #define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
  61. #define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
  62. #define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
  63. #define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
  64. #define QSPI_TIMEOUT 1000
  65. struct qspi_regs {
  66. u32 command1; /* 000:QSPI_COMMAND1 register */
  67. u32 command2; /* 004:QSPI_COMMAND2 register */
  68. u32 timing1; /* 008:QSPI_CS_TIM1 register */
  69. u32 timing2; /* 00c:QSPI_CS_TIM2 register */
  70. u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
  71. u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
  72. u32 tx_data; /* 018:QSPI_TX_DATA register */
  73. u32 rx_data; /* 01c:QSPI_RX_DATA register */
  74. u32 dma_ctl; /* 020:QSPI_DMA_CTL register */
  75. u32 dma_blk; /* 024:QSPI_DMA_BLK register */
  76. u32 rsvd[56]; /* 028-107 reserved */
  77. u32 tx_fifo; /* 108:QSPI_FIFO1 register */
  78. u32 rsvd2[31]; /* 10c-187 reserved */
  79. u32 rx_fifo; /* 188:QSPI_FIFO2 register */
  80. u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */
  81. };
  82. struct tegra210_qspi_priv {
  83. struct qspi_regs *regs;
  84. unsigned int freq;
  85. unsigned int mode;
  86. int periph_id;
  87. int valid;
  88. int last_transaction_us;
  89. };
  90. static int tegra210_qspi_of_to_plat(struct udevice *bus)
  91. {
  92. struct tegra_spi_plat *plat = bus->plat;
  93. plat->base = dev_read_addr(bus);
  94. plat->periph_id = clock_decode_periph_id(bus);
  95. if (plat->periph_id == PERIPH_ID_NONE) {
  96. debug("%s: could not decode periph id %d\n", __func__,
  97. plat->periph_id);
  98. return -FDT_ERR_NOTFOUND;
  99. }
  100. /* Use 500KHz as a suitable default */
  101. plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
  102. 500000);
  103. plat->deactivate_delay_us = dev_read_u32_default(bus,
  104. "spi-deactivate-delay",
  105. 0);
  106. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  107. __func__, plat->base, plat->periph_id, plat->frequency,
  108. plat->deactivate_delay_us);
  109. return 0;
  110. }
  111. static int tegra210_qspi_probe(struct udevice *bus)
  112. {
  113. struct tegra_spi_plat *plat = dev_get_plat(bus);
  114. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  115. priv->regs = (struct qspi_regs *)plat->base;
  116. struct qspi_regs *regs = priv->regs;
  117. priv->last_transaction_us = timer_get_us();
  118. priv->freq = plat->frequency;
  119. priv->periph_id = plat->periph_id;
  120. debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
  121. priv->periph_id);
  122. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  123. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
  124. /* Set tap delays here, clock change above resets QSPI controller */
  125. u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
  126. (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
  127. writel(reg, &regs->command2);
  128. debug("%s: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
  129. return 0;
  130. }
  131. static int tegra210_qspi_claim_bus(struct udevice *dev)
  132. {
  133. struct udevice *bus = dev->parent;
  134. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  135. struct qspi_regs *regs = priv->regs;
  136. debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
  137. /* Set master mode and sw controlled CS */
  138. setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
  139. (priv->mode << QSPI_CMD1_MODE_SHIFT));
  140. debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
  141. return 0;
  142. }
  143. /**
  144. * Activate the CS by driving it LOW
  145. *
  146. * @param slave Pointer to spi_slave to which controller has to
  147. * communicate with
  148. */
  149. static void spi_cs_activate(struct udevice *dev)
  150. {
  151. struct udevice *bus = dev->parent;
  152. struct tegra_spi_plat *pdata = dev_get_plat(bus);
  153. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  154. /* If it's too soon to do another transaction, wait */
  155. if (pdata->deactivate_delay_us &&
  156. priv->last_transaction_us) {
  157. ulong delay_us; /* The delay completed so far */
  158. delay_us = timer_get_us() - priv->last_transaction_us;
  159. if (delay_us < pdata->deactivate_delay_us)
  160. udelay(pdata->deactivate_delay_us - delay_us);
  161. }
  162. clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  163. }
  164. /**
  165. * Deactivate the CS by driving it HIGH
  166. *
  167. * @param slave Pointer to spi_slave to which controller has to
  168. * communicate with
  169. */
  170. static void spi_cs_deactivate(struct udevice *dev)
  171. {
  172. struct udevice *bus = dev->parent;
  173. struct tegra_spi_plat *pdata = dev_get_plat(bus);
  174. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  175. setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
  176. /* Remember time of this transaction so we can honour the bus delay */
  177. if (pdata->deactivate_delay_us)
  178. priv->last_transaction_us = timer_get_us();
  179. debug("Deactivate CS, bus '%s'\n", bus->name);
  180. }
  181. static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
  182. const void *data_out, void *data_in,
  183. unsigned long flags)
  184. {
  185. struct udevice *bus = dev->parent;
  186. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  187. struct qspi_regs *regs = priv->regs;
  188. u32 reg, tmpdout, tmpdin = 0;
  189. const u8 *dout = data_out;
  190. u8 *din = data_in;
  191. int num_bytes, tm, ret;
  192. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  193. __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
  194. if (bitlen % 8)
  195. return -1;
  196. num_bytes = bitlen / 8;
  197. ret = 0;
  198. /* clear all error status bits */
  199. reg = readl(&regs->fifo_status);
  200. writel(reg, &regs->fifo_status);
  201. /* flush RX/TX FIFOs */
  202. setbits_le32(&regs->fifo_status,
  203. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  204. QSPI_FIFO_STS_TX_FIFO_FLUSH));
  205. tm = QSPI_TIMEOUT;
  206. while ((tm && readl(&regs->fifo_status) &
  207. (QSPI_FIFO_STS_RX_FIFO_FLUSH |
  208. QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
  209. tm--;
  210. udelay(1);
  211. }
  212. if (!tm) {
  213. printf("%s: timeout during QSPI FIFO flush!\n",
  214. __func__);
  215. return -1;
  216. }
  217. /*
  218. * Notes:
  219. * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
  220. * 2. don't set RX_EN and TX_EN yet.
  221. * (SW needs to make sure that while programming the blk_size,
  222. * tx_en and rx_en bits must be zero)
  223. * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
  224. * i.e., both dout and din are not NULL.
  225. */
  226. clrsetbits_le32(&regs->command1,
  227. (QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
  228. QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
  229. (spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
  230. /* set xfer size to 1 block (32 bits) */
  231. writel(0, &regs->dma_blk);
  232. if (flags & SPI_XFER_BEGIN)
  233. spi_cs_activate(dev);
  234. /* handle data in 32-bit chunks */
  235. while (num_bytes > 0) {
  236. int bytes;
  237. tmpdout = 0;
  238. bytes = (num_bytes > 4) ? 4 : num_bytes;
  239. if (dout != NULL) {
  240. memcpy((void *)&tmpdout, (void *)dout, bytes);
  241. dout += bytes;
  242. num_bytes -= bytes;
  243. writel(tmpdout, &regs->tx_fifo);
  244. setbits_le32(&regs->command1, QSPI_CMD1_TX_EN);
  245. }
  246. if (din != NULL)
  247. setbits_le32(&regs->command1, QSPI_CMD1_RX_EN);
  248. /* clear ready bit */
  249. setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY);
  250. clrsetbits_le32(&regs->command1,
  251. QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
  252. (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
  253. /* Need to stabilize other reg bits before GO bit set.
  254. * As per the TRM:
  255. * "For successful operation at various freq combinations,
  256. * a minimum of 4-5 spi_clk cycle delay might be required
  257. * before enabling the PIO or DMA bits. The worst case delay
  258. * calculation can be done considering slowest qspi_clk as
  259. * 1MHz. Based on that 1us delay should be enough before
  260. * enabling PIO or DMA." Padded another 1us for safety.
  261. */
  262. udelay(2);
  263. setbits_le32(&regs->command1, QSPI_CMD1_GO);
  264. udelay(1);
  265. /*
  266. * Wait for SPI transmit FIFO to empty, or to time out.
  267. * The RX FIFO status will be read and cleared last
  268. */
  269. for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
  270. u32 fifo_status, xfer_status;
  271. xfer_status = readl(&regs->xfer_status);
  272. if (!(xfer_status & QSPI_XFER_STS_RDY))
  273. continue;
  274. fifo_status = readl(&regs->fifo_status);
  275. if (fifo_status & QSPI_FIFO_STS_ERR) {
  276. debug("%s: got a fifo error: ", __func__);
  277. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
  278. debug("tx FIFO overflow ");
  279. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
  280. debug("tx FIFO underrun ");
  281. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
  282. debug("rx FIFO overflow ");
  283. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
  284. debug("rx FIFO underrun ");
  285. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
  286. debug("tx FIFO full ");
  287. if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
  288. debug("tx FIFO empty ");
  289. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
  290. debug("rx FIFO full ");
  291. if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
  292. debug("rx FIFO empty ");
  293. debug("\n");
  294. break;
  295. }
  296. if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
  297. tmpdin = readl(&regs->rx_fifo);
  298. if (din != NULL) {
  299. memcpy(din, &tmpdin, bytes);
  300. din += bytes;
  301. num_bytes -= bytes;
  302. }
  303. }
  304. break;
  305. }
  306. if (tm >= QSPI_TIMEOUT)
  307. ret = tm;
  308. /* clear ACK RDY, etc. bits */
  309. writel(readl(&regs->fifo_status), &regs->fifo_status);
  310. }
  311. if (flags & SPI_XFER_END)
  312. spi_cs_deactivate(dev);
  313. debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
  314. __func__, tmpdin, readl(&regs->fifo_status));
  315. if (ret) {
  316. printf("%s: timeout during SPI transfer, tm %d\n",
  317. __func__, ret);
  318. return -1;
  319. }
  320. return ret;
  321. }
  322. static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
  323. {
  324. struct tegra_spi_plat *plat = bus->plat;
  325. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  326. if (speed > plat->frequency)
  327. speed = plat->frequency;
  328. priv->freq = speed;
  329. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  330. return 0;
  331. }
  332. static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
  333. {
  334. struct tegra210_qspi_priv *priv = dev_get_priv(bus);
  335. priv->mode = mode;
  336. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  337. return 0;
  338. }
  339. static const struct dm_spi_ops tegra210_qspi_ops = {
  340. .claim_bus = tegra210_qspi_claim_bus,
  341. .xfer = tegra210_qspi_xfer,
  342. .set_speed = tegra210_qspi_set_speed,
  343. .set_mode = tegra210_qspi_set_mode,
  344. /*
  345. * cs_info is not needed, since we require all chip selects to be
  346. * in the device tree explicitly
  347. */
  348. };
  349. static const struct udevice_id tegra210_qspi_ids[] = {
  350. { .compatible = "nvidia,tegra210-qspi" },
  351. { }
  352. };
  353. U_BOOT_DRIVER(tegra210_qspi) = {
  354. .name = "tegra210-qspi",
  355. .id = UCLASS_SPI,
  356. .of_match = tegra210_qspi_ids,
  357. .ops = &tegra210_qspi_ops,
  358. .of_to_plat = tegra210_qspi_of_to_plat,
  359. .plat_auto = sizeof(struct tegra_spi_plat),
  360. .priv_auto = sizeof(struct tegra210_qspi_priv),
  361. .per_child_auto = sizeof(struct spi_slave),
  362. .probe = tegra210_qspi_probe,
  363. };