pic32_spi.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Microchip PIC32 SPI controller driver.
  4. *
  5. * Copyright (c) 2015, Microchip Technology Inc.
  6. * Purna Chandra Mandal <purna.mandal@microchip.com>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <linux/bitops.h>
  13. #include <linux/compat.h>
  14. #include <malloc.h>
  15. #include <spi.h>
  16. #include <asm/types.h>
  17. #include <asm/io.h>
  18. #include <asm/gpio.h>
  19. #include <dt-bindings/clock/microchip,clock.h>
  20. #include <mach/pic32.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. /* PIC32 SPI controller registers */
  23. struct pic32_reg_spi {
  24. struct pic32_reg_atomic ctrl;
  25. struct pic32_reg_atomic status;
  26. struct pic32_reg_atomic buf;
  27. struct pic32_reg_atomic baud;
  28. struct pic32_reg_atomic ctrl2;
  29. };
  30. /* Bit fields in SPI Control Register */
  31. #define PIC32_SPI_CTRL_MSTEN BIT(5) /* Enable SPI Master */
  32. #define PIC32_SPI_CTRL_CKP BIT(6) /* active low */
  33. #define PIC32_SPI_CTRL_CKE BIT(8) /* Tx on falling edge */
  34. #define PIC32_SPI_CTRL_SMP BIT(9) /* Rx at middle or end of tx */
  35. #define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
  36. #define PIC32_SPI_CTRL_BPW_8 0x0
  37. #define PIC32_SPI_CTRL_BPW_16 0x1
  38. #define PIC32_SPI_CTRL_BPW_32 0x2
  39. #define PIC32_SPI_CTRL_BPW_SHIFT 10
  40. #define PIC32_SPI_CTRL_ON BIT(15) /* Macro enable */
  41. #define PIC32_SPI_CTRL_ENHBUF BIT(16) /* Enable enhanced buffering */
  42. #define PIC32_SPI_CTRL_MCLKSEL BIT(23) /* Select SPI Clock src */
  43. #define PIC32_SPI_CTRL_MSSEN BIT(28) /* SPI macro will drive SS */
  44. #define PIC32_SPI_CTRL_FRMEN BIT(31) /* Enable framing mode */
  45. /* Bit fields in SPI Status Register */
  46. #define PIC32_SPI_STAT_RX_OV BIT(6) /* err, s/w needs to clear */
  47. #define PIC32_SPI_STAT_TF_LVL_MASK 0x1f
  48. #define PIC32_SPI_STAT_TF_LVL_SHIFT 16
  49. #define PIC32_SPI_STAT_RF_LVL_MASK 0x1f
  50. #define PIC32_SPI_STAT_RF_LVL_SHIFT 24
  51. /* Bit fields in SPI Baud Register */
  52. #define PIC32_SPI_BAUD_MASK 0x1ff
  53. struct pic32_spi_priv {
  54. struct pic32_reg_spi *regs;
  55. u32 fifo_depth; /* FIFO depth in bytes */
  56. u32 fifo_n_word; /* FIFO depth in words */
  57. struct gpio_desc cs_gpio;
  58. /* Current SPI slave specific */
  59. ulong clk_rate;
  60. u32 speed_hz; /* spi-clk rate */
  61. int mode;
  62. /* Current message/transfer state */
  63. const void *tx;
  64. const void *tx_end;
  65. const void *rx;
  66. const void *rx_end;
  67. u32 len;
  68. /* SPI FiFo accessor */
  69. void (*rx_fifo)(struct pic32_spi_priv *);
  70. void (*tx_fifo)(struct pic32_spi_priv *);
  71. };
  72. static inline void pic32_spi_enable(struct pic32_spi_priv *priv)
  73. {
  74. writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set);
  75. }
  76. static inline void pic32_spi_disable(struct pic32_spi_priv *priv)
  77. {
  78. writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr);
  79. }
  80. static inline u32 pic32_spi_rx_fifo_level(struct pic32_spi_priv *priv)
  81. {
  82. u32 sr = readl(&priv->regs->status.raw);
  83. return (sr >> PIC32_SPI_STAT_RF_LVL_SHIFT) & PIC32_SPI_STAT_RF_LVL_MASK;
  84. }
  85. static inline u32 pic32_spi_tx_fifo_level(struct pic32_spi_priv *priv)
  86. {
  87. u32 sr = readl(&priv->regs->status.raw);
  88. return (sr >> PIC32_SPI_STAT_TF_LVL_SHIFT) & PIC32_SPI_STAT_TF_LVL_MASK;
  89. }
  90. /* Return the max entries we can fill into tx fifo */
  91. static u32 pic32_tx_max(struct pic32_spi_priv *priv, int n_bytes)
  92. {
  93. u32 tx_left, tx_room, rxtx_gap;
  94. tx_left = (priv->tx_end - priv->tx) / n_bytes;
  95. tx_room = priv->fifo_n_word - pic32_spi_tx_fifo_level(priv);
  96. rxtx_gap = (priv->rx_end - priv->rx) - (priv->tx_end - priv->tx);
  97. rxtx_gap /= n_bytes;
  98. return min3(tx_left, tx_room, (u32)(priv->fifo_n_word - rxtx_gap));
  99. }
  100. /* Return the max entries we should read out of rx fifo */
  101. static u32 pic32_rx_max(struct pic32_spi_priv *priv, int n_bytes)
  102. {
  103. u32 rx_left = (priv->rx_end - priv->rx) / n_bytes;
  104. return min_t(u32, rx_left, pic32_spi_rx_fifo_level(priv));
  105. }
  106. #define BUILD_SPI_FIFO_RW(__name, __type, __bwl) \
  107. static void pic32_spi_rx_##__name(struct pic32_spi_priv *priv) \
  108. { \
  109. __type val; \
  110. u32 mx = pic32_rx_max(priv, sizeof(__type)); \
  111. \
  112. for (; mx; mx--) { \
  113. val = read##__bwl(&priv->regs->buf.raw); \
  114. if (priv->rx_end - priv->len) \
  115. *(__type *)(priv->rx) = val; \
  116. priv->rx += sizeof(__type); \
  117. } \
  118. } \
  119. \
  120. static void pic32_spi_tx_##__name(struct pic32_spi_priv *priv) \
  121. { \
  122. __type val; \
  123. u32 mx = pic32_tx_max(priv, sizeof(__type)); \
  124. \
  125. for (; mx ; mx--) { \
  126. val = (__type) ~0U; \
  127. if (priv->tx_end - priv->len) \
  128. val = *(__type *)(priv->tx); \
  129. write##__bwl(val, &priv->regs->buf.raw); \
  130. priv->tx += sizeof(__type); \
  131. } \
  132. }
  133. BUILD_SPI_FIFO_RW(byte, u8, b);
  134. BUILD_SPI_FIFO_RW(word, u16, w);
  135. BUILD_SPI_FIFO_RW(dword, u32, l);
  136. static int pic32_spi_set_word_size(struct pic32_spi_priv *priv,
  137. unsigned int wordlen)
  138. {
  139. u32 bits_per_word;
  140. u32 val;
  141. switch (wordlen) {
  142. case 8:
  143. priv->rx_fifo = pic32_spi_rx_byte;
  144. priv->tx_fifo = pic32_spi_tx_byte;
  145. bits_per_word = PIC32_SPI_CTRL_BPW_8;
  146. break;
  147. case 16:
  148. priv->rx_fifo = pic32_spi_rx_word;
  149. priv->tx_fifo = pic32_spi_tx_word;
  150. bits_per_word = PIC32_SPI_CTRL_BPW_16;
  151. break;
  152. case 32:
  153. priv->rx_fifo = pic32_spi_rx_dword;
  154. priv->tx_fifo = pic32_spi_tx_dword;
  155. bits_per_word = PIC32_SPI_CTRL_BPW_32;
  156. break;
  157. default:
  158. printf("pic32-spi: unsupported wordlen\n");
  159. return -EINVAL;
  160. }
  161. /* set bits-per-word */
  162. val = readl(&priv->regs->ctrl.raw);
  163. val &= ~(PIC32_SPI_CTRL_BPW_MASK << PIC32_SPI_CTRL_BPW_SHIFT);
  164. val |= bits_per_word << PIC32_SPI_CTRL_BPW_SHIFT;
  165. writel(val, &priv->regs->ctrl.raw);
  166. /* calculate maximum number of words fifo can hold */
  167. priv->fifo_n_word = DIV_ROUND_UP(priv->fifo_depth, wordlen / 8);
  168. return 0;
  169. }
  170. static int pic32_spi_claim_bus(struct udevice *slave)
  171. {
  172. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  173. /* enable chip */
  174. pic32_spi_enable(priv);
  175. return 0;
  176. }
  177. static int pic32_spi_release_bus(struct udevice *slave)
  178. {
  179. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  180. /* disable chip */
  181. pic32_spi_disable(priv);
  182. return 0;
  183. }
  184. static void spi_cs_activate(struct pic32_spi_priv *priv)
  185. {
  186. if (!dm_gpio_is_valid(&priv->cs_gpio))
  187. return;
  188. dm_gpio_set_value(&priv->cs_gpio, 1);
  189. }
  190. static void spi_cs_deactivate(struct pic32_spi_priv *priv)
  191. {
  192. if (!dm_gpio_is_valid(&priv->cs_gpio))
  193. return;
  194. dm_gpio_set_value(&priv->cs_gpio, 0);
  195. }
  196. static int pic32_spi_xfer(struct udevice *slave, unsigned int bitlen,
  197. const void *tx_buf, void *rx_buf,
  198. unsigned long flags)
  199. {
  200. struct dm_spi_slave_plat *slave_plat;
  201. struct udevice *bus = slave->parent;
  202. struct pic32_spi_priv *priv;
  203. int len = bitlen / 8;
  204. int ret = 0;
  205. ulong tbase;
  206. priv = dev_get_priv(bus);
  207. slave_plat = dev_get_parent_plat(slave);
  208. debug("spi_xfer: bus:%i cs:%i flags:%lx\n",
  209. dev_seq(bus), slave_plat->cs, flags);
  210. debug("msg tx %p, rx %p submitted of %d byte(s)\n",
  211. tx_buf, rx_buf, len);
  212. /* assert cs */
  213. if (flags & SPI_XFER_BEGIN)
  214. spi_cs_activate(priv);
  215. /* set current transfer information */
  216. priv->tx = tx_buf;
  217. priv->rx = rx_buf;
  218. priv->tx_end = priv->tx + len;
  219. priv->rx_end = priv->rx + len;
  220. priv->len = len;
  221. /* transact by polling */
  222. tbase = get_timer(0);
  223. for (;;) {
  224. priv->tx_fifo(priv);
  225. priv->rx_fifo(priv);
  226. /* received sufficient data */
  227. if (priv->rx >= priv->rx_end) {
  228. ret = 0;
  229. break;
  230. }
  231. if (get_timer(tbase) > 5 * CONFIG_SYS_HZ) {
  232. printf("pic32_spi: error, xfer timedout.\n");
  233. flags |= SPI_XFER_END;
  234. ret = -ETIMEDOUT;
  235. break;
  236. }
  237. }
  238. /* deassert cs */
  239. if (flags & SPI_XFER_END)
  240. spi_cs_deactivate(priv);
  241. return ret;
  242. }
  243. static int pic32_spi_set_speed(struct udevice *bus, uint speed)
  244. {
  245. struct pic32_spi_priv *priv = dev_get_priv(bus);
  246. u32 div;
  247. debug("%s: %s, speed %u\n", __func__, bus->name, speed);
  248. /* div = [clk_in / (2 * spi_clk)] - 1 */
  249. div = (priv->clk_rate / 2 / speed) - 1;
  250. div &= PIC32_SPI_BAUD_MASK;
  251. writel(div, &priv->regs->baud.raw);
  252. priv->speed_hz = speed;
  253. return 0;
  254. }
  255. static int pic32_spi_set_mode(struct udevice *bus, uint mode)
  256. {
  257. struct pic32_spi_priv *priv = dev_get_priv(bus);
  258. u32 val;
  259. debug("%s: %s, mode %d\n", __func__, bus->name, mode);
  260. /* set spi-clk mode */
  261. val = readl(&priv->regs->ctrl.raw);
  262. /* HIGH when idle */
  263. if (mode & SPI_CPOL)
  264. val |= PIC32_SPI_CTRL_CKP;
  265. else
  266. val &= ~PIC32_SPI_CTRL_CKP;
  267. /* TX at idle-to-active clk transition */
  268. if (mode & SPI_CPHA)
  269. val &= ~PIC32_SPI_CTRL_CKE;
  270. else
  271. val |= PIC32_SPI_CTRL_CKE;
  272. /* RX at end of tx */
  273. val |= PIC32_SPI_CTRL_SMP;
  274. writel(val, &priv->regs->ctrl.raw);
  275. priv->mode = mode;
  276. return 0;
  277. }
  278. static int pic32_spi_set_wordlen(struct udevice *slave, unsigned int wordlen)
  279. {
  280. struct pic32_spi_priv *priv = dev_get_priv(slave->parent);
  281. return pic32_spi_set_word_size(priv, wordlen);
  282. }
  283. static void pic32_spi_hw_init(struct pic32_spi_priv *priv)
  284. {
  285. u32 val;
  286. /* disable module */
  287. pic32_spi_disable(priv);
  288. val = readl(&priv->regs->ctrl);
  289. /* enable enhanced fifo of 128bit deep */
  290. val |= PIC32_SPI_CTRL_ENHBUF;
  291. priv->fifo_depth = 16;
  292. /* disable framing mode */
  293. val &= ~PIC32_SPI_CTRL_FRMEN;
  294. /* enable master mode */
  295. val |= PIC32_SPI_CTRL_MSTEN;
  296. /* select clk source */
  297. val &= ~PIC32_SPI_CTRL_MCLKSEL;
  298. /* set manual /CS mode */
  299. val &= ~PIC32_SPI_CTRL_MSSEN;
  300. writel(val, &priv->regs->ctrl);
  301. /* clear rx overflow indicator */
  302. writel(PIC32_SPI_STAT_RX_OV, &priv->regs->status.clr);
  303. }
  304. static int pic32_spi_probe(struct udevice *bus)
  305. {
  306. struct pic32_spi_priv *priv = dev_get_priv(bus);
  307. struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
  308. int node = dev_of_offset(bus);
  309. struct udevice *clkdev;
  310. fdt_addr_t addr;
  311. fdt_size_t size;
  312. int ret;
  313. debug("%s: %d, bus: %i\n", __func__, __LINE__, dev_seq(bus));
  314. addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
  315. if (addr == FDT_ADDR_T_NONE)
  316. return -EINVAL;
  317. priv->regs = ioremap(addr, size);
  318. if (!priv->regs)
  319. return -EINVAL;
  320. dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
  321. 250000000);
  322. /* get clock rate */
  323. ret = clk_get_by_index(bus, 0, &clkdev);
  324. if (ret < 0) {
  325. printf("pic32-spi: error, clk not found\n");
  326. return ret;
  327. }
  328. priv->clk_rate = clk_get_periph_rate(clkdev, ret);
  329. /* initialize HW */
  330. pic32_spi_hw_init(priv);
  331. /* set word len */
  332. pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN);
  333. /* PIC32 SPI controller can automatically drive /CS during transfer
  334. * depending on fifo fill-level. /CS will stay asserted as long as
  335. * TX fifo is non-empty, else will be deasserted confirming completion
  336. * of the ongoing transfer. To avoid this sort of error we will drive
  337. * /CS manually by toggling cs-gpio pins.
  338. */
  339. ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0,
  340. &priv->cs_gpio, GPIOD_IS_OUT);
  341. if (ret) {
  342. printf("pic32-spi: error, cs-gpios not found\n");
  343. return ret;
  344. }
  345. return 0;
  346. }
  347. static const struct dm_spi_ops pic32_spi_ops = {
  348. .claim_bus = pic32_spi_claim_bus,
  349. .release_bus = pic32_spi_release_bus,
  350. .xfer = pic32_spi_xfer,
  351. .set_speed = pic32_spi_set_speed,
  352. .set_mode = pic32_spi_set_mode,
  353. .set_wordlen = pic32_spi_set_wordlen,
  354. };
  355. static const struct udevice_id pic32_spi_ids[] = {
  356. { .compatible = "microchip,pic32mzda-spi" },
  357. { }
  358. };
  359. U_BOOT_DRIVER(pic32_spi) = {
  360. .name = "pic32_spi",
  361. .id = UCLASS_SPI,
  362. .of_match = pic32_spi_ids,
  363. .ops = &pic32_spi_ops,
  364. .priv_auto = sizeof(struct pic32_spi_priv),
  365. .probe = pic32_spi_probe,
  366. };